基于编译时插桩的浮点异常检测方法

浮点数是实数的有限精度编码,在进行浮点计算时,可能会导致不精确或者异常的结果,因此实现有效的浮点异常检测方法很重要。现有异常检测方法不面向浮点数学函数,由此提出了一种面向浮点数学函数的异常检测方法。该方法依据IEEE-754标准中定义的上溢出、下溢出、被零除、无效操作和不精确5类异常,并结合申威高性能数学函数库中使用的浮点控制寄存器FPCR和IEEE-754标准定义的浮点异常产生条件的相关理论,通过将异常类型和浮点运算指令进行对应分类,在程序编译时进行插桩以检测出浮点数学函数中出现的异常,同时记录代码覆盖率。最后将该方法应用于数学函数库,对库中100多个浮点数学函数进行了测试实验。实验结果表明,该浮点异常检测方法能够有效检测各类异常。     

多核浮点非线性运算协处理器的设计与实现

在载人航天飞船的终端仪器仪表设计中,处理算法中的浮点非线性运算常采用库函数实现,但软件实现非线性函数执行速度慢,限制了浮点算法的应用。为此,针对航天领域处理器不支持非线性函数运算的情况以及浮点算法执行速度慢的问题,提出一种多核并行执行浮点非线性运算处理方法,利用现场可编程门阵列内部并行架构带来的低延迟特性来提高非线性浮点运算的速度。仿真实验结果表明,该方法可计算有限定义域范围内的浮点非线性函数,有效提高浮点运算的执行速度。     

支持超越函数的浮点运算单元的设计与实现

介绍自主设计的龙腾C2微处理器中浮点运算单元的设计与实现.该处理器与Intel 80486DX4指令系统兼容,支持IEEE 754标准扩展精度的浮点基本函数和超越函数运算.介绍了浮点运算单元的结构,分析了实现超越函数的高精度CORDIC算法的流程,讨论了实现浮点超越函数运算的数据通路和控制通路结构,并给出了仿真结果和精度评估结果.仿真和分析的结果表明,浮点运算单元的设计满足龙腾C2微处理器的设计要求.     

基于VHDL的浮点算法研究

浮点运算是数字信号处理中最基本的运算,但因为现行EDA软件没有提供浮点运算功能,使其在FPGA中的实现却是个棘手问题.文中提出了一种基于VHDL的高精度浮点算法,并以9位实序列为例,通过浮点数表示、对阶操作、尾数运算以及规格化处理等步骤高效并准确地实现浮点加/减法、乘法、除法以及平方根等运算,最后在FPGA中下载并实现了上述浮点运算,并给出测试结果.测试数据表明:所设计的浮点算法在其浮点数位宽所对应的精度范围内,可以在FPGA上成功地实现包含加、减、乘、除及求平方根等各种浮点运算.     

支持超越函数的浮点运算单元的设计与实现

介绍自主设计的龙腾C2微处理器中浮点运算单元的设计与实现。该处理器与Intel80486DX4指令系统兼容,支持IEEE754标准扩展精度的浮点基本函数和超越函数运算。介绍了浮点运算单元的结构,分析了实现超越函数的高精度CORDIC算法的流程,讨论了实现浮点超越函数运算的数据通路和控制通路结构,并给出了仿真结果和精度评估结果。仿真和分析的结果表明,浮点运算单元的设计满足龙腾C2微处理器的设计要求。     

定点DSP C55X实现浮点相关运算

引言 DSP结构可以分为定点和浮点型两种.其中,定点型DSP可以实现整数、小数和特定的指数运算,它具有运算速度快、占用资源少、成本低等特点;灵活地使用定点型DSP进行浮点运算能够提高运算的效率.目前对定点DSP结构支持下的浮点需求也在不断增长,主要原因是: 实现算法的代码往往是采用C/C 编写,如果其中有标准型的浮点数据处理,又必须采用定点DSP器件,那么就需要将浮点算法转换成定点格式进行运算.同时,定点DSP结构下的浮点运算有很强的可行性,因为C语言和汇编语言分别具有可移植性强和运算效率高的特点,因此在定点DSP中结合C语言和汇编语言的混合编程技术将大大提高编程的灵活度,以及运算速度.     

面向高可信软件的整数溢出错误的自动化测试

面向高可信软件提出了一种二进制级高危整数溢出错误的全自动测试方法(dynamic automatic integer-overflow detection and testing,简称DAIDT).该方法无需任何源码甚至是符号表支持,即可对二进制应用程序进行全面测试,并自动发现高危整数溢出错误.在理论上形式化证明了该技术对高危整数溢出错误测试与发掘的无漏报性、零误报性与错误可重现特性.为了验证该方法的有效性,实现了IntHunter原型系统.IntHunter对3个最新版本的高可信应用程序(微软公司Windows 2003和2000 Server的WINS服务、百度公司的即时通讯软件BaiDu Hi)分别进行了24小时测试,共发现了4个高危整数溢出错误.其中3个错误可导致任意代码执行,其中两个由微软安全响应中心分配漏洞编号CVE-2009-1923,CVE-2009-1924,另一个由百度公司分配漏洞编号CVE-2008-6444.     

基于申威1621数学库中的非精确结果异常处理

由于国产申威基础数学库其功能、接口需要与单机编译器glibc libm库保持一致, 将基础数学库集成到glibc 中进行功能测试时, 检测出有部分函数的INE异常需要消除. 针对这种情况, 首先研究了glibc 数学库的异常检测机制; 然后针对基础数学库中数值函数的INE异常进行分析和优化, 提出一种测试数据集分段处理的方法, 最后消除了这种INE异常. 测试表明, 测试数据集分段处理的方法能够有效解决数值函数的INE异常, 相对于之前的异常处理方法, 使用本方法后平均性能加速比达到148%.     

TL860图形加速板的设计与实现

ＩＮＴＥＬ公司的ｉ８６０芯片是一种６４位的ＲＩＳＣ超级微处理器，鉴于其强大的浮点运算、整数浮点并行运算及图形处理能力，一直为高性能图形系统设计者们所青睐。这里，我们展示了一种基于ｉ８６０ＸＲ芯片的微机图形加速板的设计和实现过程。本文阐述了这种加速板的硬件和软件设计的结构和特点，并提供了该板实现后进行的整数、浮点和图形运算性能测试的结果。本项目是浙江省“八五”攻关项目，已于１９９４年９月通过科委鉴定     

面向移动终端的统计机器翻译解码定点化方法

面向移动终端的统计机器翻译需求越来越多,但无浮点运算单元的处理器限制了翻译速度。该文提出了一种对统计机器翻译解码运算的定点化运算方法,缓解了无浮点运算单元的处理器对翻译速度的影响。基于PC和移动终端的实验表明,在保证翻译质量的情况下,利用定点处理浮点运算的解码器的运算速度较编译器模拟的浮点运算速度提高135.6%。因此,该方法可以有效地提高浮点运算能力薄弱的移动终端统计机器翻译速度。     

迁移工作流系统中的工作位置异常处理模型

针对迁移工作流异常的本地特性和工作位置的体系结构,提出一种基于事件-条件-动作(ECA)规则和案例推理(CBR)的工作位置异常处理模型。该模型采取主动检测和异常检测混合的检测技术,利用本地异常规则库实现工作位置异常处理。应用结果表明,该模型增强了不可预测异常、可预测异常的处理能力。     

异常处理——一种提高软件健壮性的方法

Exception handling is a technique that tests and handles exception events. Unlike the traditional methods that usually deal with exceptions at later design and implementation phases and easily result in many problems, we emphasis that sufficient attention should be paid to software exception handling during the development of the soft-ware requirements definition. By enforcing this policy through all phases of software development, the level of ro-bustness can be improved considerably. In this paper, the concepts of exception handling are firstly introduced, then the methods of exception handling are discussed, all kinds of exception handling methods and tools are also compared.The current problems and future directions are analyzed at the end of the paper.     

Formalization of Fixed-Point Arithmetic in HOL

This paper addresses the formalization in higher-order logic of fixed-point arithmetic. We encoded the fixed-point number system and specified the different quantization modes in fixed-point arithmetic such as the directed and even quantization modes. We also considered the formalization of exceptions detection and their handling like overflow and invalid operation. An error analysis is then performed to check the correctness of the quantized result after carrying out basic arithmetic operations, such as addition, subtraction, multiplication and division against their mathematical counterparts. Finally, we showed by an example how this formalization can be used to enable the verification of the transition from floating-point to fixed-point algorithmic level in the signal processing design flow.     

Interval operations involving NaNs

This paper considers some aspects of the implementation of interval arithmetic built on IEEE floating-point systems. Interval operations and functions on arguments involving special elements, Not-a-Numbers (NaNs) and signed zero, supported by the IEEE floating-point formats are discussed. A simple model of interval exceptions and their handling in IEEE non-trapping mode is proposed and interval operations on arguments involving NaNs are defined. Based on the floating-point exceptions and their handling, the proposed model provide consistency between interval and IEEE arithmetics.     

A rule-based approach to proactive exception handling in business processes

Effectively handling exceptions in business process is an important capability of enterprises in the current global market environment, since their business processes are becoming more complex. Effective exception handling requires systematic support for the entire scope of exception handling: from exception prediction to exception prevention, and from exception detection to exception resolution. Most existing research approaches to exception handling in business process management and workflow areas have focused on reactive exception handling which resolves exceptions only after their occurrences. Therefore, a proactive exception handling approach is required to predict and prevent business process exceptions as early as possible before they occur, and detect and resolve exceptions as soon as possible after they occur. This paper presents comprehensive behavioral, functional, and informational requirements for proactive exception handling from the lifecycle perspective. Then, it proposes a rule language for proactive exception handling based on the requirements. The proposed rule language will enable effective and flexible exception handling by providing the information required for the entire scope of exception handling, especially, for exception prediction and prevention. Finally, the paper illustrates and validates the rule language with an example of exception prevention and a prototype system.     

基于异常检测和处理的动态适应性工作流

异常的检测和处理是工作流系统执行过程中必须解决的关键性问题之一.给出了异常的分类,并给出了异常自身及其处理方法的形式化描述;实现了利用消息传递机制作为异常的检测方法,并结合异常适应库来提供异常处理的执行策略和处理措施;通过为相应的措施设计特定的操作原语,从而为其转变为实际的编码提供了可能.     

Exception handlers in functional programming languages

Constructs for expressing exception handling can greatly help to avoid clutter in code by allowing the programmer to separate the code to handle unusual situations from the code for the normal case. The author proposes a new approach to embed exception handlers in functional languages. The proposed approach discards the conventional view of treating exceptions, as a means of effecting a control transfer; instead, exceptions are used to change the state of an object. The two types of exceptions, terminate and resume, are treated differently. A terminate exception, when raised, is viewed as shielding the input object. On the other hand, a resume exception designates the input object as curable and requires the immediate application of a handler function. This approach enables the clean semantics of functions raising exceptions without associating any implementation restriction and without loss of the referential transparency and the commutativity properties of functions     

Exception handling analysis and transformation using fault injection: Study of resilience against unanticipated exceptions

ContextIn software, there are the error cases that are anticipated at specification and design time, those encountered at development and testing time, and those that were never anticipated before happening in production. Is it possible to learn from the anticipated errors during design to analyze and improve the resilience against the unanticipated ones in production?ObjectiveIn this paper, we aim at analyzing and improving how software handles unanticipated exceptions. The first objective is to set up contracts about exception handling and a way to assess them automatically. The second one is to improve the resilience capabilities of software by transforming the source code.MethodWe devise an algorithm, called short-circuit testing, which injects exceptions during test suite execution so as to simulate unanticipated errors. It is a kind of fault-injection techniques dedicated to exception-handling. This algorithm collects data that is used for verifying two formal contracts that capture two resilience properties w.r.t. exceptions: the source-independence and pure-resilience contracts. Then we propose a code modification technique, called “catch-stretching” which allows error-recovery code (of the form of catch blocks) to be more resilient.ResultsOur evaluation is performed on 9 open-source software applications and consists in analyzing 241 catch blocks executed during test suite execution. Our results show that 101/214 of them (47%) expose resilience properties as defined by our exception contracts and that 84/214 of them (39%) can be transformed to be more resilient.ConclusionOur work shows that it is possible to reason on software resilience by injecting exceptions during test suite execution. The collected information allows us to apply one source code transformation that improves the resilience against unanticipated exceptions. This works best if the test suite exercises the exceptional programming language constructs in many different scenarios.     

The TMS390C602A floating-point coprocessor for Sparc systems

A recent Sparc (scalable processor architecture) processor consists of a two-chip configuration, containing the TMS390C601 integer unit (IU) and the TMS390C602A floating-point unit (FPU). The second device, an innovative coprocessor that lets the processor execute single- or double-precision floating-point instructions concurrently with IU operations is described. Dedicated floating-point hardware in the FPU increases the performance of the system. Running at clock periods as small as 20 ns, the chip should deliver 5.5 million double-precision floating-point operations per second under the Linpack benchmark (50-MHz clock rate). The FPU provides single- and double-precision arithmetic functions: addition, subtraction, multiplication, division, square root, compare, and convert. To minimize its math unit's latency, the FPU uses a highly parallel architecture requiring separate math units to optimize additions and multiplications. Traps stop the execution of a program to jump to software routine for handling data-dependent errors or to execute instructions not implemented in the hardware. Benchmark results are presented