Board-level optical-to-electrical signal distribution at 10 gb/s

An opto/electrical prototype for on-board optical-to-electrical signal broadcasting operating at 10 Gb/s per channel over an interconnect distance of 10 cm is demonstrated. An improved 1/spl times/4 multimode interference (MMI) splitter at 1550 nm with linearly tapered output facet is heterogeneously integrated with four p-i-n photodetectors (PDs) on a silicon (Si) bench. The Si bench itself is hybrid integrated onto an FR-4 printed-circuit board with four receiver channels. A novel fabrication/integration approach demonstrates the simultaneous alignment between the four waveguides and the four PDs during the MMI fabrication process. The entire system is fully functional at 10 Gb/s.     

Electronic precompensation of intrachannel nonlinearities at 40 gb/s

Digital electronic precompensation of intrachannel nonlinearities is studied in a transmission system which consists of 100% dispersion-compensated spans. Different Mach-Zehnder-based transmitter structures are compared. Simulation results demonstrate that using a triple Mach-Zehnder modulator achieves effective compensation of intrachannel nonlinear effects at large launch powers.     

All-optical logic xor gate at 80 gb/s using SOA-MZI-DI

All-optical xor operation has been demonstrated using a semiconductor optical amplifier Mach-Zehnder interferometer (SOA-MZI) and delayed interferometer (DI) at 80 Gb/s. The DI is based on a polarization maintaining loop (PML) mirror. The results show using the PML-DI in series with the SOA-MZI improves the pulse quality of the xor result.     

100×100 optoelectronic cross-connect interconnects usingOPTOBUS

This paper demonstrates an OPTOBUS-based fully packaged optoelectronic cross-connect interconnect technique for data communication applications. Optical insertion loss of the compact 100×100 cross-connect interconnect device ranges from 0.4 to 2.9 dB among all possible connections. Optical transmissions with bit error rate (BER) of >10^-12 can be maintained at per channel bandwidth of 900 Mb/s. The system is expected to have an aggregated interconnect bandwidth near 100 Gb/s when being fully connected with the OPTOBUS chips     

Integrated tandem traveling-wave electroabsorption modulators for >100 Gbit/s OTDM applications

Integrated tandem traveling-wave electroabsorption modulators are demonstrated as high-speed optical short pulse generators and demultiplexers for >100 Gbit/s optical time-division-multiplexed systems. The tandem significantly increases the extinction ratio and further compresses the optical pulses in comparison to a single modulator. An extinction ratio of /spl sim/50 dB is achieved while optical pulses of 4-6 ps width at 30-40 GHz are generated.     

Design of 25 Gbit/s half-rate CDR with 1:2 demultiplexer for 100 GbE optical interconnects

A 25 Gbit/s clock and data recovery(CDR) circuit with 1:2 demultiplexer for 100 Gbit/s Ethernet(100 Gb E) optical interconnects has been designed and fabricated in Taiwan Semiconductor Manufacture Company(TSMC) 65 nm complementary metal-oxide-semiconductor(CMOS) technology. A novel quadrature voltage-controlled-oscillator(QVCO) structure adopts two pairs of transconductance cell and inverters to acquire rail-to-rail output swing. A half-rate bang-bang phase detector adopts four flip-flops array to sample the 25 Gbit/s input data and align the data phase, so the 25 Gbit/s data are retimed and demultiplexed into two paths 12.5 Gbit/s output data. Experimental results show that the recovered clock exhibits a peak-to-peak jitter of 7.39 ps and the recovered data presents a peak-to-peak jitter of 7.56 ps, in response to 312-1 pseudorandom bit sequence(PRBS) input. For 1.2 V voltage supply, the CDR circuit consumes 92 m W(excluding output buffers).     

Photoreceiver module using an InP HEMT transimpedance amplifier for over 40 gb/s

We developed a photoreceiver module for over 40 Gb/s that uses two ultrahigh- speed device technologies: an InP HEMT transimpedance amplifier (TIA) and a uni-traveling-carrier photodiode (UTC-PD). The TIA was designed to have a wide dynamic range by using cascade HEMT topology for the output buffer. We found that reducing the standing wave at the PD-TIA interface by decreasing the change of arg(S/sub 11/) of the TIA within the required frequency region is important for increasing the bandwidth of the module. We obtained a minimum sensitivity of -7.6 dBm and a dynamic range of 11 dB for 43-Gb/s nonreturn-to-zero optical input signal. Error-free operation of the module was confirmed at a data rate of 50 Gb/s.     

基于10Gb/s光互连的新型前均衡跨阻放大器

本文提出一种新型全均衡技术,以应用于改进调节式共源共栅跨阻放大器设计。此全均衡技术主要基于宽带串联电感π型网络技术和跨导倍增技术。这种（前均衡）技术的思想是在信号进入电路之前就对其进行补偿,并且不需要额外的功耗。此外,一种新型的密勒电容补偿技术用于后续的增益提高级,来更进一步的提高带宽。本设计的跨阻放大器基于台湾联合电子公司（UMC）的0.18 μm CMOS 工艺,并通过一个片上0.3pF的金属-半导体-金属（MIM）型电容来仿真实际的光电探测器电容。测试结果显示,此跨阻放大器带宽为8.2GHz,增益为57 dBΩ,由1.8V单端电压供电,总功耗仅为22mW.     

Comparison between NRZ and duobinary Modulation at 43 gb/s for MLSI-based and DCF-based transmission systems

In this paper, the performance of midlink spectral inversion (MLSI) is compared with the performance of "conventional" dispersion compensation fiber (DCF)-based transmission for two data formats: 43-Gb/s ON-OFF keying nonreturn-to-zero (OOK-NRZ) and 43-Gb/s duobinary. In the MLSI-based system, a polarization-diverse subsystem was used for spectral inversion employing magnesium-oxide-doped periodically poled lithium niobate (PPLN) waveguide technology. The transmission link consists of 8 /spl times/ 100 km standard single-mode fiber (SSMF) using erbium-doped fiber amplifiers (EDFAs) for amplification. Compared to the DCF-based system, it is seen that the MLSI-based configuration enhances the dispersion tolerance for both the NRZ and the duobinary modulation formats. It is concluded that the combination of the MLSI and the duobinary modulation format yields a highly dispersion-tolerant stable 43-Gb/s transmission system.     

A 5.28-Gb/s serializer ASIC for uncompressed long-haul multimedia interconnects

We report a 5.28-Gb/s serializer ASIC for uncompressed long-haul video interconnects. Our ASIC is based on the serializer architecture which maintains the constant output data rate for various resolutions of incoming video signals from VGA to UXGA. With this, a wide-band phase-locked-loop in a serializer and a continuous-rate clock-and-data-recovery circuit in a de-serializer are not necessary. The serializer ASIC contains clock-and-data-recovery circuits, de-multiplexers, a digital processing block, a phase-locked-loop, multiplexers. A VCSEL driver circuit is also integrated so that it can be used for long-haul transmission with multimode fiber. The ASIC produces 5.28-Gb/s serialized driving currents for VCSEL from parallel input signals. It occupies 3.45 mm² and consumes 151.7 mW.     

High speed 1.3 mm VCSELs for 12.5 Gbit/s optical interconnects

High speed 1.3 m vertical-cavity surface-emitting lasers for optical interconnects are presented. Error-free transmission over 3 km of standard singlemode fibre at data rates as high as 12.5 Gbit/s is demonstrated for the first time.     

Uncooled DBR laser directly Modulated at 3.125 gb/s as athermal transmitter for low-cost WDM systems

An uncooled three-section tunable distributed Bragg reflector laser is demonstrated as an athermal transmitter for low-cost uncooled wavelength-division-multiplexing (WDM) systems with tight channel spacing. A /spl plusmn/0.02-nm thermal wavelength drift is achieved under continuous-wave operation up to 70/spl deg/C. Dynamic sidemode suppression ratio of greater than 35 dB is consistently obtained under 3.125-Gb/s direct modulation over a 20/spl deg/C-70/spl deg/C temperature range, with wavelength variation of as low as /spl plusmn/0.2 nm. This indicates that more than an order of magnitude reduction in coarse WDM channel spacing is possible using this source.     

Field transmission of 8 /spl times/ 170 gb/s over high-loss SSMF link using third-order distributed Raman amplification

This paper reports on the field transmission of N/spl times/170-Gb/s over high-loss fiber links using third-order distributed Raman amplification (DRA) in a commercially operated network of Deutsche Telekom. It gives an overview of the key technologies applied for the realization of an 8 /spl times/ 170 Gb/s (1.28 Tb/s) dense wavelength division multiplexing (DWDM) system demonstrator and summarizes long-haul transmission experiments with terabit-per-second capacity over European fiber infrastructure. Third-order DRA enabled repeaterless transmission of 1 /spl times/ 170 Gb/s and 8 /spl times/ 170 Gb/s over links of 185- and 140-km field fiber, respectively. Including an additional 25 km of lumped standard single-mode fiber (SSMF) at the end of the span, a total loss of 61 and 44 dB, respectively, was bridged.     

Performance and scalability of a single-stage SOA switch for 10/spl times/10 gb/s wavelength striped packet routing

This letter reports successful routing of 10/spl times/10 Gb/s multiwavelength optical packets using single-stage semiconductor optical amplifier switches. Performance under switching is assessed with up to ten wavelengths with particular emphasis being placed on the limit of operation. A 15.2-dB power margin is demonstrated which allows at least eight port connections with a commercially available 0-dBm output 10-Gb/s transmitter and -21-dBm sensitivity receiver.     

Integrated 100-Gb/s ETDM Receiver

Ethernet in backbone networks has the potential to provide high-performance and cost-efficient networking solutions. Driven by the rapid growth of Ethernet traffic, it is likely that, in the transport network, the next step in terms of the data rate will be 100 Gb/s. In this paper, we report on an integrated electrical-time-division-multiplexing (ETDM) receiver for 100/107 Gb/s, which comprises 1 : 2 demultiplexing and clock-and-data recovery on a single chip. The ETDM receiver was tested successfully in 100- and 107-Gb/s transmission experiments over 480-km dispersion-managed fiber     

High-speed buffer management for 40 gb/s-based photonic packet switches

We develop a method of high-speed buffer management for output-buffered photonic packet switches. The use of optical fiber delay lines is a promising solution to constructing optical buffers. The buffer manager determines packet delays in the fiber delay line buffer before the packets arrive at the buffer. We propose a buffer management method based on a parallel and pipeline processing architecture consisting of (log/sub 2/N+1) pipeline stages, where N is the number of ports of the packet switch. This is an expansion of a simple sequential scheduling used to determine the delays of arriving packets. Since the time complexity of each processor in the pipeline stages is O(1), the throughput of this buffer management is N times larger than that of the sequential scheduling method. This method can be used for buffer management of asynchronously arriving variable-length packets. We show the feasibility of a buffer manager supporting 128 /spl times/ 40 Gb/s photonic packet switches, which provide at least eight times as much throughput as the latest electronic IP routers. The proposed method for asynchronous packets overestimates the buffer occupancy to enable parallel processing. We show through simulation experiments that the degradation in the performance of the method resulting from this overestimation is quite acceptable.     

100Gbit/s速率标准最新进展

本文介绍分析了100Gbit/s速率标准的最新进展。     

Theory and measurements of flip-chip interconnects for frequenciesup to 100 GHz

A detailed investigation of flip-chip interconnects up to W-band frequencies is presented in this paper. In a coplanar 50-Ω environment, different test structures were fabricated and measured to determine the electromagnetic characteristics of flip-chip multichip modules, such as detuning, reflection at the interconnect, and parasitic coupling. Electromagnetic simulation is used to explain the details behind the measured results. Key to high return loss at the interconnect is a small bump-pad area. Applying simple compensation structures, the frequency range of operation can be further extended. It is shown that a return loss beyond 20 dB in the frequency range up to 80 GHz is achievable along with excellent reproducibility. Measurements on detuning and isolation are also presented     

100 Gb/s optical time-division multiplexed networks

We present ultrafast slotted optical time-division multiplexed networks as a viable means of implementing a highly capable next-generation all-optical packet-switched network. Such a network is capable of providing simple network management, the ability to support variable quality-of-service, self-routing of packets, scalability in the number of users, and the use of digital regeneration, buffering, and encryption. We review all-optical switch and Boolean logic gate implementations using an ultrafast nonlinear interferometers (UNIs) that are capable of stable, pattern-independent operation at speeds in excess of 100 Gb/s. We expand the capability provided by the UNI beyond switching and logic demonstrations to include system-level functions such as packet synchronization, address comparison, and rate conversion. We use these advanced all-optical signal processing capabilities to demonstrate a slotted OTDM multiaccess network testbed operating at 112.5 Gb/s line rates with inherent scalability in the number of users and system line rates. We also report on long-haul propagation of short optical pulses in fiber and all-optical 3R regeneration as a viable cost-effective means of extending the long-haul distance of our OTDM network to distances much greater than 100 km.     

一种14位100 MS/s的流水线模数转换器

设计了一种14位100 MS/s的流水线模数转换器(ADC)。采样保持电路与第1级2.5位乘法数模转换器(MDAC1)共享运放,降低了功耗。提出了一种改进的跨导可变双输入开关运放,以满足采样保持和MDAC1对运放的不同要求,并消除记忆效应和级间串扰。ADC后级采用5级1.5位运放共享结构。基于0.18 μm CMOS工艺,ADC核心面积为1.4 mm²。后仿真结果表明,在1.8 V电源电压下,当采样速率为100 MS/s、输入信号频率为46 MHz时,ADC的信噪比(SNR)为82.6 dB,信噪失真比(SNDR)为78.7 dB,无杂散动态范围(SFDR)为84.1 dB,总谐波失真(THD)为-81.0 dB,有效位数(ENOB)达12.78位。ADC整体功耗为116 mW。