Low-temperature conductance measurements of surface states in HfO2–Si structures with different gate materials

Metal-oxide-semiconductor capacitors based on HfO₂ gate stack with different metal and metal compound gates (Al, TiN, NiSi and NiAlN) are compared to study the effect of the gate electrode material on the trap density at the insulator–semiconductor interface.C–V and G–ω measurements were made in the frequency range from 1 kHz to 1 MHz in the temperature range 180–300 K. From the maximum of the plot G/ω vs. ln(ω) the density of interface states was calculated, and from its position on the frequency axis the trap cross-section was found. Reducing temperature makes it possible to decrease leakage current through the dielectric and to investigate the states located closer to the band edge.The structures under study were shown to contain significant interface trap densities located near the valence band edge (around 2×10¹¹ cm⁻²eV⁻¹ for Al and up to (3.5–5.5)×10¹² cm⁻² eV⁻¹ for other gate materials). The peak in the surface state distribution is situated at 0.18 eV above the valence band edge for Al electrode. The capture cross-section is 5.8×10⁻¹⁷ cm² at 200 K for Al–HfO₂–Si structure.     

Study of electrically active defects in n-GaN layer

Deep level defects in both p⁺/n junctions and n-type Schottky GaN diodes are studied using the Fourier transform deep level transient spectroscopy. An electron trap level was detected in the range of energies at E_c−E_t=0.23–0.27 eV with a capture cross-section of the order of 10⁻¹⁹–10⁻¹⁶ cm² for both the p⁺/n and n-type Schottky GaN diodes. For one set of p⁺/n diodes with a structure of Au/Pt/p⁺–GaN/n–GaN/n⁺–GaN/Ti/Al/Pd/Au and the n-type Schottky diodes, two other common electron traps are found at energy positions, E_c−E_t=0.53–0.56 eV and 0.79–0.82 eV. In addition, an electron trap level with energy position at E_c−E_t=1.07 eV and a capture cross-section of σ_n=1.6×10⁻¹³ cm² are detected for the n-type Schottky diodes. This trap level has not been previously reported in the literature. For the other set of p⁺/n diodes with a structure of Au/Ni/p⁺–GaN/n–GaN/n⁺–GaN/Ti/Al/Pd/Au, a prominent minority carrier (hole) trap level was also identified with an energy position at E_t−E_v=0.85 eV and a capture cross-section of σ_n=8.1×10⁻¹⁴ cm². The 0.56 eV electron trap level observed in n-type Schottky diode and the 0.23 eV electron trap level detected in the p⁺/n diode with Ni/Au contact are attributed to the extended defects based on the observation of logarithmic capture kinetics.     

Charge trapping characterization of MOCVD HfO2/p-Si interfaces at cryogenic temperatures

The paper focuses on the study of charge trapping processes in high-k MOS structures at cryogenic temperatures. It was shown, that there is extremely strong trapping in shallow electron and hole traps, localized in the high-k dielectrics. Concentration of shallow electron traps is as much as 10¹³ cm⁻², while abnormal small capture cross-sections (4.5–8 × 10⁻²⁴ cm² for different samples, accordingly) suggests localization of shallow emitting electron traps in transition layer “high-k dielectric/Si”, more, than at the interface. Shallow hole traps with concentration near 10¹² cm⁻² are separated from silicon valence band with energy barrier in the range 10–39 meV for different samples.     

Correlation between infrared transmission spectra and the interface trap density of SiO2 films

This work is an attempt to estimate the electrical properties of SiO₂ thin films by recording and analyzing their infrared transmission spectra. In order to study a big variety of films having different infrared and electrical properties, we studied SiO₂ films prepared by low pressure chemical vapor deposition (LPCVD) from SiH₄ + O₂ mixtures at 425 °C and annealed at 750 °C and 950 °C for 30 min. In addition thermally grown gate quality SiO₂ films of similar thickness were studied in order to compare their infrared and electrical properties with the LPCVD oxides. It was found that all studied SiO₂ films have two groups of Si–O–Si bridges. The first group corresponds to bridges located in the bulk of the film and far away from the interfaces, the grain boundaries and defects and the second group corresponds to all other bridges located near the interfaces, the grain boundaries and defects. The relative population of the bulk over the boundary bridges was found equal to 0.60 for the LPCVD film after deposition and increased to 4.0 for the LPCVD films after annealing at 950 °C. Thermally grown SiO₂ films at 950 °C were found to have a relative population of Si–O–Si bridges equal to 3.9. The interface trap density of the LPCVD film after deposition was found equal to 5.47 × 10¹² eV⁻¹ cm⁻² and decreases to 6.50 × 10¹⁰ eV⁻¹ cm⁻² after annealing at 950 °C for 30 min. The interface trap density of the thermally grown film was found equal to 1.27 × 10¹¹ eV⁻¹ cm⁻² showing that films with similar Si–O–Si bridge populations calculated from the FTIR analysis have similar interface trap densities.     

High temperature characterization of high-κ dielectrics on SiC

We have fabricated thin catalytic metal–insulator–silicon carbide based structure with palladium (Pd) gates using TiO₂ as the dielectric. The temperature stability of the capacitor is of critical importance for use in the fabrication of electronics for deployment in extreme environments. We have evaluated the response to temperatures in excess of 450 °C in air and observed that the characteristics are stable. Results of high temperature characterization are presented here with extraction of interface state density up to 650 °C. The results show that at temperatures below 400 °C the capacitors are stable, with a density of interface traps of approximately 6×10¹¹ cm² eV⁻¹. Above this temperature the C–V and G–V characteristics show the influence of a second set of traps, with a density around 1×10¹³ cm² eV⁻¹, which is close to that observed for slow states near the conduction band edge. The study of breakdown field as a function of temperature shows two distinct regions, below 300 °C where the breakdown voltage has a strong temperature dependence and above 300, where it is weaker. We hypothesize that the oxide layer dominates the breakdown voltage at low temperature and the TiO₂ layer above 300 °C. These results at high temperatures confirms the suitability of the Pd/TiO₂/SiO₂/SiC capacitor structure for stable operation in high temperature environments.     

Electrical properties of oxidized polycrystalline silicon as a gate insulator for n-type 4H-SiC MOS devices

MOS capacitors were produced on n-type 4H-SiC using oxidized polycrystalline silicon (polyoxide). The polyoxide samples grown by dry oxidation without an anneal had a high interface state density (D_it) of 1.8 × 10¹² cm⁻² eV⁻¹ and the polyoxide samples grown by wet oxidation had a lower D_it of 1.2 × 10¹² cm⁻² eV⁻¹ (both at 0.5 eV below the conduction band). After 1 h Ar annealing, the D_it of wet polyoxide was reduced significantly to 2.6 × 10¹¹ cm⁻² eV⁻¹ (at 0.5 eV below the conduction band). Dry polyoxide exhibits higher breakdown electric fields than wet polyoxide. The interface quality and breakdown characteristics of polyoxide are comparable to published results of low-temperature CVD deposited oxides.     

An investigation of surface state capture cross-sections for metal–oxide–semiconductor field-effect transistors using HfO2 gate dielectrics

MOSFETs and MOSCs incorporating HfO₂ gate dielectrics were fabricated. The I_DS–V_DS, I_DS–V_GS, gated-diode and C–V characteristics were investigated. The subthreshold swing and the interface trap density were obtained. The surface recombination velocity and the minority carrier lifetime in the field-induced depletion region measured from the gated diodes were about 2.73 × 10³ cm/s and 1.63 × 10⁻⁶ s, respectively. The effective capture cross section of surface state was determined to be 1.6 × 10⁻¹⁵ cm² using the gated-diode technique in comparison with the subthreshold swing measurement. A comparison with conventional MOSFETs using SiO₂ gate oxide was also made.     

ICP-induced defects in GaN characterized by capacitance analysis

The defects induced by inductively coupled plasma reactive ion etching (ICP-RIE) on a Si-doped gallium nitride (GaN:Si) surface have been analyzed. According to the capacitance analysis, the interfacial states density after the ICP-etching process may be higher than 5.4 × 10¹² eV⁻¹ cm⁻², compared to around 1.5 × 10¹¹ eV⁻¹ cm⁻² of non-ICP-treated samples. After the ICP-etching process, three kinds of interfacial states density are observed and characterized at different annealing parameters. After the annealing process, the ICP-induced defects could be reduced more than one order of magnitude in both N₂ and H₂ ambient. The H₂ ambient shows a better behavior in removing ICP-induced defects at a temperature around 500 °C, and the interfacial states density around 2.2 × 10¹¹ eV⁻¹ cm⁻²can be achieved. At a temperature higher than 600 °C, the N₂ ambient provides a much more stable interfacial states behavior than the H₂ ambient.     

Effects of oxygen partial pressure on structural and electrical characteristics of HfAlO high-k gate dielectric grown on strained SiGe by pulsed-laser deposition

Dependence of oxygen partial pressures on structural and electrical characteristics of HfAlO (Hf:Al=1:1) high-k gate dielectric ultra-thin films grown on the compressively strained Si₈₃Ge₁₇ by pulsed-laser deposition were investigated. The microstructure and the interfacial structure of the HfAlO thin films grown under different oxygen partial pressures were studied by transmission electron microscopy, and the their electrical properties were characterized by capacitance–voltage (C−V) and conductance–voltage measurements. Dependence of interfacial layer thickness and C–V characteristics of the HfAlO films on the growth of oxygen pressure was revealed. With an optimized oxygen partial pressure, an HfAlO film with an effective dielectric constant of 16 and a low interface state density of 2.1×10¹⁰ cm⁻² eV⁻¹ was obtained.     

Optimization of electric properties of high-k zirconium dioxide by varying deposition and annealing conditions

ZrO₂ thin films with a smooth surface were synthesized on silicon by atomic vapor deposition™ using Zr[OC(CH₃)₃]₄ as precursor. The maximum growth rate (7 nm min⁻¹) and strongest crystalline phase were obtained at 400 °C. The increase of the deposition temperature reduced the deposition rate to 0.5 nm min⁻¹ and changed the crystalline ZrO₂ phase from cubic/tetragonal to monoclinic. These films showed no enhancement of the dominating monoclinic phase by annealing. The values of the dielectric constant (up to 32) and leakage current density (down to 1.2×10⁻⁶ A cm⁻² at 1×10⁶ V cm⁻¹) varied depending on the deposition temperature and film thickness. The midgap density of interface states was N_it=5×10¹¹ eV⁻¹ cm⁻². The leakage current and the density of interface states were lowered by the annealing to 10⁻⁷ A cm⁻² at 1×10⁶ V cm⁻¹ and to 10¹⁰ eV⁻¹ cm⁻², respectively. However, this also led to a decrease of the dielectric constant.     

Electrically active defects induced by hydrogen and helium implantations in Ge

Results of a study of electrically active defects induced in Sb-doped Ge crystals by implantations of hydrogen and helium ions (protons and alpha particles) with energies in the range from 500 keV to 1 MeV and doses in the range 1×10¹⁰–1×10¹⁴ cm⁻² are presented in this work. Transformations of the defects upon post-implantation isochronal anneals in the temperature range 50–350 °C have also been studied. The results have been obtained by means of capacitance–voltage (C–V) measurements and deep-level transient spectroscopy (DLTS).It was found from an analysis of DLTS spectra that low doses (<5×10¹⁰ cm⁻²) of H and He ion implantations resulted in the introduction of damage similar to that observed after MeV electron irradiation. The Sb–vacancy complex was the dominant deep-level defect in the lightly implanted samples. After implantations with doses higher than 5×10¹⁰ cm⁻² peaks due to more complex defects were observed in the DLTS spectra. Implantations with heavy (5×10¹³ cm⁻²) doses of both H and He ions caused the formation of a sub-surface layer with a high (up to 1×10¹⁷ cm⁻³) concentration of donors. These donors were eliminated by anneals at temperatures in the range 100–200 °C. Heat treatments of the heavy proton-implanted Ge samples in the temperature range 250–300 °C resulted in the formation of shallow hydrogen-related donors, the concentration of which was the highest in a region close to the projected depth of implanted protons. The maximum peak concentration of the H-related donors was higher than 1×10¹⁵ cm⁻³ for a proton implantation dose of 1×10¹⁴ cm⁻².     

Influence of rapid thermal annealing on morphological and electrical properties of RF sputtered AlN films

Aluminum nitride films were deposited, at 200 °C, on silicon substrates by RF sputtering. Effects of rapid thermal annealing on these films, at temperatures ranging from 400 to 1000 °C, have been studied. Fourier transform infrared spectroscopy (FTIR) revealed that the characteristic absorption band of Al–N, around 684 cm⁻¹, became prominent with increased annealing temperature. X-ray diffraction (XRD) patterns exhibited a better, c-axis, (0 0 2) oriented AlN films at 800 °C. Significant rise in surface roughness, from 2.1 to 3.68 nm, was observed as annealing temperatures increased. Apart from these observations, micro-cracks were observed at 1000 °C. Insulator charge density increased from 2×10¹¹ to 7.7×10¹¹ cm⁻² at higher temperatures, whereas, the interface charge density was found minimum, 3.2×10¹¹ eV⁻¹cm⁻², at 600 °C.     

Effects of Ti content and wet-N2 anneal on Ge MOS capacitors with HfTiO gate dielectric

Thin HfTiO gate dielectric is deposited by reactive co-sputtering method followed by wet or dry N₂ anneal. The effects of Ti content on the performance of HfTiO gate dielectric are investigated by using different sputtering powers for the Ti target. Experimental results indicate that as the Ti content increases, the dielectric constant (κ) can increase up to 40 for a Ti content of 28%. However, when the Ti content is too high, the interface properties and gate leakage properties are deteriorated. On the contrary, results show that owing to the hydrolyzable property of GeO_x, the wet-N₂ anneal can greatly suppress the growth of unstable low-κ GeO_x interlayer, resulting in lower interface-state density and gate leakage current, in addition to larger κ value. In this study, when the sputtering power of the Ti target is 80 W together with a 25-W power for the Hf target and a post-deposition anneal (PDA) in wet-N₂ ambient at 500 °C for 300 s, excellent device performance is achieved: equivalent oxide thickness of 0.72 nm, equivalent dielectric constant of 39, interface-state density of 6.5 × 10¹¹ eV⁻¹ cm⁻² and gate leakage current of 5.7 × 10⁻⁴ A/cm² at V_g = 1 V. Therefore, in order to obtain high-quality HfTiO gate dielectric for small-scaled Ge MOS devices, not only should the Ti content be optimized, the PDA should also be done in a wet-N₂ ambient.     

Investigation of Au/Ti/Al ohmic contact to N-type 4H–SiC

In this study, investigation on Au/Ti/Al ohmic contact to n-type 4H–SiC and its thermal stability are reported. Specific contact resistances (SCRs) in the range of 10⁻⁴–10⁻⁶ Ω cm², and the best SCR as low as 2.8 × 10⁻⁶ Ω cm² has been generally achieved after rapid thermal annealing in Ar for 5 min at 800 °C and above. About 1–2 order(s) of magnitude improvement in SCR as compared to those Al/Ti series ohmic systems in n-SiC reported in literature is obtained. XRD analysis shows that the low resistance contact would be attributed to the formation of titanium silicides (TiSi₂ and TiSi) and Ti₃SiC₂ at the metal/n-SiC interface after thermal annealing. The Au/Ti/Al ohmic contact is thermally stable during thermal aging treatment in Ar at temperature in the 100–500 °C range for 20 h.     

Advantages and limitations of MgO as a dielectric for GaN

MgO and Sc₂O₃ were deposited by gas source molecular beam epitaxy on GaN. MgO was found to produce lower interface state densities than Sc₂O₃, 2–3 × 10¹¹ vs. 9–11 × 10¹¹ eV⁻¹ cm⁻². The good electrical quality of the interface is believed to be due to the presence of a single crystal epitaxial layer at the GaN surface. By contrast, the MgO was found to be more sensitive to environmental and thermal degradation than the Sc₂O₃. The environmental degradation is believed to be due to interaction with water vapor in the air and was suppressed by capping of the MgO. Annealing at the temperatures needed for implant activation in GaN produced significant roughening of the MgO/GaN interface and an order of magnitude increase in the interface state density. This sensitivity to thermal degradation will require changes in the processing sequence presently envisioned for e-mode devices in order to avoid damaging the interface and increasing the gate leakage in the device.     

Examination and evaluation of La2O3 as gate dielectric for sub-100 nm CMOS and DRAM technology

High-k gate dielectric La₂O₃ thin films have been deposited on Si(1 0 0) substrates by molecular beam epitaxy (MBE). Al/La₂O₃/Si metal-oxide–semiconductor capacitor structures were fabricated and measured. A leakage current of 3 × 10⁻⁹ A/cm² and dielectric constant between 20 and 25 has been measured for samples having an equivalent oxide thickness (EOT) 2.2 nm. The estimated interface state density D_it is around 1 × 10¹¹ eV⁻¹ cm⁻². EOT and flat-band voltage were calculated using the NCSU CVC program. The chemical composition of the La₂O₃ films was measured using X-ray photoelectron spectrometry and Rutherford backscattering. Current density vs. voltage curves show that the La₂O₃ films have a leakage current several orders of magnitude lower than SiO₂ at the same EOT. Thin La₂O₃ layers survive anneals of up to 900 °C for 30 s with no degradation in electrical properties.     

Germanium FETs and capacitors with rare earth CeO2/HfO2 gates

Long channel Ge FETs and capacitors with CeO₂/HfO₂/TiN gates were fabricated by photolithography and gate wet etch. Rare earth CeO₂ in direct contact with Ge was used as a passivating layer producing lowest D_it values in the mid 10¹¹ eV⁻¹ cm⁻² range. HfO₂ cap reduces leakage and improves equivalent oxide thickness scaling of the whole gate stack. The p-FETs show exceptionally high I_ON/I_OFF ratio 10⁶, mainly due to low OFF current, and peak channel mobility around 80 cm²/V s. The n-FETs, although functional, show inferior performance producing ON currents an order of magnitude lower compared to p-FETs.     

DLTS characterisation of InGaAlP films grown using different V/III ratios

Deep levels in InGaAlP films grown using two different V/III ratios have been studied by employing deep level transient spectroscopy (DLTS). The two samples investigated have the same composition of (Al_0.3Ga_0.7)_0.51In_0.49P and a film thickness of 0.6 μm, but grown with V/III ratios 75 and 50. Two defect levels with activation energies 0.23 and 0.78 eV are detected by temperature-scan DLTS in the sample with a V/III ratio of 75, with the 0.78 eV level being the dominant peak. Their respective capture cross-sections are 1.2×10⁻¹⁶ and 3.8×10⁻¹³ cm⁻². The 0.78 eV trap level is also analysed using isothermal DLTS measurement and similar values of thermal signatures are obtained. The DLTS spectrum of the 0.78 eV trap level has been found to be broader than that expected for a point-type defect, implying that it may be associated with a complex or extended defect. The observation of logarithmic capture mechanism further supports this speculation. On the other hand, no peak corresponding to the 0.23 eV level appears in isothermal DLTS spectra, which is possibly due to the severe temperature dependence of capture rate and the system's limitation in the high-frequency regime. For the sample with a V/III ratio of 50, only one dominant electron trap level, with an activation energy of 0.42 eV and a capture cross-section of 1.4×10⁻¹⁷ cm⁻², is detected by isothermal DLTS method.     

Charge trapping in ultrathin Gd2O3 high-k dielectric

Charge trapping in ultrathin high-k Gd₂O₃ dielectric leading to appearance of hysteresis in C-V curves is studied by capacitance-voltage and current-voltage techniques. It was shown that the large leakage current at a negative gate voltage causes the generation of the positive charge in the dielectric layer, resulting in the respective shift of the C-V curve. The capture cross-section of the hole traps is around 2 × 10⁻²⁰ cm². The distribution of the interface states was measured by conductance technique showing the concentration up to 7.5 × 10¹² eV⁻¹ cm⁻² near the valence band edge.     

The positive charge neutralisation after bi-directional stress on MOS capacitors

The aim of this work is to study the positive charge relaxation after bidirectional electron injections in a p-metal-oxide-silicon capacitor submitted to a constant current. This relaxation is studied following two steps. When the stressed sample is submitted to a nonstressing constant current, the positive charge neutralisation follows an exponential law with time. This allows us to estimate the electron capture cross-section (≈10^–16 to ≈2 × 10^–15 cm²). When the sample is let without any applied field, the positive charge relaxation follows a logarithmic law with time. It is also shown that the capture cross-section depends on the stress and relaxation times.