Spread spectrum clock generator with hybrid controlled oscillator

A spread spectrum clock generator (SSCG) with a hybrid controlled oscillator (HCO) is presented. By using the proposed HCO, the modulation ratio of an SSCG can be made insensitive to process, voltage and temperature variations without a ΣΔ fractional-N phase-locked loop. The simulated modulation ratio sensitivities are as low as -1.3%/ 100°C and 7.0%/V for temperature and V_DD, respectively. The SSCG IC, designed in a 0.18 μm 1P4M CMOS process, operates from 40 to 90 MHz and consumes 5.5 mA from a 1.8 V supply voltage.     

基于皮尔斯振荡器的8MHz晶振电路设计

分析了石英晶体的等效模型和性能参数,设计了一款基于皮尔斯振荡器的8 MHz晶振电路,主要包括皮尔斯电路、使能控制及隔离电路、偏置电路和整形及电平移位电路.针对数字电路时钟为方波且数字电压域与模拟电压域不同的问题,设计了一个整形及电平移位电路,将晶体振荡器输出的正弦波整形成方波,且电路实现了双电压域工作.基于华宏0.11...     

用于以太网物理层时钟同步PLL的VCO设计

研究了一种基于以太网物理层时钟同步的高带宽低噪声压控振荡器（VCO）,该VCO采用交叉耦合的电流饥饿型环形振荡器,通过级联11级环路电路和改善其控制电压变换电路,优化了VCO的输出频率范围以及降低了输出时钟的相位噪声,完全满足以太网物理层芯片时钟电路的性能指标。基于TSMC3．3V0．25μmCMOS工艺的仿真结果表明,中心频率为250MHz时,压控增益为300MHz／V,其线性区覆盖范围是60～480MHz,在偏离中心频率600kHz处的相位噪声为-108dBc。     

Low-jitter phase-locked loop based on pseudo-differential delayelements

A phase-locked loop (PLL) that is highly robust to supply/substrate noise is described. A new type of voltage-controlled oscillator (VCO) based on pseudo-differential delay elements is presented. The proposed circuit is implemented using a 0.35 μm CMOS process technology with a 3.3 V supply. It generates 16 clock phases at 250 MHz, tailored to gigabit link applications     

Fully integrated 533 mhz programmable switched current pll in 0.012 mm2

A 533 MHz programmable phase-locked loop is designed for DDR applications using a switched current filter and implicit phase detection. The use of switched current technology allows a fully integrated loop filter which is much smaller than equivalent integrated passive filters, as a result the circuit occupies only 0.012 mm2 on a 0.12 μm 1.2 V digital CMOS process.     

A universal 0.03-mm2 one-pin crystal oscillator in CMOS

A one-pin crystal oscillator with an integrated load capacitance of 15 pF has been realized in a standard 0.35-μm CMOS technology. Due to the structure of the oscillator and the use of MOS gate capacitance for the load capacitors, the chip area can be very small. The total active area including load capacitors is less than 0.03 mm². The design can be operated with supply voltages in the range of 1.4-3.6 V and allows crystal frequencies in the range of 3-30 MHz. The current consumption of the oscillator core is 180 μA at 10 MHz with 3.3-V power supply. It produces a rail-to-rail output swing, regulated by an amplitude control loop, and has the same flexibility and ease of frequency tuning as a common Pierce oscillator. As no special IC process options are required, the design is very suitable for clock generation in digital very-large-scale-integration chips     

Digitally controlled oscillator

A monolithic integrated digitally controlled oscillator circuit is discussed. The oscillator has an output frequency range from 19.07 Hz to more than 20 MHz with a resolution of 19.07 Hz. It is fully linear over the complete control range with respect to the digital control word, has the long-term stability of a quartz oscillator, and the output clock edge uncertainty has a standard deviation of less than 0.5 ns. The circuit requires only a reference quartz as an external component. It operates from a single 5-V power supply, is fabricated in a 1.5-μm double-metal single-poly standard CMOS process, and requires an area of 4.1 mm²     

Ultra-low-power clock generation circuit for EPC standard UHF RDID transponders

A 0.6 V 720 nW relaxation oscillator fabricated in a standard 0.13 mum CMOS process is proposed as the clock generation circuit for EPC standard UHF RFID transponders. A less than 2% frequency variation is achieved at the frequency of 5.65 MHz when supply voltage varies from 0.6 to 1.0 V.     

基于门控多路环形振荡器的时间数据转换器

A gated ring oscillator(GRO) based time-to-digital converter(TDC) is presented.To enhance the resolution of the TDC,a multi-path structure for the GRO is used to achieve a higher oscillation frequency and an input stage is also presented to equivalently amplify the input time difference with a gain of 2.The GRO based TDC circuit is fabricated in TSMC 65 nm CMOS technology and the core area is about 0.02 mm~2.According to the measurement results,the effective resolution of this circuit is better than 4.22 ps under a 50 MHz clock frequency. With a 1 ns input range,the maximum clock frequency of this circuit is larger than 200 MHz.Under a 1 V power supply,with a 200-800 ps input time difference,the measured power consumption is 1.24 to 1.72 mW at 50 MHz clock frequency and 1.73 to 2.20 mW at 200 MHz clock frequency.     

A current-steering self-calibration 14-bit 100-MSPs DAC

This paper presents the design and implementation of a 14-bit,100 MS/s CMOS digital-to-analog converter(DAC).Analog background self-calibration based on the concept of analog current trimming is introduced.A constant clock load switch driver,a calibration period randomization circuit and a return-to-zero output stage have been adopted to improve the dynamic performance.The chip has been manufactured in a SMIC 0.13-μm process and occupies 1.33× 0.97 mm2 of the core area.The current consumption is 50 mA under 1.2/3.3 V dual power supplies for digital and analog,respectively.The measured differential and integral nonlinearity is 3.1 LSB and 4.3 LSB,respectively.The SFDR is 72.8 dB at a 1 MHz signal and a 100 MHz sampling frequency.     

A 6-GHz integrated phase-locked loop using AlGaAs/GaAsheterojunction bipolar transistors

A fully integrated 6-GHz phase-locked-loop (PLL) fabricated using AlGaAs/GaAs heterojunction bipolar transistors (HBTs) is described. The PLL is intended for use in multigigabit-per-second clock recovery circuits for fiber-optic communication systems. The PLL circuit consists of a frequency quadrupling ring voltage-controlled oscillator (VCO), a balanced phase detector, and a lag-lead loop filter. The closed-loop bandwidth is approximately 150 MHz. The tracking range was measured to be greater than 750 MHz at zero steady-state phase error. The nonaided acquisition range is approximately 300 MHz. This circuit is the first monolithic HBT PLL and is the fastest yet reported using a digital output VCO. The minimum emitter area was 3 μm×10 μm with f_t=22 GHz and f_max=30 GHz for a bias current of 2 mA. The speed of the PLL can be doubled by using 1-μm×10-μm emitters in next-generation circuits. The chip occupies a die area of 2-mm×3-mm and dissipates 800 mW with a supply voltage of -8 V     

CMOS ring VCO for UHF RFID readers

A complementary metal oxide semiconductor (CMOS) voltage controlled ring oscillator for ultra high frequency (UHF) radio frequency identification (RFID) readers has been realized and characterized. Fabricated in charter 0.35 μm CMOS process, the total chip size is 0.47×0.67 mm2. While excluding the pads, the core area is only 0.15×0.2 mm2. At a supply voltage of 3.3 V, the measured power consumption is 66 mW including the output buffer for 50 Ω testing load. This proposed voltage-controlled ring oscillator exhibits a low phase noise of - 116 dBc/Hz at 10 MHz offset from the center frequency of 922.5 MHz and a lower tuning gain through the use of coarse/fine frequency control.     

20-850 MHz low-distortion baseband amplifier in digital CMOS process

A CMOS baseband amplifier using an open-loop architecture is presented. The eight-stage amplifier, implemented in a standard 0.13 μm CMOS technology, shows a maximum gain of 30 dB in the broadband frequency range 20?850 MHz. Each amplification stage draws 0.8 mA from a single 1.2 V power supply. The total amplifier chain shows an output referred OIP3 of 11 dBm, which can be achieved by using active loads that compensate for the nonlinear transconductance of the input transistors.     

A compact ADPLL based on symmetrical binary frequency searching with the same circuit

A compact all-digital phase-locked loop (C-ADPLL) based on symmetrical binary frequency searching (BFS) with the same circuit is presented in this paper. The minimising relative frequency variation error Δη (MFE) rule is derived as guidance of design and is used to weigh the accuracy of the digitally controlled oscillator (DCO) clock frequency. The symmetrical BFS is used in the coarse-tuning process and the fine-tuning process of DCO clock frequency to achieve the minimum Δη of the locked DCO clock, which simplifies the circuit architecture and saves the die area. The C-ADPLL is implemented in a 0.13 μm one-poly-eight-metal (1P8M) CMOS process and the on-chip area is only 0.043 mm², which is much smaller. The measurement results show that the peak-to-peak (Pk-Pk) jitter and the root-mean-square jitter of the DCO clock frequency are 270 ps at 72.3 MHz and 42 ps at 79.4 MHz, respectively, while the power consumption of the proposed ADPLL is only 2.7 mW (at 115.8 MHz) with a 1.2 V power supply. The measured Δη is not more than 1.14%. Compared with other ADPLLs, the proposed C-ADPLL has simpler architecture, smaller size and lower Pk-Pk jitter.     

A 700-MHz 24-b pipelined accumulator in 1.2-μm CMOS forapplication as a numerically controlled oscillator

To accomplish timing recovery/synthesis in high-speed communication systems, a 24-b numerically controlled oscillator (NCO) IC using a circuit design technique called true single-phase clock (TSPC) pipelined CMOS has been fabricated in a standard 1.2-μm CMOS process. The device achieves a maximum tested input clock rate of 700 MHz, which results in an output frequency tuning range from DC up to 350 MHz with a 41.7-Hz tuning resolution and a peak-to-peak phase jitter of 1.4 ns. The 1.7-mm×1.7-mm IC dissipates 850 mW with a single 5-V supply, which is substantially lower than similar ECL and GaAs devices     

一种用于开关电源中的双极型高频振荡器

文章提出了一种基于2μm双极型工艺设计、应用于DC/DC开关电源中的高频振荡电路.该模块产生时钟信号,该时钟信号的频率可以随着负载和电源电压的变化而变化.我们用Cadence Spectre仿真工具对电路的工作状态进行仿真,结果表明该电路在宽电源输入和高、低温范围内都具有良好的性能.本振荡电路不但功能良好,而且结构简单...     

A wide supply voltage range and low-power all-digital clock generator

This study presents a low-power all-digital clock generator (ADCG) for a wide supply voltage range system. The proposed ADCG limits the maximum supply current to 100 μA at a supply voltage ranging from 1.6 to 3.6 V. The ADCG also uses a digitally controlled oscillator (DCO) to extend its operational frequency range. The proposed DCO controls the supply current and divider circuits for a wide supply voltage range. The output duty cycle of ADCG falls within 50 ± 1.9 % using a duty cycle corrector. The maximum peak-to-peak jitter is less than 2.7 % at 8.38 MHz for a digital water meter application (DWM). The operational frequencies of 1.45 and 8.38 MHz at 1.8 V are 3.1 and 36.7 μA, respectively. The core area of ADCG is 0.14 mm² for a 0.35 μm CMOS process. The operational frequency of ADCG ranges from 4.5 to 9.2 MHz at a supply voltage ranging from 1.6 to 3.6 V. This clock generator can also be applied to microcontroller applications.     

一种伪差分两级环形振荡器的设计

设计了一种伪差分两级环形振荡器,可为锁相环提供8 GHz四相位正交时钟。通过分析耦合两级环形振荡线性模型,对四级环形振荡结构进行优化,提出了伪差分两级环形振荡结构。基于单级缓冲器的开环分析,可对振荡器的输出频率进行精准估算,并判断振荡情况。采用65 nm CMOS工艺进行设计与仿真。结果表明,在1.2 V电压下,振荡器的功耗为6.9 mW,1 MHz频率处的相位噪声为－82.104 5 dB,满足高速SerDes接口的设计要求。     

一款用于DCDC芯片的多模式、高精度振荡器设计

设计了一款多模式的高精度振荡器,应用于开关电源芯片中,为芯片内部逻辑提供稳定的时钟源,并且具有3种工作模式,提高了整体电路的灵活性。电路中设计了低压差线性稳压器(LDO)和零温漂的电流源,使振荡器的输出频率不易受电压和温度变化的影响。同时采用可修调的技术,对电容的充电电流进行双向调整,消除了工艺带来的误差。该电路基于CSMC 0.25μm 2P5M工艺进行设计,采用HSPICE进行仿真,结果表明,在3.0~6.0 V输入电压范围内,输出频率变化1.1 kHz,变化率为0.22%;在-55~125℃温度范围内,输出频率变化2.1 kHz,变化率为0.41%。     

An all-digital PLL for frequency multiplication by 4 to 1022 with seven-cycle lock time

An all-digital phase-locked loop (PLL) circuit in which resolution in the phase detector and digitally controlled oscillator (DCO) exactly matches the gate-delay time is presented. The pulse delay circuit is connected in a ring shape with 32 inverters (2/sup 5/ inverters). With the inverter gate-delay time as the time base, the pulse phase difference is detected simultaneously with the generation of the output clock. In this system, the phase detector and oscillator share a single ring-delay-line (RDL). This means the resolution is the same at all times, making a high-speed response possible. In a prototype integrated circuit (IC) using 0.65-/spl mu/m CMOS, the generation of a frequency multiplication clock was achieved with four reference clocks, and that of a phase-locked clock with seven reference clocks, for a high-speed response. The cell size was 1.08 /spl times/ 1.08 mm/sup 2/, and the output clock frequency had a wide range of 50 kHz/spl sim/60 MHz. The multiplication range of the clock frequency was also a very wide 4/spl sim/1022, and a high level of precision was achieved with a clock jitter standard deviation of 234 ps. This digital PLL can withstand a broad range of operating environments, from -30/spl deg/C/spl sim/140/spl deg/C, and is suitable for making a programmable clock generator on a chip.