2 Gbit/s, 16*16 expandable high-speed space-division-switch LSI using SST

A Si bipolar 2 Gbit/s 16*16 high-speed space-division-switch LSI is described. High-speed operation of 2 Gbit/s and low-power dissipation of 2.8 W are achieved by adopting a new expandable structure, a very low voltage swing-differential bipolar circuit design and a super self-aligned process technology (SST-1A). This LSI is applicable to future B-ISDN HDTV switching systems.<>     

High-speed, low-power, bipolar standard cell design methodology forGbit/s signal processing

A low-power Si bipolar standard cell LSI design methodology for gigabit/second signal processing is described. To obtain high-speed operation, it features a pair of differential clock channels inside cells, differential clock distribution with the placement of differential wires of equal length and load, a performance-driven layout, and a highly accurate static timing analysis. A computer-aided-design-based optimization technology for power dissipation makes cell currents minimum while maintaining the circuit speed. A 5.6-K gate synchronous digital hierarchy signal-processing LSI operating at 1.6 Gbit/s with only 3.9 W power consumption demonstrates the effectiveness of this design method     

Integrated bipolar master/slave D-flip-flop with multiplexing capability for Gbit/s operation

A versatile integrated bipolar circuit developed for a broadband communication system is described. It consists of a master/slave D-flip-flop with a 2:1 time-division multiplexer at the input and a powerful buffer stage at the output. Despite realisation in a relatively simple bipolar technology, bit rates up to 1.5 Gbit/s (NRZ) were measured.     

An expandable time-division circuit switching LSI and networkarchitecture for broadband ISDN

A broadband network architecture is proposed that integrates multimedia services, such as data, video, and telephony information, using 52-Mb/s based STM-paths at the user network interface (UNI). The user can access any new service via the STM-based access network via either synchronous transfer mode (STM) switching or asynchronous transfer mode (ATM) switching. STM circuit switching supports long duration, constant bandwidth data transfer services such as video and high-definition television (HDTV) distribution and will also be used for the crossconnect system. Circuit switching can provide transparent transmission during long connection periods. This paper also proposes an expandable time-division switch architecture, an expandable time-division switching LSI, and an expandable switching module for small to large size system applications. The proposed time-division switching LSI, module, and system handle 52-Mb/s bearer signals and have throughputs of 2.4 Gb/s, 10 Gb/s, and 40 Gb/s, respectively. The time-division switch realizes video distribution with 1:n connections. Finally, a local switching node that features an expandable 52-Mb/s time-division circuit switching network is shown for multimedia access networking     

A time division multiplexer IC for bit rates up to about 2 Gbits/s

A bipolar 4:1 time-division multiplexer IC developed for a planned 1.12 Gbit/s optical communication system is presented. Without resorting to sophisticated technology, the high speed was achieved by modification of well-known circuit concepts and by careful circuit optimization. With a current-switch output, reliable operation was measured to over 2 Gbit/s compared to over 1.5 Gbit/s if emitter-follower outputs are used. The experimental results agree very well with the simulation predictions.     

High-Speed Digital Switching Technology Using Space-Division-Switch LSI's

NTT is planning a high-speed broad-band switching network that offers high-speed digital and 4 MHz video services. This paper discusses the hardware design of the high-speed space-division digital switching network and requirements for a switch LSI. In addition, the design and measured performance of a 32 × 32 CMOS space-division-switch LSI are described. In this network, video signals are converted into 32 Mbit/s digital signals by band-compression technology. In order to switch such digital signals, space-division switches are more advantageous than time-division switches. This is because time-division switches cannot multiplex many channels at that bit rate. Furthermore, the use of the space-division-switch LSI is the most effective way to miniaturize the switching system.     

1 Gbit/s high-speed bit-synchronisation LSI for B-ISDN

The CCITT recommended that the bit rates for synchronous digital hierarchy (SDH) should be multiples of 155.52 Mbit/s. In handling high-speed data (such as 622.08 Mbit/s) in B-ISDN switching systems, there are problems associated with waveform degradation caused by impedance mismatching and amplitude attenuation. A countermeasure is the regeneration of the distorted waveforms using the system clock in each board. A bit-synchronisation circuit allows distorted waveforms to be regenerated and simplifies the design of timing between boards. The author have developed a high-speed bit-synchronisation LSI with excellent jitter tolerance in the 600 Mbit/s region and which has a simple circuit structure. The LSI features a circuit structure based on an elastic store, Si-bipolar super self-aligned process technology (SST),/sup 1/ and careful timing design. It can handle three different bit-rates (622.08, 155.52, and 51.84 Mbit/s) and has a maximum bit rate of 1 Gbit/s.<>     

80 Gbit/s ATM switch MCM based on multilayer ceramic technology

An 80 Gbit/s asynchronous transfer mode (ATM) switch multichip module (MCM) of dimensions 114×160×6.5 mm has been fabricated. This MCM can support high-density mounting and high-speed interconnection among large-scale-integrated (LSI) chips. Using LSI, ceramic-substrate, high-speed/high-power connector, and compact liquid-cooling technologies, an 80 Gbit/s ATM switching module has been built     

1 Gbit/s, 32*32 high-speed space-division switching module for broadband ISDN using SST LSIs

A high-speed 32*32 space-division switching module for high-definition TV broadcasting and switching systems is described. It employs a newly developed Si-bipolar SST 8*8 switch LSI, high-speed peripheral ICs and a high-speed impedance-controlled board. The module is capable of a 1.0 Gbit/s signal speed using 1:1 and 1:n connections.<>     

A 2 Gb/s expandable space-division switching LSI and networkarchitecture for gigabit-rate broad-band circuit switching

An expandable space-division (SD) switch architecture and a bipolar circuit design for gigabit-per-second crosspoint-switch LSIs are described. An expandable 2-Gb/s 16×16 crosspoint switch LSI which employs a novel switch structure, a novel circuit design, and a super self-aligned process (SST-1A) is developed. A switching module and partial 1:n nonblock, full 1:1 nonblock switching network architecture are also presented. Using the LSI and the switching network architecture, an experimental 620-Mb/s network system is demonstrated     

Scalable 10 Gbit/s 4×20.25 μm CMOS/SIMOX ATM switch LSIcircuit based on distributed contention control

A scalable 10 Gbit/s 4×2 ATM switch LSI circuit has been fabricated. It employs a new distributed contention control technique that makes the LSI circuit expandable. To increase the LSI circuit throughput, 0.2 μm CMOS/SIMOX (separation by implanted oxygen) technology is used. It allows the LSI circuit to offer 221 I/O pins, an operating speed of 1.25 Gbit/s and 7 W power consumption     

160 Gbit/s full optical time-division demultiplexing using FWM ofSOA-array integrated on PLC

160 Gbit/s full time-division demultiplexing using a semiconductor optical amplifier hybrid integrated demultiplexer on a planar lightwave circuit is demonstrated. Error-free, demultiplexing from a 160 Gbit/s signal to eight-channel, 20 Gbit/s signals is successfully demonstrated     

Newly structured 512 Mbit/s high-speed time-division switch

The letter describes the recently developed fastest time-division switch experimental system operating at 512 Mbit/s. The system adopts a new switch structure which can increase switching throughput by four times over the basic structure to ensure high-speed performance. Also employed in the switch are two types of peripheral logic developed using Si bipolar super-self-aligned process technology. This switch makes possible the ISDN time-division switches necessary for TV and high-definition TV communication.     

A 1.8 Gb/s GaAs optoelectronic universal switch LSI withmonolithically integrated photodetector and laser driver

A high-speed monolithic optical interface switch LSI is developed using a GaAs MSM photodetector and large-scale integrated electric circuits. This LSI operates universally as a 1.8 Gb/s optical-input/optical-output four-channel time-division switch, a 1.8 Gb/s optical-input/electrical-output 1:4 demultiplexer, a 2.0 Gb/s electrical-output 4:1 multiplexer, and a 2.8 Gb/s electrical-input/electrical-output 4×4 space-division switch. It uses a new multistage 2×2 switch block with small hardware and high-speed operation. It can be expanded to a 16×16 optical-input/optical-output time-division switch operating at up to 1.8 Gb/s for broadband-ISDN     

12.5 Gbit/s fibre-optic network using all-optical processing

A 12.5 Gbit/s fibre-optic network is implemented with a central mode-locked laser clock, integrated-optic waveguide modulators, optical time-multi/demultiplexing and an optical reservation protocol. The network accommodates 125 stations transmitting at 100 Mbit/s each, using receiver-fixed assignment time-division multiple access.     

Low power optical gate HBT driver array for 2.5 Gbit/s ATMswitching

A four element driver array for optical gates in a 2.5 Gbit/s optical ATM switch is presented. The circuit uses a GaAs-GaAlAs heterojunction bipolar transistor (HBT) technology. It enables a switching time of <300 ps and current up to 150 mA with <400 mW per gate power consumption     

All-optical time-division demultiplexing experiment withsimultaneous output of all constituent channels from 100 Gbit/s OTDMsignal

The successful demonstration of all-optical time-division demultiplexing is reported, wherein all 10 Gbit/s constituent channels are simultaneously demultiplexed with no error from a 10×10 Gbit/s OTDM signal. A multichannel demultiplexer based on cross phase modulation (XPM)-induced frequency shift in an optical fibre, called MOXIC, is used     

16 Gbit/s fibre transmission experiment using optical time-division multiplexing

An experimental four-channel optical time-division multiplexed transmission system is described, and the first demonstration of fibre transmission at a bit rate of 16Gbit/s is reported. In this experiment, data at 16Gbit/s have been transmitted over 8 km of fibre with a bit error rate below 10-9.     

25 Gbit/s decision circuit, 34 Gbit/s multiplexer, and 40 Gbit/s demultiplexer IC in selective epitaxial Si bipolar technology

A 25 Gbit/s decision circuit, a 34 Gbit/s multiplexer, and a 40 Gbit/s demultiplexer IC have been realised with selective epitaxial silicon bipolar technology using 0.8 mu m lithography. The data rates achieved are the highest values reported for these types of circuit in any IC technology.<>     

Asynchronous transfer mode switching LSI chips with 10-Gb/s serialI/O ports

LSI chips were developed that fit on a switching fabric using chip-to-chip optical interconnections; they have 10-Gb/s serial input and output ports, which facilitates the layout of optically interfaced switching element modules. A test switching module composed of these chips was operated at 10.2 Gb/s without bit errors. Ultrahigh-speed switching LSI chips have been developed for a future asynchronous transfer mode (ATM) switching system with an over-Tb/s capacity. Their serial input and output ports facilitate chip-to-chip optical interconnection. Cell-dropper and crosspoint-router LSI chips, composing the core of the switching element, were fabricated by using GaAs LSI technology. A test switching module composed of these chips was operated at 10.2 Gb/s without bit errors