A MOST invertor with improved switching speed

A modified MOST invertor circuit consisting of a driver, load, and bias MOST is proposed. The gate voltage of the load MOST is supplied by the bias MOST. This leads to an improvement of both the output pulse height and the switching speed if the circuit is applied in dynamic logic. The switching transients are studied by considering first the dynamic loadlines of the driver and the load MOST, and second an analytical function has been developed predicting the 10-90 percent turnoff time of the circuit. The theoretical turn-off times are found to be in agreement with measurements on a breadboard circuit and from this a maximum gain in 10-90 percent turn-off time of the modified invertor of about a factor of 3, as compared with a conventional MOST invertor, appears to be attainable. The modified invertor circuit may also be used in static logic with conservation of its full advantages, provided that the minimum switching period is about 50 ns.     

An improved hysteresis current controller for reducing switchingfrequency

In this paper, an improved invertor hysteresis current controller is proposed. It coordinates the switching of the three-phase switches in the d-q phase plane. In addition to the current error, information of the current error derivative is further employed so that one can take more advantage of adding the zero voltage vector for reducing the switching frequency. A simple hardware implementation of the improved hysteresis current controller is also proposed such that merits of the conventional hysteresis current controller can still be kept. Theoretical basis and some simulation and experimental results are presented to demonstrate the validity of the improved hysteresis current controller     

Design and Evaluation of Cascode GaN FET for Switching Power Conversion Systems

In this paper, we present the design and characterization analysis of a cascode GaN field‐effect transistor (FET) for switching power conversion systems. To enable normally‐off operation, a cascode GaN FET employs a low breakdown voltage (BV) enhancement‐mode Si metal‐oxide‐semiconductor FET and a high‐BV depletion‐mode (D‐mode) GaN FET. This paper demonstrates a normally‐on D‐mode GaN FET with high power density and high switching frequency, and presents a theoretical analysis of a hybrid cascode GaN FET design. A TO‐254 packaged FET provides a drain current of 6.04 A at a drain voltage of 2 V, a BV of 520 V at a drain leakage current of 250 μA, and an on‐resistance of 331 mΩ. Finally, a boost converter is used to evaluate the performance of the cascode GaN FET in power conversion applications.     

GaAs enhancement mode FET-tunnel diode ultra-fast low power inverter and memory cell

A microtunnel diode load for a normally off enhancement mode gallium arsenide field effect transistor provides a compact inverter circuit of fast switching speed and low power consumption. Level shifting is not required, and direct coupling with multiple fan-out causes a comparatively small decrease in speed. The tunnel diode FET logic (TDFL) should be capable of operation at 2 GHz with a power-delay time product of 3.4 fJ for an output node capacitance of 50 fF. The negative characteristic of the tunnel diode combined with the FET provides a compact memory cell. However, advances in the state of the art for producing microtunnel diodes of precisely controlled peak current will be required before a viable TDFL can emerge.     

高性能PWM型DC-DC升压变换器研究

设计了一种单片集成PWM型电流模式升压变换器,芯片内部集成了耐压22V的DMOS功率开关管,开关频率为1.6MHz,采用1.5μmBCD工艺实现。芯片具有很宽的输入电压(2.7~14V)、高效率(85%)、低关断电流、快速暂态响应和低功耗等特性,适宜于用作便携式设备的电源管理,也可作为IP核,嵌入同种工艺下的其它芯片。文中除了对芯片设计方法、思路及主要电路模块结构的设计方案进行讨论外,还提出了减小单片集成开关电源噪声的措施。     

Dithering Skip Modulation, Width and Dead Time Controllers in Highly Efficient DC-DC Converters for System-On-Chip Applications

This paper proposes temperature-independent load sensor (LS), optimum width controller (OWC), optimum dead-time controller (ODC), and tri-mode operation to achieve high efficiency over an ultra-wide-load range. Higher power efficiency and wider loading current range require rethinking the control method for DC-DC converters. Therefore, a highly efficient tri-mode DC-DC converter is invented in this paper for system-on-chip (SoC) applications, which is switched to sleeping mode at very light load condition or to high-speed mode at heavy load condition. The efficiency improvement is upgraded by inserting new proposed dithering skip modulation (DSM) between conventional pulse-width modulation (PWM) and pulse-frequency modulation (PFM). In other words, an efficiency-improving DSM operation raises the efficiency drop because of transition from PWM to PFM. Importantly, DSM mode can dynamically skip the number of gate driving pulses, which is inverse proportional to load current. Simplistically and qualitatively stated, the novel load sensor automatically selects optimum modulation method and power MOSFET width to achieve high efficiency over a wide load range. Moreover, optimum power MOSFET turn-on and turn-off delays in synchronous rectifiers and reduced ground bounce can save much switching loss by current-mode dead-time controller. Experimental results show the tri-mode operation can have high efficiency about 90% over a wide load current range from 3 to 500 mA. Owing to the effective mitigation of the switching loss contributed by optimum power MOSFET width and reduction of conduction loss contributed by optimum dead-times, the novel width and dead-time controllers achieve high efficiency about 95% at heavy load condition and maintain the highly efficient performance to very light load current about 0.1 mA.     

Use of active loads with MSM photodetectors in digital GaAs MESFETphotoreceivers

Illuminated metal-semiconductor-metal (MSM) photodetectors display a current-voltage characteristic that saturates with increasing bias voltage and resembles the output characteristics of a field-effect transistor (FET). It is shown that operating an MSM photodetector with a GaAs FET active load can produce output voltage signal swings of over 80% of the power supply voltage from less than a 1 decade change in the MSM photocurrent, which may in turn be produced by only a 0.1 mW change in the input optical power. This swing allows the circuit to be used as an extremely compact optical input to high-speed digital gate circuits without the need for any intervening amplifiers. For fully monolithic prototype optical input circuits, less than -6 dBm of peak optical input power provided noise-free switching of a standard buffered FET logic (BFL) inverter from DC up to 25 MHz     

Switching characteristics of logic gates addressed by picosecond light pulses

We report detailed characteristics of the response of GaAs FET logic gates to picosecond light pulses, from which optimum conditions for optically induced logic level switching are deduced. These characteristics include plots of photoinduced output electrical signals versus input dc voltages for the illumination of individual FET's in NOR gates and Inverters. Optically induced logic level switching has applications in high-speed data processing in gigahertz-rate communications links, contactless diagnosis of logic circuits, and picosecond resolution measurements of on-chip response times of logic gates.     

Design and simulation of nanoscale double-gate TFET/tunnel CNTFET

A double-gate tunnel field-effect transistor (DG tunnel FET) has been designed and investigated for various channel materials such as silicon (Si),gallium arsenide (GaAs),alminium gallium arsenide (AlxGa1xAs) and CNT using a nano ViDES Device and TCAD SILVACO ATLAS simulator.The proposed devices are compared on the basis of inverse subthreshold slope (SS),ION/IoFF current ratio and leakage current.Using Si as the channel material limits the property to reduce leakage current with scaling of channel,whereas the AlxGalxAs based DG tunnel FET provides a better ION/IoFF current ratio (2.51 × 106) as compared to other devices keeping the leakage current within permissible limits.The performed silmulation of the CNT based channel in the double-gate tunnel field-effect transistor using the nano ViDES shows better performace for a sub-threshold slope of 29.4 mV/dec as the channel is scaled down.The proposed work shows the potential of the CNT channel based DG tunnel FET as a futuristic device for better switching and high retention time,which makes it suitable for memory based circuits.     

Analysis of sensitivity degradation caused by the flicker noise ofGaAs-MESFETs in fiber-optic receivers

The total input noise current and sensitivity of the fiber-optic receiver was calculated. The flicker noise source was included by adopting a pertinent flicker noise model. Power penalties caused by the flicker noise were calculated for various fiber-optic receivers using the calculated noise current. It has been found that the flicker noise affects the sensitivity over the whole range of the bit rates, and that the total input capacitance is an important parameter affecting the power penalty which is serious in the case of a high-impedance-type p-i-n FET receiver. The optimum feedback resistance for practical p-i-n FET receiver design is also suggested     

Analysis of GaAs FET's for integrated logic

This paper presents an analysis of the speed and power dissipation of various GaAs FET inverter circuits as prototypes of integrated logic circuit design. The analysis provides analytical expressions to assess the switching performance of enhancement-mode and depletion-mode MESFET's and JFET's with respect to switching-speed and power-dissipation capabilities in optimized configurations. Various load elements are described and analyzed for circuit applications. The various logic gates, now under development, are compared in their switching performance and a review of the state of the art is given. Prospects of large-scale integration (LSI) of gigabit logic for GaAs FET's are assessed.     

A model reference adaptive PWM technique

A model reference adaptive (MRA) pulsewidth-modulated (PWM) technique for invertor switching applications is presented and analyzed. With this technique, the near optimal inverter gating signals are determined through a closed-loop process which compares a reference signal to a feedback signal derived from a built-in reference model of the load. In addition to its simplicity of implementation, the proposed PWM technique has the advantages of inherent controlled constant volts-per-Hertz (V/f) ratio operation and jitter-free operation with free-running carrier. Such features are of importance in variable-speed AC-drive applications where V/f control increases the control-circuit complexity and where carrier frequency jumps cause harmful torque/speed transients     

First-order, switched-capacitor, low-pass filter implemented with GaAs insulated-gate FET switches

The application of the GaAs insulated-gate FET in switched-capacitor circuits is demonstrated. This is achieved by constructing a first-order, switched-capacitor, low-pass filter from monolithic GaAs IGFET switches and discrete capacitors. Hysteresis in the FET characteristic is shown to be unimportant. FET switching is shown to be independent of the absolute level of the switching signal.<>     

开关电源电磁干扰滤波器插入损耗的研究

研究了电磁干扰(EMI)滤波器的共模和差模插入损耗(IL)，并进行理论分析和测量；分析了影响IL的各种原因及改进方法。最后，测量了EMI滤波器插入损耗，为了检验EMI滤波器对开关电源的电流(电压)谐波的抑制效果，测量了开关电源的电流(电压)谐波分量，列出了测量数据，并对测量结果进行分析，总结出开关电源传导干扰的特点。测量结果验证了理论计算和分析的正确性。     

Design of Parasitic Inductance Reduction in GaN Cascode FET for High‐Efficiency Operation

This paper presents a method of parasitic inductance reduction for high‐speed switching and high‐efficiency operation of a cascode structure with a low‐voltage enhancement‐mode silicon (Si) metal–oxide–semiconductor field‐effect transistor (MOSFET) and a high‐voltage depletion‐mode gallium nitride (GaN) field‐effect transistor (FET). The method is proposed to add a bonding wire interconnected between the source electrode of the Si MOSFET and the gate electrode of the GaN FET in a conventional cascode structure package to reduce the most critical inductance, which provides the major switching loss for a high switching speed and high efficiency. From the measured results of the proposed and conventional GaN cascode FETs, the rising and falling times of the proposed GaN cascode FET were up to 3.4% and 8.0% faster than those of the conventional GaN cascode FET, respectively, under measurement conditions of 30 V and 5 A. During the rising and falling times, the energy losses of the proposed GaN cascode FET were up to 0.3% and 6.7% lower than those of the conventional GaN cascode FET, respectively.     

Quartz oscillator in complementary m.o.s. technology

A short mathematical method is developed to obtain the drain?source current expression at low voltage of an m.o.s. transistor, and therefore the gain of a complementary m.o.s. invertor. Input/output transfer characteristics are compared with computed theoretical results. A variant of the c.m.o.s. invertor, the passive-charge invertor, gives the best results for supply voltage. Another variant, the mixed-charge invertor, is the most advantageous from the point of view of frequency change with temperature and supply voltage.     

A functional GaAs FET noise model

It is the purpose of this paper to develop a theory upon which the design of low noise FET amplifiers can be based. This is not a fundamenta model of the noise mechanisms in GaAs FET's, but rather, an endeavor to relate physically measurable device capacitances and resistances to the device noise figure and optimum noise source impedance. I will be shown that the noise performance of an FET can be adequately described by two uncorrelated noise sources. One, at the input of the FET, is the thermal noise generated in the various resis, tances in the gate-source loop. This noise source is frequency dependent and it can be calculated from the equivalent circuit of the FET. The second noise source, in the Output of the FET, is frequency independent, and not recognizably related to any measured parameters. This output nise is a function of drain current and voltage. The decomposition of the FET noise into two uncorrelated sources simplifies the design of broad-band low noise amplifiers. Once the equivalent circuit of a device and its noise figure at one frequency are known, the optimum noise source impedance and noise figure over a broad range of frequencies may be calculated. For the device designer this model also may be helpful in balancing input-output noise tradeoffs.     

A novel soft-switching high-frequency transformer isolated three-phase AC-to-DC converter with low harmonic distortion

A high-frequency transformer isolated, fixed-frequency, 3-/spl phi/ single-stage ac-to-dc converter using a boost-integrated bridge converter that employs a new gating scheme is proposed. This converter enjoys natural power factor correction with low line current harmonic distortion and symmetric high frequency voltage and current waveforms while ensuring zero-voltage switching for all the switches for a wide variation in load and line voltage. Various operating modes of the converter are presented and analyzed. Based on the analysis, design curves are obtained and an optimum design is given. A design example is presented. Results obtained from SPICE simulation and a 500 W output experimental prototype are given to verify the performance of the proposed converter for varying load as well as line voltage.     

Designing FET's for broad noise circles

It is shown that the keys to broader noise circles are a lower minimum noise figure and a small optimum generator reflector coefficient. An optimum FET width for the smallest generator reflection coefficient and the broadest noise circles has been demonstrated with 0.25 μm MODFETs. A FET of optimum width also has the lowest noise figure with a 50 Ω generator. An expression is derived showing that the optimum gate width is inversely proportional to frequency, and that the optimum width should be a weak function of gate length for FETs optimally scaled for gate length     

Low-Noise, Low Power Dissipation GaAs Monolithic Broad-Band Amplifiers

Low-noise, low dc power dissipation GaAs monolithic amplifiers have been developed for use in VHF-UHF mobile radio systems. The developed amplifiers have two-stage constuction, where gate width for the first stage is 1000 µm, and for the second stage is 500 pm. Using this circuit configuration, both noise figure and bandwidth have been improved. To maintain the uniformity for the ion-implanted active layers and to reduce gate-source resistance R/sub S/ and gate-drain resistance R/sub D/, the "closely spaced electrode FET" was adopted. The FET enables low drain voltage operation, resulting in low dc power dissipation. The developed amplifier for the FET threshold voltage VT= --0.6 V provides a 3-dB noise figure, less than 170-mW dc power dissipation, 9-MHz-3.9-GHz bandwidth with 16-dB gain. It can operate under a unipolar power source. When external choke inductors were introduced for the amplifier, 120-mW dc power dissipation has been achieved. It has also been demonstrated that the amplifier for V/sub T/= --0.6V, which is inferior to the amplifier for VT= -2.7V regarding gain-bandwidth product and power efficiency under the same dc power dissipation, however, has an acceptable performance for use in the mobile radio systems.