Automatic Virtual Entity Simulation of Conceptual Design Results—Part Ⅱ:Symbolic Scheme Simulation

The development of new products of high quality, low unit cost, and short lead time to market are the key elements required for any enterprise to obtain a competitive advantage. This part of the paper presents a methodology to automatically simulate the conceptual design results in the virtual entity form. To the identified basic mechanisms, their kinematic analysis is carried out by matching basic Barranov trusses, and their virtual entities are modeled based on feature-based technique and encapsulated as one design object. Based on the structures of the basic mechanisms and their connections, a space layout to the mechanical system corresponding to the symbolic scheme is then fulfilled. With the preset-assembly approach, all parts in the mechanical system are put onto proper positions where the constraint equations are met according to the space layout results. In this way, the virtual entity assembly model of the mechanical system relative to the symbolic scheme is set up. The approach presented in this paper can not only obtain innovative conceptual conceptual design results, but also can evaluate their performances under 3-D enviroment efficently.     

Layout aid for the design of VLSI circuits

VLSI (very large scale integration) circuits are the most complex chips yet developed, typically having over 50 000 transistors. Some examples are a 16 kbit static RAM chip or a 16 bit microprocessor chip. The complexity of these chips necessitates the invention of new techniques in order to reduce production costs and design time.The design cycle of an IC (integrated circuit) consists of a series of complex tasks often requiring more than a year to complete. As ICs grow in complexity, the cycle time increases and could potentially become too lengthy to be realistic. One of the most time consuming tasks in the design cycle is laying out a circuit. This paper describes a new layout aid that will significantly reduce the layout time.In this new layout aid, a designer is required to digitize an approximate layout, fully routed but loosely placed. From this approximate layout, two graphs are created, one representing the relative vertical position of each circuit element in the loose sketch, and the other representing their relative horizontal position. In the graphs, modes indicate the coordinate locations and branches indicate minimum spacing requirements due to design rules. An optimization technique, namely the longest path algorithm, is invoked to compact the circuit. In the original layout, design rule violations may be overlooked, which will prevent the longest path algorithm from converging. A method is devised to resolve this problem. Results of empirical testing of the new layout aid are reported.     

An analog implementation of discrete-time cellular neural networks

An analog circuit structure for the realization of discrete-time cellular neural networks (DTCNNs) is introduced. The computation is done by a balanced clocked circuit based on the idea of conductance multipliers and operational transconductance amplifiers. The circuit is proposed for a one-neighborhood on a hexagonal grid, but can also be modified to larger neighborhoods and/or other grid topologies. A layout was designed for a standard CMOS process, and the corresponding HSPICE simulation results are given. A test chip containing 16 cells was fabricated, and measurements of the transfer characteristics are provided. The functional behavior is demonstrated for a simple example.     

一种船用气象要素相对湿度传感器

针对陆地用气象要素相对湿度传感器难以适应海洋高湿、高盐雾、高腐蚀环境的问题,研制了一船用气象要素相对湿度传感器。采用高精度湿敏元件,设计出频率发生电路,将空气相对湿度的变化量转换为频率信号;通过设计的频率电压转换电路将频率信号转换为电压信号;设计的线性化调理电路将变化的电压信号进行线性化处理,使电压的变化能够线性化地对应于空气相对湿度的变化。通过特殊结构和可靠性设计,满足了气象要素相对湿度传感器的海洋环境适应性。测试结果表明:研制的船用气象要素相对湿度传感器测量精度高、线性化好,能够适应于海洋环境。     

CMOS单元电路版图的自动设计

本文描述了ＣＭＯＳ单元电路版图自动设计程序是自动电路版图设计系统的一个组成部分，它通过一列变换，将单元电器描述翻译成单元电路版图的几何描述。其特点是允许单元内多端口线网布和允许在单元四周指定端口，并对单元电路版图进行优化，因此，只要输入单元电路描述，便可自动产生单元电路的版图文件。     

An extraction-based verification methodology for MEMS

Micromachining techniques are being increasingly used to develop miniaturized sensor and actuator systems. These system designs tend to be captured as layout, requiring extraction of the equivalent microelectromechanical circuit as a necessary step for design verification. This paper presents an extraction methodology to (re-)construct a circuit schematic representation from the layout, enabling the designer to use microelectromechanical circuit simulators to verify the functional behavior of the layout. This methodology uses a canonical representation of the given layout on which feature-based and graph-based recognition algorithms are applied to generate the equivalent extracted schematic. Extraction can be performed to either the atomic level or the functional level representation of the reconstructed circuit. The choice of level in hierarchy is governed by the trade off between simulation time and simulation accuracy of the extracted circuit. The combination of the MEMS layout extraction and lumped-parameter circuit simulation provides MEMS designers with VLSI-like tools enabling faster design cycles, and improved design productivity     

新型电路版图布局布线算法设计

调研了电路自动布局布线技术的国内外研究现状,在此基础上设计了一种面向中等规模电路布局布线算法,主要用于大型版图设计软件的模块测试环节,为用户提供各模块初步的布线布局结果,方便用户高效查找并修正错误点,填补了我国在相关领域的空白.建立了超图模型并转换为图模型,改进了Stoer-Wagner算法并利用该算法和Fiduccia-Mattheyses算法对图进行了基于最小割理论的划分,从而构建出一棵划分树.在这棵树的基础上设计了一种二元相对移动算法来确定各个电路元件的位置,大大降低了布局拥挤度,提高了美观度,对于数百元件的电路均能在0.5s内得出布局结果.基于A*算法在多个方面做了改进,提高了布线速度,对于线路数1000以下的元件能在0.1 s～60 s内得出结果,实现了100％ 布通率以及均匀的布局布线效果.     

Structure and spatial consistency of network-based space layouts for building and product design

Network-based space layouts are schematic models of whole spaces, subspaces, and related physical elements. They address diverse space modeling needs in building and product design. A schema (data model) for network-based space layouts is defined that is influenced by existing space schemas. Layout elements and selected spatial relations form a geometric network. The network is embedded in 3-space and facilitates analysis with graph and network algorithms. Spatial constraints on layout elements and spatial relations extend the schema to support spatial consistency checking. Spatially consistent layouts are required for reliable network analysis and desirable for layout modification operations. An operation is introduced that evaluates spatial constraints to detect and semi- or fully-automatically resolve spatial inconsistencies in a layout. A layout modeling system prototype that includes proof-of-concept implementations of the layout schema extended by spatial constraints and the inconsistency resolution operation is described. Layouts of a floor of an office building and a rack server cabinet have been modeled with the system prototype.     

Symbolic pattern manipulation of Karnaugh-Veitch maps for pneumatic circuits

Pneumatics continue to play a vital role in low-cost automation. The designing of pneumatic control circuits has to date been a slow manual process. This paper describes the computational symbolic manipulation of the Karnaugh-Veitch (KV) map which is the heart of the prototype expert system called PNEUMAES. The symbolic manipulation of a KV map is governed by two sets of generic rules for signal flow plotting and for logic equation minimisation applicable for complex pneumatic circuits. As the complexity of the circuit increases, the symbolic manipulation of a KV map leads to the combinatorial explosion problem. Because of this problem, PNEUMAES can only automatically generate pure pneumatic circuit design equations which will yield minimised circuit configuration for up to four cylinders with auxiliary control valves. A case study is included and issues and problems relating to the implementation of the KV map are discussed. Symbolic and sub-symbolic learning approaches are suggested as a means by which the search space of the symbolic patterns of the KV map can be pruned.     

基于坐标变换的图形自适应排列算法

为了解决基于网格技术的图形排列算法在处理可变尺寸图形排列问题上的局限性,基于几何变换思想,建立了有界平面上图形自适应排列的数学模型,并证明了其正确性,进而提出了基于坐标变换的图形自适应排列算法。此算法用图形平移变换方式代替网格划分方法在有界视图上部署图形元素,其时间复杂性为O(N)。最后将所获得的算法应用到面向中央空调节能控制的软PLC系统上,基于9类指令图形、3类测试案例的测试结果表明：本文算法能以较低的CPU占用率实现图形有序排列的效果,具有较高的运行速率与稳定性。     

An integrated circuit layout design system

An integrated circuit layout design system is presented. The system is effectively combined with a combinatorial optimization technique and man/machine interaction. This optimization technique allows wiring and placement of components to be determined simultaneously. By means of a c.r.t. display, the layout design of an integrated circuit chip is finally improved.     

基于认知规律的用户界面信息布局设计方法

为进一步提高工作效率,提出一种基于人的认知因素和几何位置匹配因素的界面信息布局设计方法。建立任务模型,获取合理的待布局任务信息元素;从人的认知规律中提取3个布局原则,分别将其以定量化的形式构建数学模型,以目标函数变量的形式作用于界面布局过程中;引入带有惯性权重的粒子群算法求解目标函数,对界面中所有待布局元素的几何位置寻求最优布局方案。以隧道应急救援培训系统的决策界面布局为例,提出解决方案并验证该方法的可行性。实验结果表明,该方法具有一定的实用性。     

Production layout design system by GA with one by one encoding method

One of the problems encountered in the design and implementation of a flexible transfer line (FTL) is the layout design of the FTL. The layout design of the FTL has an important impact on material handling. In this paper, we develop a LAyout Design system (LAD). LAD can find FTL layout design including the buffer size between each pair of FTL machine tools. LAD divides the goal plant into cells and uses GA to find the efficient FTL layout design. In order to carry out GA, we propose a new encoding method to express GA individual. The new encoding method is called a One by One Encoding Method (OOEM). OOEM generates the elements of the individual one by one with the sequence of relative direction of the FTL components. The sequence of individual elements indicates the sequence of machine tools and conveyer buffer spaces of FTL. The developed LAD based on the proposed OOEM is not limited to a single static environment plant, but is highly flexible within the plant structure. An application example was developed, and after a number of generations based on LAD, an efficient FTL layout design was able to be found. This work was presented in part at the 13th International Symposium on Artificial Life and Robotics, Oita, Japan, January 31–February 2, 2008     

基于CPLD的相控声发射系统设计与实现

提出一种新的增强声源指向性的电路设计方法,设计了基于复杂可编程逻辑器件(CPLD)的相控声发射系统.该系统由滤波采样、信号延时、按键显示、D/A转换等电路组成,通过控制声波在空气中波阵面的耦合,实现声波的相控发射.试验表明,该系统能够较明显地增强声源指向性.     

The Magic VLSI Layout System

Magic is a new IC layout system that includes several facilities traditionally contained in separate batch-processing programs. Magic incorporates expertise about design rules, connectivity, and routing directly into the layout editor and uses this information to provide several unusual features. They include a continuous design-rule checker that operates in background and maintains an up-to-date picture of violations; a hierarchical circuit extractor that only re-extracts portions of the circuit that have changed; an operation called plowing that permits interactive stretching and compaction; and a suite of routing tools that can work under and around existing connections in the channels. A design style called logs and a data structure called corner stitching are used to achieve an efficient implementation of the system.     

Data Layout Transformation Exploiting Memory-Level Parallelism in Structured Grid Many-Core Applications

We present automatic data layout transformation as an effective compiler performance optimization for memory-bound structured grid applications. Structured grid applications include stencil codes and other code structures using a dense, regular grid as the primary data structure. Fluid dynamics and heat distribution, which both solve partial differential equations on a discretized representation of space, are representative of many important structured grid applications. Using the information available through variable-length array syntax, standardized in C99 and other modern languages, we enable automatic data layout transformations for structured grid codes with dynamically allocated arrays. We also present how a tool can guide these transformations to statically choose a good layout given a model of the memory system, using a modern GPU as an example. A transformed layout that distributes concurrent memory requests among parallel memory system components provides substantial speedup for structured grid applications by improving their achieved memory-level parallelism. Even with the overhead of more complex address calculations, we observe up to 10.94X speedup over the original layout, and a 1.16X performance gain in the worst case.