A low power variable length decoder for MPEG-2 based on nonuniformfine-grain table partitioning

Variable length coding is a widely used technique in digital video compression systems. Previous work related to variable length decoders (VLDs) was primarily aimed at high throughput applications, but the increased demand for portable multimedia systems has made power a very important factor. In this paper, a data-driven variable length decoding architecture is presented, which exploits the signal statistics of variable length codes to reduce power. The approach uses fine-grain lookup table (LUT) partitioning to reduce switched capacitance based on codeword frequency. The complete VLD for MPEG-2 has been fabricated and consumes 530 μW at 1.35 V with a video rate of 48-M discrete cosine transform samples/s using a 0.6-μm CMOS technology. More than an order of magnitude power reduction is demonstrated without performance loss compared to a conventional parallel decoding scheme with a single LUT     

Interleaving and decoding scheme for a product code for a mobiledata communication

We propose a new ordered decoding scheme for a product code for mobile data communications. The ordered decoding scheme determines the order of decoding for both row and column component codewords according to the probability of decoding the component codeword correctly. Component codewords are decoded independently. To randomize burst errors in both row and column codewords, a diagonal interleaving scheme is used for code symbols in the codeword. It is shown that the ordered decoding scheme combined with diagonal interleaving improves the performance of a product code with reasonably long code length for mobile data communications     

MPEG-2视频码流分解的VHDL描述与验证

本文提出一个ＭＰＥＧ－２视频解码中码流分解的硬件设计,包括解码控制和变长码解码。一些新的硬件设计,如：将宏块和块控制作为主要状态;采用桶形移位缓冲器并行解变长码;将变长码的长度计算和解码分别进行;将码表分割成多个小码表等等,保证ＭＰＥＧ－２ＭＰ＠ＭＬ的实时解码,并为更复杂的应用提供了扩展的余地。本文中的设计是ＭＰＥＧ－２解码ＡＳＩＣ ＶＬＳＩ设计工作的一部分。     

Variable-rate coding for meteor-burst communications

The performance of variable-rate Reed-Solomon error-control coding for meteor-burst communications is considered. The code rate is allowed to vary from codeword to codeword within each packet, and the optimum number of codewords per packet and optimum rates for the codewords are determined as a function of the length of the message and the decay rate for the meteor trail. The resulting performance is compared to that obtained from, fixed-rate coding. Of central importance is the derivation of tractable expressions for the probability of correct decoding for bounded-distance decoding on a memoryless channel with a time-varying symbol error probability. A throughout measure is developed that is based on the probability distribution of the initial signal-to-noise ratio     

Permuted M-matrices for the reduction of phase-induced intensity noise in optical CDMA network

Two codeword families and the corresponding encoder/decoder schemes are present for spatial/frequency optical code-division multiple-access communications. These 2-D codewords have multiple weights per row and can be encoded/decoded via compact hardware. With the proposed decoding mechanism, the intended user will reject interfering users and multiple-access interference is fully eliminated. In addition, the power of the same wavelength contributed by all interfering codewords is split and detected by distinct photodiodes in the decoder. Thus the performance degradation due to the beat noise arising in the photodetecting process is improved, as compared with the traditional 1-D coding scheme, and a larger number of active users is supported under a given bit-error rate.     

Advances in the performance of Reed-Solomon codes

This paper presents generalized expressions for the probabilities of correct decoding and decoder error for Reed-Solomon (RS) codes. In these expressions, the symbol error and erasure probabilities are different in each coordinate in a codeword. The above expressions are used to derive the expressions for reliability and delay for Type-I hybrid ARQ (HARQ-I) systems when each symbol in a packet (multiple codewords per packet) has unique symbol error and erasure probabilities. Applications of the above results are demonstrated by analyzing a bursty-correlative channel in which the symbols and codewords within the packet are correlated     

Distributed decoding of cyclic block codes using a generalizationof majority-logic decoding

One-step majority-logic decoding is one of the simplest algorithms for decoding cyclic block codes. However, it is an effective decoding scheme for very few codes. This paper presents a generalization based on the “common-symbol decoding problem.” Suppose one is given M (possibly corrupted) codewords from M (possibly different) codes over the same field; suppose further that the codewords share a single symbol in common. The common-symbol decoding problem is that of estimating the symbol in the common position. This is equivalent to one-step majority logic decoding when each of the “constituent” codes is a simple parity check. This paper formulates conditions under which this decoding is possible and presents a simple algorithm that accomplishes the same. When applied to decoding cyclic block codes, this technique yields a decoder structure ideal for parallel implementation. Furthermore, this approach frequently results in a decoder capable of correcting more errors than one-step majority-logic decoding. To demonstrate the simplicity of the resulting decoders, an example is presented     

High Throughput Parallel Decoding Method for H.264/AVC CAVLC

A high throughput parallel decoding method is developed for context‐based adaptive variable length codes. In this paper, several new design ideas are devised and implemented for scalable parallel processing, a reduction in area, and a reduction in power requirements. First, simplified logical operations instead of memory lookups are used for parallel processing. Second, the codes are grouped based on their lengths for efficient logical operation. Third, up to M bits of the input stream can be analyzed simultaneously. For comparison, we designed a logical‐operation‐based parallel decoder for M=8 and a conventional parallel decoder. High‐speed parallel decoding becomes possible with our method. In addition, for similar decoding rates (1.57 codes/cycle for M=8), our new approach uses 46% less chip area than the conventional method.     

Improved Analysis of List Decoding and Its Application to Convolutional Codes and Turbo Codes

A list decoder generates a list of more than one codeword candidates, and decoding is erroneous if the transmitted codeword is not included in the list. This decoding strategy can be implemented in a system that employs an inner error correcting code and an outer error detecting code that is used to choose the correct codeword from the list. Probability of codeword error analysis for a linear block code with list decoding is typically based on the "worst case" lower bound on the effective weights of codewords for list decoding evaluated from the weight enumerating function of the code. In this paper, the concepts of generalized pairwise error event and effective weight enumerating function are proposed for evaluation of the probability of codeword error of linear block codes with list decoding. Geometrical analysis shows that the effective Euclidean distances are not necessarily as low as those predicted by the lower bound. An approach to evaluate the effective weight enumerating function of a particular code with list decoding is proposed. The effective Euclidean distances for decisions in each pairwise error event are evaluated taking into consideration the actual Hamming distance relationships between codewords, which relaxes the pessimistic assumptions upon which the traditional lower bound analysis is based. Using the effective weight enumerating function, a more accurate approximation is achieved for the probability of codeword error of the code with list decoding. The proposed approach is applied to codes of practical interest, including terminated convolutional codes and turbo codes with the parallel concatenation structure     

Design of High‐Speed CAVLC Decoder Architecture for H.264/AVC

In this paper, we propose hardware architecture for a high‐speed context‐adaptive variable length coding (CAVLC) decoder in H.264. In the CAVLC decoder, the codeword length of the current decoding block is used to determine the next input bitstreams (valid bits). Since the computation of valid bits increases the total processing time of CAVLC, we propose two techniques to reduce processing time: one is to reduce the number of decoding steps by introducing a lookup table, and the other is to reduce cycles for calculating the valid bits. The proposed CAVLC decoder can decode 1920×1088 30 fps video in real time at a 30.8 MHz clock.     

Symbol re-mapping method for improvement of TML-1 VLC coder

To improve the efficiency of variable length codeword (VLC) encoding in TML-1 for H.26L, the authors propose to adaptively change the mapping relationship between a symbol and its bit pattern in the VLC table, based on a local measurement of the symbol probability. Simulation results show that the proposed method gives a ~30 and 37% reduction in the average bit rate for macro block type and coded block pattern information, respectively     

Single Chip Dual–Issue RISC Processor for Real–Time MPEG–2 Software Decoding

A single chip system for real–time MPEG–2 decoding can be created by integrating a general purpose dual–issue RISC processor, with a small dedicated hardware for the variable length decoding (VLD) and block loading processes; a 32KB instruction RAM; and a 32KB data RAM. The VLD hardware performs Huffman decoding on the input data. The block loader performs the half–sample prediction for motion compensation and acts as a direct memory access (DMA) controller for the RISC processor by transferring data between an external 2MB DRAM and the internall 32 KB data RAM. The dual-issue RISC processor, running at 250MHz, is enhanced with a set of key sub-word and multimedia instructions for a sustained peak performance of 1000 MOPS. With this setup for MPEG-2 decoding applications, bi-directionally predicted non-intra video blocks are decoded in less than 800 cycles, leading to a single-chip, real-time MPEG-2 decoding system.     

Analysis, design, and iterative decoding of double seriallyconcatenated codes with interleavers

A double serially concatenated code with two interleavers consists of the cascade of an outer encoder, an interleaver permuting the outer codeword bits, a middle encoder, another interleaver permuting the middle codeword bits, and an inner encoder whose input words are the permuted middle codewords. The construction can be generalized to h cascaded encoders separated by h-1 interleavers, where h>3. We obtain upper bounds to the average maximum likelihood bit-error probability of double serially concatenated block and convolutional coding schemes. Then, we derive design guidelines for the outer, middle, and inner codes that maximize the interleaver gain and the asymptotic slope of the error probability curves. Finally, we propose a low-complexity iterative decoding algorithm. Comparisons with parallel concatenated convolutional codes, known as “turbo codes”, and with the proposed serially concatenated convolutional codes are also presented, showing that in some cases, the new schemes offer better performance     

An efficient coding system for long source sequences

The Elias source coding scheme is modified to permit a source sequence of practically unlimited length to be coded as a single codeword using arithmetic of only limited precision. The result is shown to be a nonblock arithmetic code of the first in, first out (FIFO) type-- source symbols are decoded in the same order as they were encoded. Codeword lengths which are near optimum for the specified statistical properties of the source can be achieved. Explicit encoding and decoding algorithms are Provided which effectively implement the coding scheme. Applications to data compression and cryptography are suggested.     

基于哈希表查询的CAVLC解码查表优化算法

主要针对当前H.264/AVC中CAVLC中的标准解码方法 TLSS查表时存在查表时间长的问题,提出了一种全新的基于哈希表快速查询的CAVLC解码查表优化方法。在CAVLC解码查表中引入哈希表查找技术,提高了CAVLC解码查表速度,降低了CAVLC解码中不规则可变长码表(UVLCT)的码字获取时间,从而减少CAVLC解码查表时间。实验仿真结果表明,在没有丝毫降低视频解码质量前提下,相比于标准TLSS方法,提出的新算法可以提高约18%~22%的表查找时间。     

An efficient hybrid decoding algorithm for Reed-Solomon codes based on bit reliability

The paper presents a computationally efficient hybrid reliability-based decoding algorithm for Reed-Solomon (RS) codes. This hybrid decoding algorithm consists of two major components, a re-encoding process and a successive erasure-and-error decoding process for both bit and symbol levels. The re-encoding process is to generate a sequence of candidate codewords based on the information provided by the codeword decoded by an algebraic decoder and a set of test error patterns. Two criteria are used for testing in the decoding process to reduce the decoding computational complexity. The first criterion is devised to reduce the number of re-encoding operations by eliminating the unlikely error patterns. The second criterion is to test the optimality of a generated candidate codeword. Numerical results show that the proposed decoding algorithm can achieve either a near-optimum error performance or an asymptotically optimum error performance.     

MIMO CDMA系统中一种新的循环空时分组编译码方法

该文提出了MIMO CDMA系统中一种新的空时分组编译码方法,称为循环空时分组码(Cyclic Space-Time Block Code,C-STBC),它是将输入信息进行分组循环编码,然后对循环编码后的码字通过不同的天线分别采用不同的扩频码扩频后发射出去。这种CDMA系统下的循环空时分组码对任意的发射天线数都能达到满编码速率和满分集度,且其译码与传统的空时分组码一样简单。仿真结果验证了这种循环空时分组码优于传统的空时分组码。     

一种混合定变长虚拟块游程编码的测试数据压缩方案

 文章提出了一种混合定变长虚拟块游程编码的测试数据压缩方案,该方案将测试向量级联后分块,首先在块内找一位或最大一位表示,再对块内不能一位表示的剩下位进行游程编码,这样减少了游程编码的数据量,从而突破了传统游程编码方法受原始测试数据量的限制.对ISCAS 89部分标准电路的实验结果显示,本文提出的方案在压缩效率明显优于类似的压缩方法,如Golomb码、FDR码、VIHC码、v9C码等.     

纠正随机错误与长突发删除的多进制乘积码研究

考虑多进制LDPC码的符号特性，以及对其残留错误和删除的分析，本文采用多进制LDPC码作为内码，相同Galois域下的高码率RS码作为外码来构造多进制乘积码；并提出了一种低复杂度的迭代译码方案，减少信息传输的各类错误。在译码时，只对前一次迭代中译码失败的码字执行译码，并对译码正确码字所对应的比特初始概率信息进行修正，增强下一次迭代多进制LDPC译码符号先验信息的准确性，减少内码译码后的判决错误，从而充分利用外码的纠错能力。仿真结果显示，多进制乘积码相较于二进制LDPC乘积码有较大的编码增益，并通过迭代进一步改善了性能，高效纠正了信道中的随机错误和突发删除。对于包含2%突发删除的高斯信道，在误比特率为10-6时，迭代一次有0.4 dB左右的增益。      

Hybrid ARQ scheme using interleaved Reed-Solomon codes in apower-controlled DS-CDMA cellular system

A new hybrid automatic repeat request (ARQ) scheme is proposed for data transmission in a power-controlled direct sequence (DS) code division multiple access (CDMA) system cellular system. The data frame is composed of interleaved Reed-Solomon codes. The depth of interleaving is determined by a power-control interval. After decoding each codeword with algebraic decoding, the post-decoding processor decides whether to accept the codeword or to discard it by using channel state information from the power-control processor. The proposed hybrid ARQ scheme significantly reduces the probability of undetected error among accepted codewords without significantly reducing the throughput