CMOS analog/digital circuit of the hysteresis McCulloch-Pitts neuron for Ramsey numbers

A parallel algorithm for finding Ramsey numbers is presented where analog/digital CMOS circuits for the hysteresis McCulloch-Pitts binary neuron are described. The hysteresis McCulloch-Pitts binary neuron model is used in order to suppress the oscillatory behaviors of neural dynamics so that the convergence time is shortened. The proposed algorithm using the hysteresis McCulloch-Pitts binary neuron found five Ramsey numbers. The analog CMOS sigmoid circuit with variable gain controls has been fabricated and tested using the SAC data acquisition board interfaced with a TMS 32010 processor. Hysteresis can be implemented by the positive feedback in the fabricated CMOS analog circuit.     

一种基于符号逻辑的神经元模型和电路实现

为了实现基于符号逻辑的神经网络系统,本文定义了一种逻辑神经元模型,并采用了电流型CMOS工艺实现这种神经元电路的各种逻辑功能,最后通过电路模拟,证明设计的正确性。     

Design and characterization of analog VLSI neural network modules

A systematic method for testing large arrays of analog, digital, or mixed-signal circuit components that constitute VLSI neural networks is described. This detailed testing procedure consists of a parametric test and a behavioral test. Characteristics of the input neuron, synapse, and output neuron circuits are used to distinguish between faulty and useful chips. Stochastic analysis of the parametric test results can be used to predict chip yield information. Several measurement results from two analog neural network processor designs that are fabricated in 2 μm double-polysilicon CMOS technologies are presented to demonstrate the testing procedure     

Novel CMOS sampled-data VLSI implementation of artificial neural networks

A mixed-mode VLSI implementation of artificial neural networks offers a tradeoff solution for speed, area saving, and flexibility. A novel CMOS sampled-data programmable synapse and a simple CMOS analogue neuron have been developed. Using a 1.2 mu m CMOS technology, the synapse consumed 120*120 mu m/sup 2/ and the neuron consumed 120*260 mu m/sup 2/.<>     

A concurrent error detection IC in 2-μm static CMOS logic

When a comprehensive fault model is considered, static CMOS VLSI has long been prohibited from realizing concurrent error detecting (CED) circuits due to the unique analog faults (bridging and stuck-on faults). In this paper, we present the design, fabrication and testing of an experimental chip containing the integration of a totally self-checking (TSC) Berger code checker and a strongly code disjoint (SCD) built-in current sensor (BICS). This chip was fabricated by MOSIS using 2 μm p-well CMOS technology. In chip tests, all implanted faults, including analog faults, were detected as expected. We also show that the self-exercising mechanism of the SCD BICS is indeed functioning properly. This is the first demonstration of a working static CMOS CED chip     

An experimental analog VLSI neural network with on-chip back-propagation learning

Analog VLSI implementations of artificial neural networks are usually considered efficient for the small area and the low power consumption they require, but very poor in terms of programmability. In this paper, we present an approach to the design of analog VLSI neural information-processing systems with on-chip learning capabilities. We describe a set of analog circuits for implementing the neural computational primitives of a Multi-Layer Perceptron, including the ones supporting a gradient-based learning algorithm (Back Propagation). Only supervision tasks are managed off chip.An experimental chip has been designed and fabricated using a standard digital 1.5 m CMOS N-well technology. The chip contains 4 neurons and 32 synapses organized into a single-layer architecture with 8 inputs and 4 outputs. Measures illustrating the chip behavior during learning are reported.     

A VLSI chip set for a large-scale parallel inference machine: PIM/m

The authors present three VLSI chips-a processor (PU) chip, a cache memory (CU) chip, and a network control (NU) chip-for a large-scale parallel inference machine. The PU chip has been designed to be adapted to logic programming languages such as PROLOG. The CU chip implements a hardware support called `trial buffer' which is suitable for the execution of the PROLOG-like languages. The NU chip makes it possible to connect 256 processing elements in a mesh network. The parallel inference machine (PIM/m) runs a PROLOG-like network-based operating system called PIMOS as well as many applications and has a peak performance of 128 mega logical inferences per second (MLIPS). The PU chip containing 384000 transistors is fabricated in a 0.8 μm double-metal CMOS technology. The CU chip and the NU chip contain 610000 and 329000 transistors, respectively. They are fabricated in a 1.0 μm double-metal CMOS technology. A cell-based design method is used to reduce the layout design time     

MARVLE: a VLSI chip for data compression using tree-based codes

Describes the architecture and design of a CMOS VLSI chip for data compression and decompression using tree-based codes. The chip, called MARVLE, implements a memory-based architecture for variable length encoding and decoding based on tree-based codes. The architecture is based on an efficient scheme of mapping the tree representing any binary code onto a memory device. A prototype 2-mm CMOS VLSI chip has been designed, verified, and fabricated by the MOSIS facility. The chip has a 512×12 static RAM with an access time of 4 ns and logic circuitry for compression as well as decompression. The chip occupies a silicon area of 6.8 mm×6.9 mm and consists of 49695 transistors. The prototype chip yields a compression rate of 95.2 Mb/s and a decompression rate of 60.6 Mb/s with a clock rate of 83.3 MHz. The VLSI hardware can be used to implement the JPEG baseline compression scheme     

A versatile half-micron complementary BiCMOS technology formicroprocessor-based smart power applications

A modular, high density 0.5 μm Complementary BiCMOS technology with integrated high-voltage Lateral Diffused MOS (LDMOS) and conductivity modulated Lateral Insulated Gate Bipolar Transistor (LIGBT) structures designed for high performance, multi-functional integrated circuit applications is described. The advantages of VLSI processing and 0.5 μm compatible layout rules have been applied to the design and fabrication of the tight-pitch high-voltage devices without sacrificing the performance of 0.5 μm dual-poly (N+/P+) gate CMOS and complementary vertical bipolar transistors. Single chip integration of VLSI microprocessors with high-voltage and/or high-current input and output functions for “Smart Power” applications can be achieved using this technology     

Model for yield and manufacturing prediction on VLSI designs foradvanced technologies, mixed circuitry, and memories

A yield model has been developed and validated for use in optimizing VLSI floorplanning in next generation products. The model successfully predicts yields and costs on a variety of products in CMOS, bipolar, and BiCMOS process flows from low cost DIP's and QFP's to more complex PGAs and flip chip package solutions. This paper discusses how the model was developed for use in evaluating the viability of next generation VLSI solutions. The model takes into account variables such as layout sensitivity, circuit redundancy, and learning curves in wafer, assembly, and test processing in determining the total manufacturing cost     

A reconfigurable VLSI neural network

Due to the variety of architectures that need be considered while attempting solutions to various problems using neural networks, the implementation of a neural network with programmable topology and programmable weights has been undertaken. A new circuit block, the distributed neuron-synapse, has been used to implement a 1024 synapse reconfigurable network on a VLSI chip. In order to evaluate the performance of the VLSI chip, a complete test setup consisting of hardware for configuring the chip, programming the synaptic weights, presenting analog input vectors to the chip, and recording the outputs of the chip, has been built. Following the performance verification of each circuit block on the chip, various sample problems were solved. In each of the problems the synaptic weights were determined by training the neural network using a gradient-based learning algorithm which is incorporated in the experimental test setup. The results of this work indicate that reconfigurable neural networks built using distributed neuron synapses can be used to solve various problems efficiently     

Optimization of device area and overall delay for CMOS VLSI designs

This paper addresses specific design tradeoffs that should be considered relative to CMOS VLSI designs using gate-array, semi-custom, or full-custom implementations. The main focus is on design optimization for speed and device area and on meeting the on-chip load drive requirements using one- and two-dimensional expansion techniques. Detailed comparisons are made between the effectiveness of the various design options in their ability to yield a specific performance within speed and/or area constraints while driving on-chip loads with and without geometrical constraints. These comparisons result in a number of design curves that cover the range of full CMOS custom design, for which two-dimensional scaling can be optimally utilized, to those cases involving semi-custom and gate-array designs for which geometric constraints exist (fixed height cells or fixed device sizes). A figure of merit is defined that relates speed and area to each specific circuit implementation, indicating that it can be used to make an effective comparison between overall performance and design option. It is finally suggested that a chip layout approach can be adopted that is useful for implementing any of the design options discussed.     

Analog ASIC for improved temperature drift compensation of a high sensitive porous silicon pressure sensor

The paper focuses on the design of a CMOS analog ASIC for temperature-drift compensation of a high sensitivity piezoresistive micro-machined porous silicon pressure sensor to avoid analog-to-digital conversion, limit chip area and reduce power consumption. For implementing the compensation circuitry, multilayered perceptron (MLP) based artificial neural network (ANN) with inverse delayed function model of neuron has been optimized. The temperature drift compensation CMOS ASIC has been implemented to make porous silicon pressure sensor an excellent SMART porous silicon pressure sensor. Using the compensation circuit, the error in temperature-drift has been minimized from 93% to about 0.5% as compared to 3% using conventional neuron model in the temperature range of 25–80°C. The entire circuit has been designed using 0.35 μm AMS technology model and simulated using mentor graphics ELDO Simulator.     

A self-learning neural network chip with 125 neurons and 10 Kself-organization synapses

A learning neural network LSI chip is described. The chip integrates 125 neuron units and 10K synapse units with the 1.0 μm double-poly-Si, double-metal CMOS technology. Most of this integration has been realized by using a mixed design architecture of digital and analog circuits. The fully feedback connection network LSI can memorize at least 15 patterns with 50 μs learning time for each pattern. Under the condition that each test vector keeps a Hamming distance of 6 from memorized pattern, a correct association rate of 98% is obtained. The relaxation time is 1 to 2 μs. This chip consumes less than 7.5 W     

ANN based CMOS ASIC design for improved temperature-drift compensation of piezoresistive micro-machined high resolution pressure sensor

The paper investigates the temperature-drift compensation of a high resolution piezoresistive pressure sensor using ANN based on conventional neuron model as also the inverse delayed function model of neuron. Using the delayed neuron model, an improvement in temperature-drift compensation has been obtained compared to the conventional neuron model. The CMOS analog ASIC design of a feed forward neural network using the inverse delayed function model of self connectionless neuron for the precise temperature-drift compensation has been presented. The inverse tan-sigmoid function is realized in CMOS implementation by Gilbert multiplier, differential adder and a cubing circuit. The entire design of the circuit has been done using AMS 0.35 μm CMOS model and simulated using Mentor Graphics ELDO simulator. Using the inverse delayed function model of neuron a mean square error of the order of 10⁻⁷ of the neural network has been obtained against a mean square error of the order of 10⁻³ using conventional neuron model for the same architecture of ANN. This brings down the error from 9% for uncompensated sensor to 0.1% only for compensated sensor using the delayed model of neuron in the temperature range of 0-70 °C. Using conventional neuron based ANN compensation, the error is reduced to 1% error.     

VLSI Implementation of a Neural Model Using Spikes

The paper presents a VLSI approach to approximate thereal-time dynamics of a neuron model inspired from the classicalmodel of Hodgkin and Huxley, in which analog inputs and outputsare represented by short spikes. Both the transient and the steady-statebehaviours of these circuits depend only on process-independentlocal ratios, thus enabling single or multiple-chip VLSI implementationsof very large analog neural networks in which parallelism, asynchronyand temporal interactions are kept as important neural processingfeatures. Measurements on an integrated CMOS prototype confirmexperimentally the expected electrical and temporal behavioursof the proposed neural circuits and illustrate some outstandingfunctional features of the neural model: spike-mediated modulationof the neural activity, self-regulation of the total activityin neural groups, and emulation of temporal interaction mechanismswith well controlled time constants at different scales.     

CMOS工艺多功能数字芯片的输出缓冲电路设计

为了提高数字集成电路芯片的驱动能力,采用优化比例因子的等比缓冲器链方法,通过Hspice软件仿真和版图设计测试．提出了一种基于CSMC2P2M0．6μmCMOS工艺的输出缓冲电路设计方案。本文完成了系统的电原理图设计和版图设计,整体电路采用Hspice和CSMC2P2M的0．6μmCMOS工艺的工艺库（06mixddct02v24）仿真,基于CSMC2P2M0．6μmCMOS工艺完成版图设计,并在一款多功能数字芯片上使用,版图面积为1mm×1mm,并参与MPW（多项目晶圆）计划流片。流片测试结果表明,在输出负载很大时,本设计能提供足够的驱动电流,同时延迟时间短、并占用版图面积小。     

ANALYSIS AND DESIGN OF A NEURAL CHIP USED FOR BINARY IMAGE PROCESSING

Based on the model of a formal neuron proposed by McCulloch and Pitts,a kind ofneural circuit,which is a CMOS Variable Threshold Logic(VTL)circuit,is given in this paperconsidering the features of the binary image processing system.The theoretical analysis,andthe simulations for the building block circuits such as D/A converters,comparator and so on aregiven.The layout design of the whole circuit are also given.The binary image processing can berealized by using the VTL circuit combined with its external auxiliary circuits.     

Design of a Standard Floating-Point Chip

Some aspects of design of a VLSI floating-point chip, which provides the WE/spl registered/32100 microprocessor with math acceleration capabilities, are described. The chip is implemented in 1.75-/spl mu/m twin-tub CMOS II technology [2] and contains 140 000 transistors.