LaON钝化层改善HfTiO高k栅介质Ge MOS电容电特性（英文）

采用溅射法淀积一层LaON薄膜作为钝化层,制备了HfTiO栅介质Ge MOS电容,并对它们的电特性进行了仔细研究。HfTiO/LaON堆栈栅介质Ge MOS电容呈现出许多比HfTiO Ge MOS电容更好的电特性,如更低的界面态密度(4.5×10~(11)eV~(-1)/cm~2)、更小的栅极漏电流(1.08×10~(-5)A/cm~2 at V_(fb)+1 V)和更大的k值(24.8)。获得这些结果的机理在于LaON钝化层能有效阻止O、Ti、Hf和Ge的相互扩散,从而抑制HfGeTiO界面层的生长。HfTiO/LaON是高质量Ge MOS器件有前途的高k栅介质。     

HfTiO高κ栅介质Ge MOS电容特性研究

采用反应磁控共溅射方法在Ge衬底上制备亚-nm等效氧化物厚度(EOT)的HfTiO高κ栅介质薄膜,研究了湿N2和干N2气氛退火对GeMOS电容电特性的影响。隧穿电子显微镜、椭偏仪、X射线光电子频谱、原子力显微镜以及电特性的测量结果分别表明,与干N2退火比较,湿N2退火能明显抑制不稳定的低κGeOx界面层的生长,从而减小栅介质厚度,降低栅介质表面粗糙度,有效提高介电常数,改善界面质量和栅极漏电流特性,这都归因于GeOx的易水解性。还研究了Ti靶溅射功率对HfTiO栅介质GeMOS器件性能的影响。     

湿N_2退火HfTiO和HfO_2栅介质Ge MOS电特性研究

采用反应磁控溅射方法在Ge衬底上分别制备了HfTiO和HfO2高κ栅介质薄膜,并研究了湿N2和干N2退火对介质性能的影响。由于GeOx在水气氛中的水解特性,湿N2退火能分解淀积过程中生长的锗氧化物,降低界面态和氧化物电荷密度,有效提高栅介质质量。测量结果表明,湿N2退火Al/HfTiO/n-GeMOS和Al/HfO2/n-GeMOS电容的栅介质等效厚度分别为3.2nm和3.7nm,-1V栅偏压下的栅极漏电流分别为1.08×10-5A/cm2和7.79×10-6A/cm2。实验结果还表明,HfTiO样品由于Ti元素的引入提高了介电性能,但是Ti的扩散也使得界面态密度升高。     

退火气氛对Ge MOS电容电特性的影响

采用反应磁控溅射法在Ge衬底上制备了HfTiO高介电常数k栅介质薄膜,研究了不同气体(N2、NO、N2O)淀积后退火对Ge金属-氧化物-半导体(MOS)电容性能的影响.透射电子显微镜和电特性测量表明,湿N2退火能有效抑制界面层的生长,提高界面质量,改善栅极漏电流特性,从而得到最优的器件性能,即Al/HfTiO/n-Ge MOS电容的栅介质等效氧化物厚0.81 nm,k=34.5,带隙中央界面态密度为2.4×1011cm-2·eV-1,1 V栅偏压下的栅极漏电流为2.71×10-4A·cm-2.     

表面预处理对Ge MOS电容特性的影响

通过不同气体(NO、N2O、NH3)对Ge衬底进行表面预处理,生长GeOxNy界面层,然后采用反应磁控溅射方法生长HfTiO薄膜,制备HfTiO/GeOxNy叠层高k栅介质Ge MOS电容,研究表面预处理对界面层以及界面层对器件性能的影响.隧穿电子扫描电镜(TEM)、栅电容-电压(C-V)栅极漏电流-电压(J-V)的测量结果表明,湿NO表面预处理能生长高质量的界面层,降低界面态密度,抑制MOS电容的栅极漏电流密度.施加高场应力后,湿NO表面预处理样品的平带漂移及漏电流增加最小,表示器件的可靠性得到有效增强.     

超薄HfN界面层对HfO_2栅介质Ge pMOSFET电性能的改进

通过在高k介质和Ge表面引入一层超薄HfN界面层,实验制备了HfO2/HfON叠层栅介质Ge MOS器件。与没有界面层的样品相比,HfO2/HfON叠层栅介质MOSFET表现出低的界面态密度、低的栅极漏电和高有效迁移率。因此利用HfON作为Ge MOS器件的界面钝化层对于获得小的等效氧化物厚度和高的high-k/Ge界面质量有着重要的意义。     

HfTiO氮化退火对MOS器件电特性的影响

采用磁控溅射方法,在Si衬底上淀积HfTiO高k介质,研究了NO、N2O、NH3和N2不同气体退火对MOS电特性的影响。结果表明,由于NO氮化退火能形成类SiO2/Si界面特性的HfTiSiON层,所制备的MOS器件表现出优良的电特性,即低的界面态密度、低的栅极漏电和高的可靠性。根据MOS器件栅介质(HfTiON/HfTiSiON)物理厚度变化(ΔTox)和电容等效厚度变化(ΔCET)与介质(HfTiON)介电常数的关系,求出在NO气氛中进行淀积后退火处理的HfTiON的介电常数达到28。     

TaON界面层Hf基高κ栅介质Ge MOS电容特性研究

制备了含TaON界面层的Hf基氧化物和氮氧化物叠层高κ栅介质GeMOS电容。器件的测量结果表明,HfTaON/TaON叠层栅介质GeMOS电容表现出良好的界面特性、低的栅极漏电流密度、小的等效氧化物厚度(0.94nm)、高的介电常数(～24)和良好的可靠性。这些都归因于TaON界面层阻挡了O及金属原子向Ge衬底的扩散,抑制了不稳定的低κGeOx的生长,从而改善界面质量,增强器件性能。     

HfO_2/TaON叠层栅介质Ge pMOSFET制备及迁移率退化研究

为提高high-k/Ge界面质量,在high-k介质和Ge表面引入薄的TaON界面层。相对于没有界面层的样品,HfO2/TaON叠层栅介质Ge pMOSFET样品的空穴迁移率有显著提高,但仍小于理论预测值。利用high-k栅介质MOSFET中各种新的附加散射机制,分析了迁移率退化的原因,模型计算结果与实验结果一致。     

叠层高k栅介质中远程界面粗糙散射的理论模型

利用双子带近似,从理论上研究了远程界面粗糙散射对叠层高k栅介质MOSFET反型载流子迁移率的退化作用,模拟了叠层高k栅介质结构参数和材料参数对远程界面粗糙散射的影响。结果表明,对于精确的迁移率模型,远程界面粗糙散射必须加以考虑,另外,在设计叠层高k栅介质MOSFET时,在EOT得到满足的条件下,尽可能利用具有较高介电常数的界面层和具有较低介电常数的高k栅介质,可以减小迁移率退化。     

Effects of Ti content and wet-N2 anneal on Ge MOS capacitors with HfTiO gate dielectric

Thin HfTiO gate dielectric is deposited by reactive co-sputtering method followed by wet or dry N₂ anneal. The effects of Ti content on the performance of HfTiO gate dielectric are investigated by using different sputtering powers for the Ti target. Experimental results indicate that as the Ti content increases, the dielectric constant (κ) can increase up to 40 for a Ti content of 28%. However, when the Ti content is too high, the interface properties and gate leakage properties are deteriorated. On the contrary, results show that owing to the hydrolyzable property of GeO_x, the wet-N₂ anneal can greatly suppress the growth of unstable low-κ GeO_x interlayer, resulting in lower interface-state density and gate leakage current, in addition to larger κ value. In this study, when the sputtering power of the Ti target is 80 W together with a 25-W power for the Hf target and a post-deposition anneal (PDA) in wet-N₂ ambient at 500 °C for 300 s, excellent device performance is achieved: equivalent oxide thickness of 0.72 nm, equivalent dielectric constant of 39, interface-state density of 6.5 × 10¹¹ eV⁻¹ cm⁻² and gate leakage current of 5.7 × 10⁻⁴ A/cm² at V_g = 1 V. Therefore, in order to obtain high-quality HfTiO gate dielectric for small-scaled Ge MOS devices, not only should the Ti content be optimized, the PDA should also be done in a wet-N₂ ambient.     

Au/Ge/Pd ohmic contacts to n-GaAs with the Mo/Ti diffusion barrier

The influences of the As-outdiffusion and Au-indiffusion on the performances of the Au/Ge/Pd/n-GaAs ohmic metallization systems are clarified by investigating three different types of barrier metal structures Au/Ge/Pd/GaAs, Au/Ti/Ge/Pd/ GaAs, and Au/Mo/Ti/Ge/Pd/GaAs. The results indicate that As-outdiffusion leads to higher specific contact resistivity, whereas Au-indiffusion contributes to the turnaround of the contact resistivity at even higher annealing temperature. For Au/Mo/Ti/Ge/Pd/n-GaAs samples, they exhibit the smoothest surface and the lowest specific contact resistivity with the widest available annealing temperature range. Moreover, Auger electron spectroscopy depth profiles show that the existing Ti oxide for the Mo/Ti bilayer can very effectively retard Au-indiffusion, reflecting the onset of the turnaround point at much higher annealing temperature.     

Solid phase reaction of Ti with Si−Ge layers prepared by Ge-implantation

Titanium germanosilicide films from thin Ti films (∼27.5 nm) are formed by solid phase reaction of Ti/Si_0.62Ge_0.38 bilayer at different annealing temperatures ranging from 600°C to 800°C. The effect of crystallographic state of Si−Ge alloy film on the reaction, phase formations, and polymorphic phase transformations, stability of germanosilicides have been investigated by x-ray diffraction, atomic force microscope, and sheet resistance measurements. Both amorphous and relaxed epitaxial Si_0.62Ge_0.38 films are prepared by Ge-multiple implantations into Si wafers with appropriate dose and energy followed by different post-implantation RTA schemes comprising alternative implantation and annealing in on case, and single final annealing in another one. XRD results indicate that the reaction sequence in both cases is found to be Ti/Si like with the formation of C49-Ti(Si−Ge)₂ as a precursor to the low resistivity C54-Ti(Si−Ge)₂. The films formed on amorphous alloy layer exhibit lower polymorphic transition temperature (∼750°C), smoother surface, lower sheet resistance and less agglomeration as compared to those on c:Si−Ge films. These characteristics are due to enhanced nucleation of C54 phase as a result of greater number of nucleation sites in the reaction with amorphous films. The formation of Ti(Si−Ge)₂ films is, however, accompanied by the decrease of Ge content in Ti(Si−Ge)₂ films formed on both amorphous and crystalline alloy films and indicates possible segregation/diffusion effects during the germanosilicidation.     

钛掺杂对Ge2Sb2Te5薄膜相变特性的改善

利用椭偏光谱术与XRD对钛掺杂Ge2Sb2Te5薄膜中钛元素对体系的光学性质及其微结构的影响进行了实验研究。进而对该薄膜进行的变温阻抗实验表明,钛掺杂Ge2Sb2Te5薄膜与未掺杂的薄膜相比具有更好的热稳定性。基于对薄膜样品的数据保持能力测试的实验数据,经阿伦纽斯外推处理可知,钛掺杂Ge2Sb2Te5薄膜样品的10年数据保持温度要高于未掺杂Ge2Sb2Te5薄膜样品。本文的实验结果均证实,钛掺杂Ge2Sb2Te5薄膜更适合应用于相变随机存取存储器中。     

Influence of annealing on the metal/semiconductor contacts deposited on sulfur-treated <Emphasis Type="Italic">n</Emphasis>-GaAs surface

Comparative analysis of the influence of thermal annealing on Ge/Au/Ni-, Ge/Au/Ti/Au-, and Ge/Au/Ni/Ti/Au-based ohmic contacts and Ti/Au-based Schottky contacts deposited on an n-GaAs (100) surface treated and nontreated in (NH₄)₂S aqueous solution have been performed. Annealing conditions for ohmic contacts are found that lead to a decrease in the specific contact resistance of sulfur-treated samples by a factor of 2.5–15 in comparison with the nontreated samples. Optimal annealing conditions are also determined for sulfur-treated GaAs samples with Schottky contacts, which make it possible to reduce the ideality factor and increase the barrier height and the breakdown voltage with respect to the nontreated samples.     

High-κ Al2O3−HfTiO Nanolaminates With Less Than 0.8-nm Equivalent Oxide Thickness

High quality nanolaminate stacks consisting of five Al₂O₃-HfTiO layers with an effective dielectric constant of about 22.5 are reported. A dielectric constant for binary HfTiO thick films of about 83 was also demonstrated. The electrical characteristics of as-deposited structures and ones which were annealed in an O₂ atmosphere at up to 950 degC for 5-10 min were investigated. Two types of gate electrodes: Pt and Ti were compared. The dielectric stack which was annealed up to 500 degC exhibits a leakage current density as small as ~1times10^-4 A/cm² at an electric of field 1.5 MV/cm for a quantum-mechanical corrected equivalent oxide thickness of ~0.76 nm. These values change to ~1times10^-8 A/cm² and 1.82 nm, respectively, after annealing at 950 degC     

Extremely low-resistance nonalloyed ohmic contacts on molecular beam epitaxially grown p-type Ge

Extremely low-resistance nonalloyed ohmic contacts have been formed on p-type Ge grown on GaAs by molecular beam epitaxy as part of a research effort into GaAs/Ge heterojunction devices. Using evaporated Ti/Al metallisation, specific contact resistances well below 1*10/sup -8/ Omega cm/sup 2/ were achieved for heavily doped Ge (p>1*10/sup 19/ cm/sup -3/). The investigated Ge layers were grown as the base region of AlGaAs/Ge/GaAs HBTs. The influence of the low base resistance on the high-frequency performance of HBTs was studied by simulations.<>