Free charge transfer in charge-coupled devices

The free charge-transfer characteristics of charge-coupled devices (CCD's) are analyzed in terms of the charge motion due to thermal diffusion, self-induced drift, and fringing field drift. The charge-coupled structures considered have separations between the gates equal to the thickness of the channel oxide. The effect of each of the above mechanisms on charge transfer is first considered separately, and a new method is presented for the calculation of the self-induced field. Then the results of a computer simulation of the charge-transfer process that simultaneously considers all three charge-motion mechanisms is presented for three-phase CCD's with gate lengths of 4 and 10 µ. The analysis shows that while the majority of the charge is transferred by means of the self-induced drift that follows a hyperbolic time dependence, the last few percent of the charge decays exponentially under the influence of the fringing field drift or thermal diffusion, depending on the design of the structure. The analysis shows that in CCD's made on relatively high resistivity substrates, the transfer by fringing-field drift can be very fast, such that transfer efficiencies of 99.99 percent are expected at 5- to 10- MHz bit rates for 10-µ gate lengths and at up to 100 MHz for 4-µ gate lengths.     

Charge transfer in overlapping gate charge-coupled devices

A detailed numerical simulation of the free charge transfer in overlapped gate charge-coupled devices is presented. The transport are analyzed in terms of thermal diffusion, self-induced fields, and fringing fields under all the relevant electrodes and interelectrode regions with time-varying gate potentials. The results of the charge transfer with different clocking schemes and clocking waveforms are presented. The dependence of the stages of the charge transfer on the device parameters are discussed in detail. A lumped-circuit model of CCD that could be used to obtain the charge-transfer characteristics with various clocking waveforms is also presented.     

Short-channel effects on the input stage of surface-channel CCD's

A detailed study of transient signal charge injection into surface-channel charge-coupled devices using a two-dimensional computer model including the source diffusion and the self-induced and fringing field effects has been carried out. The total delay time required to inject a packet of charge into CCD's for a range of device structures was determined. It is found that the maximum clock pulse frequency of operation is determined by the input delay time and not by the speed of charge transfer which is normally assumed. The results of this study are compared with results obtained using a one-dimensional simulation model for charge injection into CCD's. Experimental justification of the one-dimensional model is provided. With the aid of this analysis a design expression for the intrinsic input delay (the delay associated with the fill portion) for short gate surface-channel CCD's is derived and presented in this paper. It is also shown that for short gate devices (L < 8µm) the input delay time due to scooping is about two to four times the intrinsic delay.     

Charge transfer in charge-coupled devices in the presence of interface states

The transfer of charge from under a gate of a three-phase surface-channel charge-coupled device is analysed in terms of thermal diffusion, charge-gradient induced drift, fringing field drift, and interface state trapping. A method based on a piecewise approximation for the emission rate from interface states is proposed and used to derive the single-transfer characteristics in the presence of interface traps. It is shown that the emission rate exhibits a marked spatial dependence, which is a function of both fringing field profile and interface state density. It is also concluded that trapping effects are a strong limitation on the transfer efficiencies attainable in surface-channel charge-coupled devices at low and moderate frequencies.     

Numerical methods for the charge transfer analysis of charge-coupled devices

Charge transfer phenomenon in charge-coupled devices is characterized by a nonlinear partial differential equation of the parabolic type, usually coupled with a very undesirable nonlinear boundary condition. In this study, special treatment is made to the boundaries such that the nonlinearity of the boundary condition does not appear in the final calculation. Four possible finite-difference schemes for this problem are described and results compared. Through numerical experimentations, the linearized Crank-Nicolson scheme is proved to exhibit superior quality and is recommended for the exclusive use in studying the charge transfer phenomenon in CCD. Using this scheme, the charge transfer phenomenon of a two phase overlapping gate CCD has been studied and numerical results are presented. Special emphasis is directed toward the relative importance of the self-induced drift, fringing field drift and thermal diffusion currents. Also, the usefulness of approximating a spatial fringing field pattern by a constant value to the charge transfer phenomenon is discussed.     

Simulation and Design of AlGaAs/InGaAs CCDs Based on pHEMT Technology

This paper describes the modeling, design, and fabrication of quarter-micrometer double delta-doped AlGaAs/InGaAs charge-coupled devices (CCDs) whose epitaxial layers and geometry were based around the device structure of commercial pHEMTs. A quasi-2-D physical model has been developed to investigate the properties of this novel 2-D electron gas CCD. This physical model allows the characteristics of the InGaAs transport channel as well as the dc characteristics of the device to be predicted within a reasonable amount of time. This model also shows how "individual" charge packets can be controllably transferred through the device when appropriate clocking voltages are applied to the gates of the CCD. This capacitive gate structure device is then shown to be successfully fabricated using established GaAs heterostructure fabrication techniques to ensure good repeatability. The dc characteristics of the fabricated CCD delay line are included.     

Final stage of the charge-transfer process in charge-coupled devices

The final stages of transfer of charge from under a storage gate is formulated analytically including both fringing-field induced drift and diffusion. Analytic solutions to these equations are presented for constant fringing fields, and a system of equations for spatially varying fields is developed. Approximate solutions for spatially varying fringing fields, when combined with a lumped-parameter model of the self-induced field effects, are shown to give a reasonably accurate representation of the free-charge transfer process.     

Drift-aiding fringing fields in charge-coupled devices

Transverse electric fields at the Si-SiO/SUB 2/ interface (fringing fields) can aid transfer of charge from one potential well to another in charge- coupled devices (CCD). The magnitudes of these drift-aiding fringing fields are evaluated by an approximate analysis and also by computer. The analytical approach assumes zero space charge in the silicon and agrees with the computer solutions in that limit. When the depletion width becomes less than the gate width the fringing field is reduced considerably. Transit times associated with these fringing fields are evaluated. Trapping of charge in interface states rather than transfer of free charge is expected to be the fundamental limitation on speed and transfer efficiency in appropriately designed CCDs.     

Charge-control method of charge-coupled device transfer analysis

An analysis of charge transfer based on the "charge-control" approach has been made for charge-coupled devices (CCD's). A general closed-form equation for the charge transfer efficiency has been obtained that includes the major mechanisms of 1) charge-gradient induced drift, 2) thermal diffusion, 3) an external fringing field, and 4) charge loss due to traps or recombination. When the charge loss and fringing field terms are neglected, the results are in close agreement with the numerical solutions by Strain and Schryer. With the fringing field term included, the closed-form solution compares well with the numerical results by Heller, Chang, and Lo. The effect of charge loss on the transfer efficiency is studied and the temperature dependence of the efficiency, including the temperature dependent surface mobility, is discussed. The effect of a "fat" zero on the diminution of a digital one is discussed with and without charge loss to surface states. It is believed that the charge-control approach not only simplifies the mathematics involved, but also provides practical charge-coupled device and circuit design guides.     

Computer analysis of surface-charge transport between transfer electrodes in a charge-coupled device

A computer program has been developed that simulates two-dimensional dynamics of electrons and holes in a p-channel charge-coupled device. By using this program we have investigated the effects of two-dimensional device structure on surface-charge transfer, particularly a potential-barrier and fringing field. We have obtained the following results: 1) in case of a p-channel CCD negative charges on the SiO2film at a gap reduce the potential-barrier between transfer electrodes. This effect aids transfer of surface-charge in a CCD with wide gaps. 2) In transfer operation of a CCD with wide gaps, the signal charge must be less than a particular value so that a potential-barrier does not emerge. The particular value depends upon the device parameters and the transfer pulses. 3) The fringing field created by the adjacent electrode enhances the speed of surface-charge transfer. This effect increases with decreasing the transfer-electrode length and the signal charge level. 4) The computer results indicate that 100 percent transfer efficiency is obtained from the strong fringing field after the transfer time is equal to the transit time if no surface states exist.     

The influence of interface states on incomplete charge transfer in overlapping gate charge-coupled devices

A simple and accurate model is used to estimate the incomplete charge transfer due to interface states trapping in the overlapping gate charge-coupled devices. It is concluded that trapping in the interface states under the edges of the gates parallel to the active channel limits the performance of the devices at moderate and low frequencies. The influence of the device parameters, dimensions, and clocking waveforms on the signal degradation is discussed. It is shown that increasing the clock voltages, reduces the incomplete charge transfer due to interface state trapping.     

Design and optimization of BCCD in CMOS technology

This paper optimizes the buried channel charge-coupled device (BCCD) structure fabricated by complementary metal oxide semiconductor (CMOS) technology. The optimized BCCD has advantages of low noise, high integration and high image quality. The charge transfer process shows that interface traps, weak fringing fields and potential well between adjacent gates all cause the decrease of charge transfer efficiency (CTE). CTE and well capacity are simulated with different operating voltages and gap sizes. CTE can achieve 99.999% and the well capacity reaches up to 25 000 electrons for the gap size of 130 nm and the maximum operating voltage of 3 V.     

Proton-bombardment isolated GaAlAs/GaAs charge-coupled devices

Proton bombardment is used for the first time as a channel isolation technique to fabricate buried channel homojunction charge-coupled devices (c.c.d.s) of n-GaAs channel on GaAs substrate and heterojunction c.c.d.s of n-Ga1?xAlxAs on GaAs. The c.c.d. structure is a Schottky-barrier gate buried channel 3-phase device with 30 transfer gates. The channel-stop bombardment was carried out at room temperature with an energy of 200 keV and a total dose of 1015/cm2. The c.c.d.s were tested with electrical charge injection and direct readout. The charge transfer efficiency was found to be greater than 0.999 per transfer for both GaAs and GaAlAs. The proton-bombardment isolated devices were compared with similar devices using mesa isolation and were found to perform similarly.     

Frequency response of charge transfer in MOS inversion layers

The dynamics of charge transfer from a reservoir into an MOS inversion layer, which limits the frequency response of an MOS transistor or a charge-coupled device, is investigated. Using Berman and Kerr's model of space-charge capacitance in the semiconductor, a small-signal distributed model is developed for an MOS structure which transfers charge in an inversion channel due to a variation in the gate voltage. The dynamics of the charge transfer is characterized by a time constant which is determined by the length of the inversion channel and its mobility. Experimental data of gate capacitance vs frequency, taken from a test structure with a diffused source/drain well, are satisfactorily fitted by theoretical curves derived from the model. The channel mobility is precisely determined from the adjusted time constant. The influence of interface states on the capacitance-frequency relationship is also briefly discussed.     

A two-phase GaAs cermet gate charge-coupled device

The design, fabrication, and operation of a 64-pixel, two-phase GaAs cermet gate charge-coupled device (CMCCD) is described. A castellated channel geometry provides the built-in electric field for directing the flow of signal charge within the CMCCD channel. A two-dimensional computer model for the electrostatic potential within a single pixel of the CMCCD is used to verify the presence of the built-in electric field and is used to show the possibility of the existence of energy troughs under the cermet gates. Energy troughs within the CMCCD are undesirable, as they increase the dispersion of signal charge through the device. It is shown that the energy troughs are overcome by increasing the clock voltage amplitude. A 64-pixel, two-phase CMCCD demonstrated a charge-transfer efficiency of 0.996 when operated at 46 MHz     

A simple analysis of CCDs driven by pn junctions

It is shown that charge-coupled devices driven by pn junctions, instead of MOS capacitors, can be conveniently described as consisting of two pn diodes put back to back. The dependance of the quantity of transportable charge on doping levels and gate-voltages is derived. The absolute maximum of transportable charge is calculated as the dielectric constant times the maximum electrical field. For real devices in silicon, a charge handling capability of about 1 × 10¹⁶ electrons/m² is derived for a 10 V clock-swing. The presence of bare gaps between gates, making it difficult to obtain a sufficiently smooth channel potential, is the most serious drawback of these devices. The possibility to inject or extract charge at the upside in these devices, their high sensitivity to light, the anti-blooming properties of line sensors and the reduced influence of the semiconductor-insulator interface are attractive features of the steering of CCDs with pn diodes.     

A 9-b charge-to-digital converter for integrated image sensors

Charge-to-digital conversion offers advantages over conventional charge readout techniques because it performs digitization directly in the charge domain. The approach consolidates hardware, reduces power and weight, and eliminates many sources of noise and nonlinearity. This paper introduces an architecture for a charge-to-digital converter (CDC) that is tailored toward a charge-coupled device (CCD) implementation. New methods of generating charge, sensing charge, and comparing charge packets are described that improve conversion accuracy. Factors limiting device performance are discussed. Measured results are presented for two prototype CDCs. The first, using buried channel CCDs, is optimized for resolution. It achieves 56 dB spurious free dynamic range (SFDR) at a 2 MHz sampling rate and operates from 5 V. The second, using surface channel CCDs, is optimized for power and speed. It achieves 49 dB SFDR at a 15 MHz sampling rate and consumes 13 mW power at its maximum sampling rate of 22 MHz     

Linearity of potential equilibration method of injecting charge into CCD's

The linearity of injecting charge into charge-coupled devices (CCD's) by potential equilibration method has been studied. Experimental results obtained agree Well with the theoretically derived expression for the input characteristic. If the two input gates have identical structures, i.e., the same oxide thicknesses and substrate dopings, input linearity is obtained irregardless to which gate the signal is applied. On the other hand, if the two gates are different, the signal should always be applied to the second gate in order to obtain a linear input function.     

Correlation between most 1/f noise and CCD transfer inefficiency

The 1/f noise in MOS transistors has been investigated and is shown to correlate with charge transfer inefficiency experiments on surface-channel CCDs. Both independent phenomena can be quantitatively explained by the same interface state model. The oxide trap density turns out to vary by more than a factor 10. The 1/f noise is compared with McWhorter's number fluctuation model and with the mobility fluctuation model. The oxide trap density is calculated from the charge transfer inefficiency in surface CCDs. Both the quantitative agreement between oxide trap density and 1/f noise and the observed dependence of 1/f noise on gate voltage here give strong arguments in favour of the McWhorter model. The investigated MOS transistors fall into a category that cannot be explained by the present mobility fluctuation model.     

Development and Testing of a 2-D Transfer CCD

This paper describes the development, operation, and characterization of charge-coupled devices (CCDs) that feature an electrode structure that allows the transfer of charge both horizontally and vertically through the image area. Such devices have been termed two-dimensional (2-D) transfer CCDs (2DT CCDs), as opposed to the conventional devices, which might be called one-dimensional transfer CCDs, but in other respects are the same as conventional CCD devices. Batches of two different 2DT CCD test devices, featuring different electrode structures but with identical clocking operation in each case, were produced and tested. The methodology of 2-D charge transfer in each of the device types is described, followed by a presentation of test results from the new CCDs. The ability of both 2DT CCD transfer electrode schemes to successfully transfer charge in both horizontal and vertical directions in the image section of the devices has been proven, opening up potential new applications for 2DT CCD use