共查询到20条相似文献,搜索用时 31 毫秒
1.
The device consists primarily of several molecular-beam-epitaxy (MBE-) grown GaAs/(AlGa)As resonant tunneling diodes connected in parallel. This device exhibits multiple peaks in the I -V characteristic. When a load resistor is connected, the circuit can be operated in a multiple stable mode. With this concept, implementation of three-state and four-state memory cells are made. In the three-state case the operating points at voltages V 0=0.27 V , V 1=0.42 V, and V 2=0.53 V represent the logic levels 0, 1, and 2. Similarly for the four-state memory cell the logic levels voltages are V 0=0.35 V, V 1=0.42 V, V 2=0.54 V, and V 3=0.59 V. A suggestion of an integrated device structure using this concept is also presented 相似文献
2.
Hot-carrier stressing carried out as a function of substrate voltage on 2-μm NMOS devices under bias conditions V d =8 V and V g=5.5 V is discussed. The time power-law dependence of stressing changes as a function of substrate bias (V b), having a power-law gradient of 0.5 for V b=0 V and 0.3 for V b=-9 V. Investigation of the type of damage resulting from stressing shows that at V b=0 V, interface state generation results, while at V b=-9 V, the damage is mostly by charge trapping. Measurements of the gate current under these two substrate bias conditions show that the gate electron current increases by over two orders of magnitude upon application of a strong back bias. It is suggested that the electron trapping arises from this enhanced gate electron current under large substrate voltage conditions 相似文献
3.
The circuit performance of CMOS technologies with silicon dioxide (SiO2) and reoxidized nitrided oxide (RONO) gate dielectrics over the normal regime of digital circuit operation, i.e. V GS⩽5 V and B DS⩽5 V, is discussed. The simulation of a simple CMOS inverter has shown that the SiO2 inverter consistently outperforms the RONO inverter over temperatures ranging from 300 to 100 K. This can be attributed mainly to the significantly lower μp (hole mobility) of RONO p-channel devices. At 300 K, μp(RONO) is 14-8% smaller than μp(SiO2) over the entire range of gate biases, while μn(RONO) (electron mobility of n-channel RONO devices) is also smaller than μn(SiO2) and reaches only 96% of μn(SiO2) at V GS=5 V. At 100 K, μn(RONO)/μn (SiO2) at V GS=5 V is increased to 1.10, however, μp(RONO)/μp(SiO2) at V GS=5 V is degraded to 0.59. The dependence of circuit performance on the supply voltage has also been evaluated for the RONO and SiO2 inverters 相似文献
4.
Peransin J.-M. Vignaud P. Rigaud D. Vandamme L.K.J. 《Electron Devices, IEEE Transactions on》1990,37(10):2250-2253
The 1/f noise in normally-on MODFETs biased at low drain voltages is investigated. The experimentally observed relative noise in the drain current S I/I 2 versus the effective gate voltage V G=V GS-V off shows three regions which are explained. The observed dependencies are S I/I 2∝V G m with the exponents m =-1, -3, 0 with increasing values of V G. The model explains m =-1 as the region where the resistance and the 1/f noise stem from the 2-D electron gas under the gate electrode; the region with m =0 at large V G or V GS≅0 is due to the dominant contribution of the series resistance. In the region at intermediate V G , m =-3, the 1/f noise stems from the channel under the gate electrode, and the drain-source resistance is already dominated by the series resistance 相似文献
5.
Stress effects on poly-Si PMOS devices are investigated, and stress is related to the improvement or degradation of PMOS on/off current ratio. P-channel polysilicon MOSFETs have been stressed in the saturation and off-state regimes. Both the drive (on) current and leakage (off) current can be either increased or decreased after particular bias stress. On/off current ratio can be decreased by a factor of 2 for a stress bias of V GS=V DS=-11 V, but can be increased by a factor of 50 for a stress bias of V GS=-2 V, V DS=-11 V. Two effects of bias stress have been identified in poly-Si PMOS devices for which the on/off current ratio can either be increased or decreased after stress bias depending on the value of stress bias V GS. These effects of room-temperature stress are proposed to be due to either trapping of hot electrons or hot-hole-induced donor-type interface state generation 相似文献
6.
Hot-carrier stressing was carried out on 1-μm n-type MOSFETs at 77 K with fixed drain voltage V d=5.5 V and gate voltage V g varying from 1.5 to 6.5 V. It was found that the maximum transconductance degradation ΔG m and threshold voltage shift ΔV t, do not occur at the same V g. As well, ΔK t is very small for the V g <V d stress regime, becomes significant at V g≈V d, and then increases rapidly with increasing V g, whereas ΔG m has its maximum maximum in the region of maximum substrate current. The behavior is explained by the localized nature of induced defects, which is also responsible for a distortion of the transconductance curves and even a slight temporary increase in the transconductance during stress 相似文献
7.
Scherrer D. Kruse J. Laskar J. Feng M. Wada M. Takano C. Kasahara J. 《Electron Device Letters, IEEE》1993,14(9):428-430
The low-power microwave performance of an enhancement-mode ion-implanted GaAs JFET is reported. A 0.5-μm×100-μm E-JFET with a threshold voltage of V th=0.3 V achieved a maximum DC transconductance of g m=489 mS/mm at V ds=1.5 V and I ds=18 mA. Operating at 0.5 mW of power with V ds=0.5 V and I ds =1 mA, the best device on a 3-in wafer achieved a noise figure of 0.8 dB with an associated gain of 9.6 dB measured at 4 GHz. Across a 3-in wafer the average noise figure was F min=1.2 dB and the average associated gain was G a=9.8 dB for 15 devices measured. These results demonstrate that the E-JFET is an excellent choice for low-power personal communication applications 相似文献
8.
Self-aligned high-frequency InP/InGaAs double heterojunction bipolar transistors (DHBTs) have been fabricated on a Si substrate. A current gain of 40 was obtained for a DHBT with an emitter dimension of 1.6 μm×19 μm. The S parameters were measured for various bias points. In the case of I C=15 mA, f T was 59 GHz at V CE=1.8 V, and f max was 69 GHz at V CE=2.3 V. Due to the InP collector, breakdown voltage was so high that a V CE of 3.8 V was applied for I C=7.5 mA in the S -parameter measurements to give an f T of 39 GHz and an f max of 52 GHz 相似文献
9.
A report is presented on an InAs channel field-effect transistor (FET) based on AlGaSb/InAs/AlSb/AlGaSb structures grown by molecular-beam epitaxy. Excellent pinch-off characteristics have been obtained. An FET with a gate length of 1.7 μm showed transconductances ranging from 460 mS/mm (at V ds=0.5 V) to 509 mS/mm (at V ds=1 V) and a K factor of 1450 mS/Vmm (at V ds=1 V) at room temperature 相似文献
10.
Low-voltage silicon trench power MOSFETs with forward conductivities approaching the silicon limit are reported. Vertical trench power MOSFETs with the measured performances of V DB =55 V (R sp=0.2 mΩ-cm2, k D=5.7 Ω-pF) and V DB=35 V (R sp=0.15 mΩ-cm2, k D =4.3 Ω-PF) were developed where V DB is the drain-source avalanche breakdown voltage, R sp is the specific on-state resistance, and k D=R spC sp is the input device technology factor where C sp is the specific MOS gate input capacitance. The optimum device performance resulted from an advanced trench processing technology that included (1) an improved RIE process to define scaled vertical silicon trenches, (2) silicon trench sidewall cleaning to reduce the surface damage, and (3) a novel polysilicon gate planarization technique using a sequential oxidation/oxide etchback, process. The measured performances are shown to be in excellent agreement with the two-dimensional device simulations and the calculated results obtained from an analytical model 相似文献
11.
The characteristics of polycrystalline silicon thin-film transistors (poly-Si TFTs) with a field-induction-drain (FID) structure using an inversion layer as a drain are investigated. The FID structure not only reduces the anomalous leakage current, but also maintains a high on current. An off current of 1.5 pA/μm and an on/off current ratio of 107 (V d=10, V g =-20 V) are successfully obtained. These characteristics result from good junction characteristics between the p channel and n+ inversion layer. Reducing the threshold voltage of the FID region allows a simple circuit configuration for the FID TFTs 相似文献
12.
Laskar J. Ketterson A.A. Baillargeon J.N. Brock T. Adesida I. Cheng K.Y. Kolodzey J. 《Electron Device Letters, IEEE》1989,10(12):528-530
The observation of negative differential resistance (NDR) and negative transconductance at high drain and gate fields in depletion-mode AlGaAs/InGaAs/GaAs MODFETs with gate lengths L g ~0.25 μm is discussed. It is shown that under high bias voltage conditions, V ds>2.5 V and V gs>0 V, the device drain current characteristic switches from a high current state to a low current state, resulting in reflection gain in the drain circuit of the MODFET. The decrease in the drain current of the device corresponds to a sudden increase in the gate current. It is shown that the device can be operated in two regions: (1) standard MODFET operation for V gs<0 V resulting in f max values of >120 GHz, and (2) a NDR region which yields operation as a reflection gain amplifier for V gs >0 V and V ds>2.5 V, resulting in 2 dB of reflection gain at 26.5 GHz. The NDR is attributed to the redistribution of charge and voltage in the channel caused by electrons crossing the heterobarrier under high-field conditions. The NDR gain regime, which is controllable by gate and drain voltages, is a new operating mode for MODFETs under high bias conditions 相似文献
13.
《Electron Devices, IEEE Transactions on》1990,37(1):153-158
The fabrication of a silicon heterojunction microwave bipolar transistor with an n+ a-Si:H emitter is discussed, and experimental results are given. The device provides a base sheet resistance of 2 kΩ/□ a base width 0.1 μm, a maximum current gain of 21 (V CE=6 V, I c=15 mA), and an emitter Gummel number G E of about 1.4×1014 Scm-4. From the measured S parameters, a cutoff frequency f t of 5.5 GHz and maximum oscillating frequency f max of 7.5 GHz at V CE=10 V, I c=10 mA are obtained 相似文献
14.
N-channel MOSFETs with different gate dielectrics, such as silicon dioxide, silicon dioxide annealed in nitrous oxide (NO), and reoxidized nitrided oxide (ONO), were first hot-carrier (HC) stressed and then irradiated to a total dose of 1.5 Mrd. For equal substrate current stressing NO devices have the least degradation, whereas the threshold voltage (V t) shift due to irradiation is maximum for these devices. For all three types of gate dielectrics the V t shift due to irradiation of HC stressed devices was higher than that of the unstressed device. However, for ONO devices the V t shift due to irradiation of the hot-electron stressed (stressing with V d=V g=6.5 V) device was less than that of the unstressed device 相似文献
15.
An experimental technique for accurately determining both the inversion charge and the channel mobility μ of a MOSFET is presented. With this new technique, the inversion charge is measured as a function of the gate and drain voltages. This improvement allows the channel mobility to be extracted independent of drain voltage V DS over a wide range of voltages (V DS=20-100 mV). The resulting μ(V GS) curves for different V DS show no drastic mobility roll-off at V GS near V TH. This suggests that the roll-off seen in the mobility data extracted using the split C - V method is probably due to inaccurate inversion charge measurements instead of Coulombic scattering 相似文献
16.
Takashima D. Watanabe S. Fuse T. Sunouchi K. Hara T. 《Solid-State Circuits, IEEE Journal of》1993,28(4):504-509
In order to achieve 3.3-V 1-Gb DRAM and beyond, a new on-chip supply voltage conversion scheme that converts 3.3-V external supply voltage, V ext, to lowered 1.5-V internal supply voltage, V ent, without any power loss within the voltage converter is proposed. This scheme connects two identical DRAM circuits in series between V ixt and V ss. By operation of two DRAM circuits with the same clock timing, the voltage between two DRAMs, V int, is automatically fixed to 1/2V ext. Therefore, each upper and lower DRAM circuit can operate at lowered 1/2V ext without use of the conventional voltage converter. This scheme was successfully verified by an experimental system using 4-Mb DRAMs. Utilizing the proposed scheme, power dissipation was reduced by as much as 50% and stable operation was achieved without access speed penalty 相似文献
17.
Magneto-transport and cyclotron resonance measurements were made to determine directly the density, mobility, and the effective mass of the charge carriers in a high-performance 0.15-μm gate In0.52 Al0.48As/In0.53Ga0.47As high-electron-mobility transistor (HEMT) at low temperatures. At the gate voltage V G=0 V, the carrier density n g under the gate is 9×1011 cm-2, while outside of the gate region n g=2.1×1012 cm-2. The mobility under the gate at 4.2 K is as low as 400 cm2/V-s when V G<0.1 V and rapidly approaches 11000 cm2/V-s when V G>0.1 V. The existence of this high mobility threshold is crucial to the operation of the device and sets its high-performance region in V G>0.1 V 相似文献
18.
Electrical and reliability characteristics of diagonally shaped n-channel MOSFETs have been extensively investigated. Compared with the conventional device structure, diagonal MOSFETs show longer device lifetime under peak I sub condition (V g =0.5 V d). However, in the high-gate-bias region (V g=V d), diagonal MOSFETs exhibit a significantly higher degradation rate. From the I sub versus gate voltage characteristics, this larger degradation rate under high gate bias is concluded to be due mainly to the current-crowding effect at the drain corner. For a cell-transistor operating condition (V g>V d), this current-crowding effect in the diagonal transistor can be a serious reliability concern 相似文献
19.
The results of measurements of the digital characteristics of CMOS devices as a function of temperature between 77 and 300 K and of supply voltage between 3 and 20 V are presented. Using a fixed supply of 5 V, the low noise margin decreased from 2.54 to 2.11 V, but the high noise margin increased from 2.18 to 2.40 V as the temperature was increased from 77 to 300 K. On lowering the temperature from 300 to 77 K, both V II and V IH increased and the transition between these input logic voltages became more abrupt. These and other digital characteristics including noise immunity. V H-V I, and V IH-V II all showed a smooth monotonic improvement as the temperature decreased. These results can be qualitatively explained due to the increase in the absolute threshold voltages of the NMOS and PMOS transistors and to the decrease in the βN/βP ratio as the temperature is lowered 相似文献
20.
Cong H.-I. Andrews J.M. Boulin D.M. Fang S.-C. Hillenius S.J. Michejda J.A. 《Solid-State Circuits, IEEE Journal of》1988,23(5):1189-1194
A low-power CMOS dual-modulus (divide-by-128/129) prescaler IC is described. The IC has been fabricated with symmetric CMOS technology that optimizes simultaneously the characteristics of both the p-channel and n-channel transistors for low-power-supply-voltage operation. Two different gate oxide thicknesses of 175 and 100 Å have been used. The best prescalar fabricated with 175-Å gate oxide functions at 2.06 GHz with 25-m W power consumption (L eff=0.5 μm; V dd=3.5 V). Preliminary results for prescalars fabricated with 100-Å gate oxide show that 4.2-GHz operation is possible (L eff=0.4 μm; V dd=3.5 V). Power-supply voltage as low as 1.7 V can be used for the prescalar to function at 1 GHz with a power consumption of only 4 mW 相似文献