MOSFET degradation due to stressing of thin oxide

Oxide and interface traps in 100 Å SiO2created by Fowler-Nordheim tunneling current have been investigated using capacitor C-V, I-V, and transistor I-V measurements. The net oxide trapped charge is initially positive due to hole trapping near the anode interface and, at sufficiently high fluence, it becomes negative due to the trapping of electrons with a centroid of 60 Å from the injector (cathode) interface. Interface traps (Surface states) are created by tunneling electrons flowing to and from the substrate. The interface-trap energy distribution gives a distinct peak at 0.65 eV above the valence band edge. The positive charge trapping and interface traps generation saturate at high electron fluence, but not the electron trap generation. The generation rates for electron traps and interface traps are weak functions of tunneling current density over the range tested. The interface traps cause degradations in subthreshold current slope and surface electron mobility. The threshold-voltage shift can be either positive or negative under the combined influence of the oxide charges and the interface charges.     

Electrical characteristics of very thin SiO2deposited at low substrate temperatures

Very thin (≲ 100-Å) films of SiO2have been deposited by a modified plasma-enhanced chemical-vapor deposition (PECVD) process at very low substrate temperatures (≲ 350°C). Low flow rates of reactive gases and a high flow of inert carrier gas were used to lower the deposition rate, ensuring improved dielectric properties and good control over film thickness. Measurements made on MOS capacitors of current-voltage characteristics, electrical breakdown, interface trap density, and mobile ion drift indicate that these very thin PECVD films are approaching thermally grown SiO2in quality and may be suitable as gate dielectrics in device applications.     

Hot-carrier memory effect in an Al/SiN/SiO2/Si MNOS diode due to electrical stress

An Al/SiN(70 Å)/SiO2(126 Å)/(p)Si MNOS diode was fabricated by using the LOCOS process. The interface trap densities at SiN-SiO2and at the SiO2-Si interface were measured by a CV method. Successive stresses of biasing at -20 V introduces both trap densities. Memory effect of the flat-band shifts was observed. The electron traps were first produced at the SiN-SiO2interface. In addition, the hole traps were also produced owing to the two-step barrier formation in the insulators. Fowler-Nordheim tunneling may be responsible for the trapping in the oxide. The hole traps can be annealed while the electron traps cannot be.     

Reliability of ultra thin ZrO2 films on strained-Si

Ultra thin high-k zirconium oxide (equivalent oxide thickness 1.57 nm) films have been deposited on strained-Si/relaxed-Si_0.8Ge_0.2 heterolayers using zirconium tetra-tert-butoxide (ZTB) as an organometallic source at low temperature (<200 °C) by plasma enhanced chemical vapour deposition (PECVD) technique in a microwave (700 W, 2.45 GHz) plasma cavity discharge system at a pressure of 66.67 Pa. The trapping/detrapping behavior of charge carriers in ultra thin ZrO₂ gate dielectric during constant current (CCS) and voltage stressing (CVS) has been investigated. Stress induced leakage current (SILC) through ZrO₂ is modeled by taking into account the inelastic trap-assisted tunneling (ITAT) mechanism via traps located below the conduction band of ZrO₂ layer. Trap generation rate and trap cross-section are extracted. A capture cross-section in the range of 10⁻¹⁹ cm² as compared to 10⁻¹⁶ cm² in SiO₂ has been observed. The trapping charge density, Q_ot and charge centroid, X_t are also empirically modeled. The time dependence of defect density variation is calculated within the dispersive transport model, assuming that these defects are produced during random hopping transport of positively charge species in the insulating layer. Dielectric breakdown and reliability of the dielectric films have been studied using constant voltage stressing. A high time-dependent dielectric breakdown (TDDB, t_bd > 1500 s) is observed under high constant voltage stress.     

Comparison of the orientation effect of SiO2- and Si3N4-encapsulated GaAs MESFET's

This letter compares the influence of stressed-SiO2and Si3N4films on threshold voltage of WSix-gate self-aligned GaAs MESFET's oriented along [011]- and [011]-directions. The experimental results showed that the orientation effect originates, mainly from piezoelectric effect due to strain in the n-layers, induced by the dielectric overlayer. Furthermore, the disagreement among workers regarding the preferable orientation turned out to be due to the difference of the stress-sign in dielectric overlayers employed; it was confirmed that SiO2film is in compressive stress and Si3n4film in tensile stress on GaAs.     

Thermal nitridation of Si and SiO2for VLSI

This paper presents an extensive review of our work on thermal nitridation of Si and SiO2. High-quality ultrathin films of silicon nitride and nitrided-oxide (nitroxide) have been thermally grown in ammonia atmosphere in a cold-wall RF-heated reactor and in a lamp-heated system. The growth kinetics and their dependence on processing time and temperature have been studied from very short to long nitridation times. The kinetics of thermal nitridation of SiO2in ammonia ambient have also been studied. In nitroxide, nitrogen-rich layers are formed at the surface and interface at a very early stage of the nitridation. Then the nitridation reaction mainly goes on in the bulk region with the surface and near interface nitrogen content remaining fairly constant. Our results also indicate the formation of an oxygen-rich layer at the interface underneath the nitrogen-rich layer whose thickness increases slowly with nitridation time. The nitride and nitroxide films were analyzed using Auger electron spectroscopy, grazing angle Rutherford backscattering, and etch rate measurements. MIS devices were fabricated using these films as gate insulators and were electrically characterized usingI - V, C - V, time-dependent breakdown, trapping, and dielectric breakdown techniques. Breakdown, conduction, andC-Vmeasurements on metal-insulator semiconductor (MIS) structures fabricated with these films show that very thin thermal silicon nitride and nitroxide films can be used as gate dielectrics for future highly scaled-down VLSI devices. The electrical characterization results also indicate extremely low trapping in the nitride films. The reliability of ultrathin nitride was observed to be far superior to SiO2and nitroxide due to its much less trapping. Studies show that the interface transition from nitride to silicon is almost abrupt and the morphology and roughness of the interface are comparable to the SiO2-Si interfaces.     

MOS Compatibility of high-conductivity TaSi2/n+poly-Si gates

The MOS-VLSI parameters and process compatibility of a high-conductivity refractory silicide gate with a sheet resistance of ∼ 2 Ω/□ have been evaluated. The gate metallization typically consisted of 2.5 kÅ TaSi2/2.5 kÅ poly-Si, which was sintered prior to patterning with a CF4/O2plasma etch. Measurements were made to determine the metal work function, oxide fixed charge, surface-states density, dielectric strength, oxide defect density, lifetime, current leakage, and the flat-band voltage stability with respect to mobile charge contamination, slow trapping, and hot-electron trapping. On IGFET's (500-Å SiO2, As-implanted source/ drain), VTand β measurements were made as a function of the back-gate bias and the channel length as small as 2 µm. The MOS and IGFET parameters are nearly ideal and correspond to those expected of n⁺poly-Si gates. Static and dynamic bias-temperature aging stability of the VFBis excellent. These characteristics are preserved through subsequent standard VLSI process steps. However, certain process and structure limitations do exist and these have been defined.     

Effects of subgrain boundaries on carrier transport in zone-melting-recrystallized Si films on SiO2-coated Si substrates

The transport properties of zone-melting-recrystallized Si films on SiO2-coated Si substrates have been studied by the fabrication and characterization of thin-film resistors and n-channel MOSFET's. Subgrain boundaries, which are the predominant crystal defects in the films, have a relatively low trapping state density (7-8 × 10¹¹cm^-2) and low resistance. N-channel MOSFET's fabricated in the films exhibit high surface electron mobilities (∼ 640 cm²/V-s) for electron transport either parallel or perpendicular to the subgrain boundaries.     

Hole trapping and breakdown in thin SiO2

The field dependence of the hole generation rate, also known as the impact ionization coefficient α, in thin SiO2(< 20 nm) was characterized by measuring the negative flat-band shift due to hole trapping. In thicker oxides,alpha = alpha_{0}e^{-H/E}where H = 78 MV/cm for electric fields ranging from 7 to 14 MV/cm, which covers the field range from the onset of significant Fowler-Nordheim current to instant breakdown. The similar field dependences of α and charge-to-breakdown supports the model that hole generation and trapping leads to oxide wearout. Because of the fact that positive charge generation is observed for oxide voltage well below the SiO2bandgap, we propose that the generated holes arise from transition between band tails in the amorphous SiO2. It is also observed that α decreases rapidly when the applied oxide voltage is very low; thus α is a function of both oxide field and voltage in general. This suggests that ultra-thin oxide with low operating voltages might be a good candidate for high endurance E²PROM devices at very low oxide field.     

Ultra-thin Ta2O5dielectric film for high-speed bipolar memories

A new capacitor technology, with extremely thin (5.3-20 nm) Ta2O5film deposition and weak-spot oxidation, is developed to realize high capacitance and high reliability. The Ta2O5film was reactively sputtered, followed by weak-spot oxidation. The weak-spot oxidation is achieved by placing the Ta2O5film on Si in a high-temperature dry O2ambient. The oxidation significantly improves the time-dependent-dielectric-breakdown (TDDB) characteristics and reduces the defect density of Ta2O5capacitors without reducing the capacitance by selectively oxidizing the Si surface at weak spots where the Ta2O5is locally thin or missing. The technology is based on the new discovery that Ta2O5film less than 20 nm thick shows no reduction in dielectric breakdown strength after dry O2high-temperature annealing up to 1000° C. The Ta2O5(7.5-nm) capacitor with a capacitance of 8.5 fF/µm²is applied to a high-speed bipolar memory. This makes it possible to reduce the memory cell area to one-third that of a conventional bipolar memory. The memory provides high-speed operation; access time is less than 5 ns, and sufficient soft error immunity is provided.     

Device quality MOS Gate insulators: Sputter deposition and low temperature processing

A series of n-channel, Al-gate MOS transistors were fabricated using reactively sputtered SiO2as the gate insulator. The SiO2was deposited at low temperatures and low RF powers, and during subsequent processing was not subjected to temperatures in excess of 465°C. Test results showed that for gate oxides deposited at 20 W, the measured breakdown strength was 3-4 MV/cm with interface trapped charge density of 4-8 × 10¹⁰cm^-2and that the resulting electron mobility of the transistor was 470 cm²/V.s. After annealing in nitrogen at 1000°C, the deposited oxides exhibited electrical properties which are very similar to those of thermally grown SiO2.     

Schottky barriers and ohmic contacts on n-type InP based compound semiconductors for microwave FET's

InP, and In0.73Ga0.27As0.6P0.4, and In0.53Ga0.47As lattice matched to InP are of special importance as active FET channel materials because of the high electron velocity and/or high electron mobility they offer. Using a AuGe/Ni/Au metallization system, specific contact resistances of 5 × 10^-7Ω . cm², 8 × 10^-7Ω . cm², and 5.8 × 10^-6Ω cm²were obtained for ohmic contacts on In0.53Ga0.47As, InP, and In0.89Ga0.11As0.24P0.76, respectively. Leakage currents of 10 µA at 7-V reverse bias were observed for 1 × 200-µm gates on InP. and In0.89Ga0.11As0.24P0.76FET's having a SiO2film about 50 Å thick under the gate. A thin SiO2layer underneath the gate improved the Schottky-gate I-V characteristics, but thick oxides severely degraded the microwave performance of the FET's. These excellent ohmic contacts and Schottky barriers resulted in a maximum insertion gain of 15 dB at 8 GHz and a noise figure of 2.5 dB with 8-dB gain at 7 GHz for the InP deviees. For 1.15-eV InxGa1-xAsyP1-yFET's, the resulting gain was 9 dB at 8 GHz.     

Hole trapping and trap generation in the gate silicon dioxide

Oxide breakdown has been proposed to be a limiting factor for future generation CMOS. The breakdown is caused by defect generation in the oxide. Although electron trap generation has received much attention, there is little information available on the hole trap generation. The relatively high potential barrier for holes at the oxide/Si interface makes it difficult to achieve a high level of hole injection. Most previous work was limited to an injection level Q_inj of 10¹⁴ cm^-2. In this paper, we investigate the hole trapping and trap generation when Q_inj reaches the order of 10¹⁸ cm^-2. When Q_inj <10¹⁵ cm^-2, the trapping is dominated by the as-grown traps. As Q_inj increases further, however, it is found that the generation of new traps controls the trapping. The trap generation does not saturate up to the oxide breakdown. The trapping kinetics for both the as-grown and the generated traps is studied. The relationship between the density of generated traps and the Q_inj is explored. Attention is paid to how the trapping and trap generation depends on the distance from the interface. In contrast to the uniform generation of electron traps across the oxide, we found that the hole trap generation was not uniform and it moved away from the interface as Q_inj increased     

Common origin for electron and hole traps in MOS devices

Experimental evidence is provided to show that many electron and hole traps found in ultraclean and annealed SiO2layers are related to intrinsic oxygen deficient defects. These trapping sites are found to play a dominant role in low-field oxide breakdown, radiation sensitivity, and interface state generation in MOS devices. The saturation of SiO2with oxygen leads to the elimination of a large number of these traps and to the stabilization of SiO2layers for use in submicrometer devices.     

Tapered windows in phosphorus-doped SiO2by ion implantation

Phosphorus-doped SiO2is frequently used as a dielectric coating in silicon integrated circuits. It is important that windows in this dielectric have sufficiently tapered walls so that the subsequent metallization has good step coverage. It is shown here that tapered windows can be made in both Nitrox-deposited ∼ 1-percent phosphorus-doped SiO2and Silox-deposited ∼ 7-percent phosphorus-doped SiO2as well as undoped SiO2by an ion implantation which produces a thin damaged layer at the top of the oxide. The damaged layer etches at a faster rate than the undamaged oxide. This fast-etching layer undercuts the photoresist which serves as the etching mask and results in window walls having slopes in the range of 30-40° with respect to the wafer surface. Tapering windows by ion implantation is a dependable process that gives reproducible results without having to rely on the art of photoresist liftoff methods.     

Anodic oxidation of Si in oxygen/chlorine plasma

By adding a few percent of chlorine to oxygen plasma, the anodization rate of Si was enhanced; for example, the rate was doubled for oxygen containing 3-percent chlorine. With a chlorine concentration of 1.5 percent, the density of trap states at the Si-SiO2interface was reduced from 7×10¹¹/cm².eV to 5×10¹¹/cm².eV at the midgap of Si; after annealing at 800°C in argon for 60 min, it was reduced to 8 × 10¹⁰/cm².eV, and did not return to the original value after heating the specimen to 800°C. The density and capture cross section of traps in plasma-anodic oxide were also measured using the constant-current avalanche-injection method. The number of electron traps with small cross sections in plasmaanodic SiO2films was reduced by annealing them at 800°C in argon, but SiO2films which were anodized in oxygen/chlorine plasma showed an increase of trap density under the same annealing condition.     

Hot-electron trapping in thin LPCVD SiO2dielectrics

The electron-trapping and surface-state generation characteristics of thin LPCVD SiO2dielectrics have been studied using avalanche hot-electron injection. Layered structures of thermal and LPCVD oxide have been examined as a function of anneal time and temperature. After a 1000°C anneal, bulk trapping in the LPCVD oxide was reduced to levels comparable to those in a high-quality dry thermal oxide. Sensitivity to remaining traps was reduced by the presence of a thermal oxide layer on the semiconductor surface. After a post-deposition anneal (PDA), these layered surfaces demonstrated hot-electron performance equal to that of thermal oxide within measurable limits. Also, layered structures generally demonstrated better resistance to surface-state generation than thermal oxides alone. Since less chlorine is incorporated into the layered structures during fabrication, this result is consistent with a recent model identifying broken chlorine bonds as the origin of surface states.     

Transport properties of thermal oxide films grown on polycrystalline silicon—Modeling and experiments

A theoretical model considering the effects of Fowler-Nordheim tunneling, image-force lowering, first-order trapping kinetics, impact ionization, and asperity-induced field enhancement has been developed to investigate the ramp-voltage-stressed I-V characteristics of the oxide films thermally grown on the polycrystalline silicon. From the ramp-voltage-stressed I-V measurements, the important physical parameters such as average field-enhancement factor, effective total trapping density, trap capture cross section, recombination capture cross section, and dielectric breakdown field can be extracted. Under a ramp voltage stress, it is shown that the serious asperity effect can lead to a larger leakage current and a weaker dielectric breakdown field, but the serious trapping effect may reduce the leakage current and enlarge the dielectric breakdown field. Moreover, dry O2oxidation at a higher temperature and steam oxidation at a lower temperature can result in a better quality poly-oxide because the asperity-induced field enhancement is weakened and the electron trapping effect is slightly increased. Besides, high-temperature dry O2oxidation can result in a smaller asperity effect as compared with steam oxidation, and the quality of the poly-oxide is deteriorated when the poly-Si substrate is heavily doped because the asperity effect is enhanced.     

Ion-sensitive field-effect transistors with inorganic gate oxide for pH sensing

Ion-sensitive field-effect transistors (ISFET's) have been fabricated by using silicon films on sapphire substrates (SOS). Using this structure SiO2, ZrO2, and Ta2O5films are examined as hydrogenion-sensitive materials, and Ta2O5film has been found to have the highest pH sensitivity (56 mV/pH) among them. The measured pH sensitivity of this SOS-ISFET's is compared with the theoretical sensitivity based on the site-binding model of proton dissociation reaction on the metal oxide film and good agreement between them is obtained.     

The Impact of Nitrogen Engineering in Silicon Oxynitride Gate Dielectric on Negative-Bias Temperature Instability of p-MOSFETs: A Study by Ultrafast On-The-Fly $I_{rm DLIN}$ Technique

Degradation of p-MOSFET parameters during negative-bias temperature instability (NBTI) stress is studied for different nitridation conditions of the silicon oxynitride (SiON) gate dielectric, using a recently developed ultrafast on-the-fly I_DLIN technique having 1-mus resolution. It is shown that the degradation magnitude, as well as its time, temperature, and field dependence, is governed by nitrogen (N) density at the Si/SiON interface. The relative contribution of interface trap generation and hole trapping to overall degradation as varying interfacial N density is qualitatively discussed. Plasma oxynitride films having low interfacial N density show interface trap dominated degradation, whereas relative hole trapping contribution increases for thermal oxynitride films having high N density at the Si/SiON interface.