Optimum RNS sign detection algorithm using MRC-II with special moduli set

In this paper, we present a generic sign detection algorithm based on mixed radix conversion algorithm, MRC-II [M. Akkal, P. Siy, A new mixed radix conversion algorithm MRC-II, Journal of System Architecture (2006)] and also we present an optimum algorithm for sign detection based on a special moduli set where m_n is even. The described algorithm requires only one comparison for sign detection. A new moduli set will also be presented which simplifies MRC-II conversion algorithm by eliminating the need for table lookup normally used in MRC hardware implementation. The algorithm does not require ROM table like other algorithms. For a moduli set of four moduli that satisfies the special moduli set conditions, 0 tables are needed to do the conversion, while Szabo and Tanaka MRC algorithm [N.S. Szabo, R.I. Tanaka, Residue Arithmetic and Its Application to Computer Technology, McGraw-Hill, New York, 1967] requires 6 tables with a total table size of 4608 bits; and Huang MRC algorithm [C.H. Huang, A fully ParallelMixed-radix conversion algorithm for residue number applications, IEEE Transactions on Computers c-32 (4) (1983)] requires 10 tables with a total table size of 3840 bits.     

An efficient RNS parity checker for moduli set{2~n-1,2~n 1,2~(2n) 1}and its applications

Residue number system (RNS) has received considerable attention since decades before,because it has inherent carry-free and parallel properties in addition,sub-traction,and multiplication operations. For an odd moduli set,the fundamental problems in RNS,such as number comparison,sign determination,and overflow detection,can be solved based on parity checking. The paper proposes a parity checking algorithm along with related propositions and the certification based on the celebrated Chinese remainder theory (CRT) and mixed radix conversion (MRC) for the moduli set {2n-1,2n 1,22n 1}. The parity checker consists of two modular adders and a carry-look-ahead chain. The hardware implementation requires less area and path delay. Besides,the implementations of number comparison,sign determination,and overflow detection,which are based on this parity checker,are also performed in this paper. And this kind of parity checker can be used as a basic element to design ALUs and DSP module in RNS.     

An efficient RNS parity checker for moduli set {2^n-1, 2^n＋1, 2^2n＋1} and its applications

Residue number system （RNS） has received considerable attention since decades before, because it has inherent carry-free and parallel properties in addition, sub- traction, and multiplication operations. For an odd moduli set, the fundamental problems in RNS, such as number comparison, sign determination, and overflow detection, can be solved based on parity checking. The paper proposes a parity checking algorithm along with related propositions and the certification based on the celebrated Chinese remainder theory （CRT） and mixed radix conversion （MRC） for the moduli set {2^n-1, 2^n＋1, 2^2n＋1}. The parity checker consists of two modular adders and a carry-look-ahead chain. The hardware implementation requires less area and path delay. Besides, the implementations of number comparison, sign determination, and overflow detection, which are based on this parity checker, are also performed in this paper. And this kind of parity checker can be used as a basic element to design ALUs and DSP module in RNS.     

FPGA implementation of reversible watermarking in digital images using reversible contrast mapping

Reversible contrast mapping (RCM) and its various modified versions are used extensively in reversible watermarking (RW) to embed secret information into the digital contents. RCM based RW accomplishes a simple integer transform applied on pair of pixels and their least significant bits (LSB) are used for data embedding. It is perfectly invertible even if the LSBs of the transformed pixels are lost during data embedding. RCM offers high embedding rate at relatively low visual distortion (embedding distortion). Moreover, low computation cost and ease of hardware realization make it attractive for real-time implementation. To this aim, this paper proposes a field programmable gate array (FPGA) based very large scale integration (VLSI) architecture of RCM-RW algorithm for digital images that can serve the purpose of media authentication in real-time environment. Two architectures, one for block size (8 × 8) and the other one for (32 × 32) block are developed. The proposed architecture allows a 6-stage pipelining technique to speed up the circuit operation. For a cover image of block size (32 × 32), the proposed architecture requires 9881 slices, 9347 slice flip-flops, 11291 number 4-input LUTs, 3 BRAMs and a data rate of 1.0395 Mbps at an operating frequency as high as 98.76 MHz.     

A high-throughput and high-capacity IPv6 routing lookup system

With the growing number of routing entries, IP routing lookup has become the major performance bottleneck in backbone routers. In this paper, a complete hardware-based routing lookup system is proposed to achieve high-throughput and high-capacity for IPv6. The proposed system is a cache-centric, hash-based architecture that contains a routing lookup application specific integrated circuit (ASIC) and a memory set. A hash function is used to reduce lookup time for the routing table and ternary content addressable memory (TCAM) effectively resolves the collision problem. The gate count of the ASIC, excluding the binary content addressable memory (BCAM), is about 5306 gates, using an in-house 0.18 μm CMOS single-poly six-metal standard cell library. The results of post-layout simulations show that the ASIC operates in 3.6 ns so that the routing lookup system approaches 260 Mega lookups per second (Mlps), which is sufficient for 100 Gbps networks. The memory density is good, with each routing entry requiring only 64 bits. Moreover, the routing table only needs 10.24 KB on-chip BCAM, 20.04 KB off-chip TCAM and 29.29 MB DRAM for 3.6 M routing entries in the proposed system.     

Residue-to-binary conversion for general moduli sets based on approximate Chinese remainder theorem

The residue number system (RNS) is an unconventional number system which can lead to parallel and fault-tolerant arithmetic operations. However, the complexity of residue-to-binary conversion for large number of moduli reduces the overall RNS performance, and makes it inefficient for nowadays high-performance computation systems. In this paper, we present an improved approximate Chinese remainder theorem (CRT) with the aim of performing efficient residue-to-binary conversion for general RNS moduli sets. To achieve this aim, the required number of fraction bits for accurate residue-to-binary conversion is derived. Besides, a method is proposed to substitute fractional calculations by similar computations based on integer numbers to have a hardware amenable algorithm. The proposed approach results in high-speed and low-area residue-to-binary converters for general RNS moduli sets. Therefore, with this conversion method, high dynamic range residue number systems suitable for cryptography and digital signal processing can be designed.     

A novel adaptive cuckoo search algorithm for intrinsic discriminant analysis based face recognition

This paper presents a novel adaptive cuckoo search (ACS) algorithm for optimization. The step size is made adaptive from the knowledge of its fitness function value and its current position in the search space. The other important feature of the ACS algorithm is its speed, which is faster than the CS algorithm. Here, an attempt is made to make the cuckoo search (CS) algorithm parameter free, without a Levy step. The proposed algorithm is validated using twenty three standard benchmark test functions. The second part of the paper proposes an efficient face recognition algorithm using ACS, principal component analysis (PCA) and intrinsic discriminant analysis (IDA). The proposed algorithms are named as PCA + IDA and ACS–IDA. Interestingly, PCA + IDA offers us a perturbation free algorithm for dimension reduction while ACS + IDA is used to find the optimal feature vectors for classification of the face images based on the IDA. For the performance analysis, we use three standard face databases—YALE, ORL, and FERET. A comparison of the proposed method with the state-of-the-art methods reveals the effectiveness of our algorithm.     

An enhanced one-dimensional SPIHT algorithm and its implementation for TV systems

In general, to achieve high compression efficiency, a 2D image or a 2D block is used as the compression unit. However, 2D compression requires a large memory size and long latency when input data are received in a raster scan order that is common in existing TV systems. To address this problem, a 1D compression algorithm that uses a 1D block as the compression unit is proposed. 1D set partitioning in hierarchical trees (SPIHT) is an effective compression algorithm that fits the encoded bit length to the target bit length precisely. However, the 1D SPIHT can have low compression efficiency because 1D discrete wavelet transform (DWT) cannot make use of the redundancy in the vertical direction. This paper proposes two schemes for improving compression efficiency in the 1D SPIHT. First, a hybrid coding scheme that uses different coding algorithms for the low and high frequency bands is proposed. For the low-pass band, a differential pulse code modulation–variable length coding (DPCM–VLC) is adopted, whereas a 1D SPIHT is used for the high-pass band. Second, a scheme that determines the target bit length of each block by using spatial correlation with a minimal increase in complexity is proposed. Experimental results show that the proposed algorithm improves the average peak signal to noise ratio (PSNR) by 2.97 dB compared with the conventional 1D SPIHT algorithm. With the hardware implementation, the throughputs of both encoder and decoder designs are 6.15 Gbps, and gate counts of encoder and decoder designs are 42.8 K and 57.7 K, respectively.     

A microtranslation table with scratch-drive actuators fabricated from silicon-on-insulator wafer

From a silicon-on-insulator (SOI) wafer, a microtranslation table with scratch-drive actuator (SDA) has been fabricated. The device Si layer of SOI wafer is etched to form the plate of SDA, which is partially connected to the handle Si substrate by the SiO₂ layer. Dicing the handle Si substrate, a microtranslation table with the SDA array has been fabricated. Placing the microtranslation table upside down on the other Si substrate on which a thin conductive film is patterned for the electrical connection, the microtranslation table is moved by the SDA without carrying a metal wire. The moving velocity of 45.5 μm/s has been obtained by applying the voltage of 120 V at the operating frequency of 500 Hz.     

A liquid rate gyroscope using electro-conjugate fluid

We propose a novel liquid rate gyroscope using an electro-conjugate fluid (ECF). The electro-conjugate fluid is a dielectric fluid that works as a smart fluid, generating a powerful jet flow (ECF jet) when subjected to a high DC voltage. In this study, we introduce this functional fluid into gyroscopes. Although the sensing principle for angular rate is based on that of a conventional gas rate sensor, the proposed gyroscope has a much higher sensitivity because the density of the liquid is generally higher than that of a gas. In addition, the gyroscope is small in size because the ECF jet is generated only with a pair of tiny electrodes. In other words, the pumping part of the proposed gyroscope does not need mechanical moving parts, resulting in an ECF gyroscope more suitable for micro-applications than a gas rate sensor, which requires a pumping mechanism inside. We fabricated a prototype of the liquid rate gyroscope (40 mm × 60 mm × t7 mm) and confirmed its characteristics by experiments. The experimental results confirm the effectiveness of the proposed liquid rate gyroscope. The prototype has a scale factor of ?29 mV/(°/s) with an applied voltage of 4.5 kV, which is 2.2 times more sensitive than the conventional gas rate gyroscope.     

A reversible data hiding scheme based on the Sudoku technique

Data hiding, also known as information hiding, plays an important role in information security for various purposes. Reversible data hiding is a technique that allows distortion-free recovery of both the cover image and the secret information. In this paper, we propose a new, reversible data hiding scheme that is based on the Sudoku technique and can achieve higher embedding capacity. The proposed scheme allows embedding more secret bits into a pair of pixels while guaranteeing the good quality of the stego-image. The experimental results showed that the proposed scheme obtained higher embedding capacity than some other previous schemes. In addition, our proposed scheme maintained the good visual quality of the stego-image (i.e., PSNR > 46 dB), which outperforms some existing schemes.     

基于前缀扩展的快速路由查找算法

该文对路由器中的快速路由查找算法进行了研究。针对路由查找算法在查找速度、算法空间复杂度以及插入和删除表项的难度算方法存在的问题,提出了一种快速路由查找算法。该算法通过构造两级索引表结构来减小路由查找的访存次数以提高查找速度;利用前缀扩展的特性并采用特殊的数据结构来构建索引表,能支持动态插入、删除和更新路由;采用压缩技术对二级索引表进行压缩,从而大大减小了路由所需的存储空间。该算法最多四次访存,最少两次访存就完成一次路由查找。由于采用了压缩方法,所需存储空间很小,该算法不仅适合于软件实现,也适合于硬件实现。查找速度快、存储空间小并支持动态插入和删除是该算法的主要特点。     

High resolution ambulatory holter ECG events detection-delineation via modified multi-lead wavelet-based features analysis: Detection and quantification of heart rate turbulence

The presented study describes a false-alarm probability-FAP bounded solution for detecting and quantifying Heart Rate Turbulence (HRT) major parameters including heart rate (HR) acceleration/deceleration, turbulence jump, compensatory pause value and HR recovery rate. To this end, first, high resolution multi-lead holter electrocardiogram (ECG) signal is appropriately pre-processed via Discrete Wavelet Transform (DWT) and then, a fixed sample size sliding window is moved on the pre-processed trend. In each slid, the area under the excerpted segment is multiplied by its curve-length to generate the Area Curve Length (ACL) metric to be used as the ECG events detection-delineation decision statistic (DS). The ECG events detection-delineation algorithm was applied to various existing databases and as a result, the average values of sensitivity and positive predictivity Se = 99.95% and P+ = 99.92% were obtained for the detection of QRS complexes, with the average maximum delineation error of 7.4 msec, 4.2 msec and 8.3 msec for P-wave, QRS complex and T-wave, respectively. Because the heart-rate time series might include fast fluctuations which don’t follow a premature ventricular contraction (PVC) causing high-level false alarm probability (false positive detections) of HRT detection, based on the binary two-dimensional Neyman-Pearson radius test (which is a FAP-bounded classifier), a new method for discrimination of PVCs from other beats using the geometrical-based features is proposed. The statistical performance of the proposed HRT detection-quantification algorithm was obtained as Se = 99.94% and P+ = 99.85% showing marginal improvement for the detection-quantification of this phenomenon. In summary, marginal performance improvement of ECG events detection-delineation process, high performance PVC detection and isolation from noisy holter data and reliable robustness against holter strong noise and artifacts can be mentioned as important merits and capabilities of the proposed HRT detection algorithm.     

Bin packing problems with rejection penalties and their dual problems

In this paper we consider the following problems: we are given a set of n items {u₁, … , u_n} and a number of unit-capacity bins. Each item u_i has a size w_i ∈ (0, 1] and a penalty p_i ⩾ 0. An item can be either rejected, in which case we pay its penalty, or put into one bin under the constraint that the total size of the items in the bin is no greater than 1. No item can be spread into more than one bin. The objective is to minimize the total number of used bins plus the total penalty paid for the rejected items. We call the problem bin packing with rejection penalties, and denote it as BPR. For the on-line BPR problem, we present an algorithm with an absolute competitive ratio of 2.618 while the lower bound is 2.343, and an algorithm with an asymptotic competitive ratio arbitrarily close to 1.75 while the lower bound is 1.540. For the off-line BPR problem, we present an algorithm with an absolute worst-case ratio of 2 while the lower bound is 1.5, and an algorithm with an asymptotic worst-case ratio of 1.5. We also study a closely related bin covering version of the problem. In this case p_i means some amount of profit. If an item is rejected, we get its profit, or it can be put into a bin in such a way that the total size of the items in the bin is no smaller than 1. The objective is to maximize the number of covered bins plus the total profit of all rejected items. We call this problem bin covering with rejection (BCR). For the on-line BCR problem, we show that no algorithm can have absolute competitive ratio greater than 0, and present an algorithm with asymptotic competitive ratio 1/2, which is the best possible. For the off-line BCR problem, we also present an algorithm with an absolute worst-case ratio of 1/2 which matches the lower bound.     

Fast IP routing lookups for high performance routers

The key to the success of the next generation IP networks to provide good services relies on the deployment of high performance routers to do fast IP routing lookups. In this paper, we propose a new algorithm for fast IP lookups using a so-called two-trie structure. The two-trie structure provides the advantages in that less memory space is required for representing a routing table than the standard trie while it still provides fast IP lookups. Based on the simulation result, the memory space can be saved around 27% over the standard trie while a lookup operation takes 1.6 memory accesses in the average case and 8 memory accesses in the worst case. Also, the structure is not based on any assumptions about the distribution of the prefix lengths in routing tables. Thus, increasing the lengths from 32 to 128 bit (from IPv4 to IPv6) does not affect the main structure.     

Ferroelectric properties of direct-patterned half-micron thick PZT film

Ferroelectric properties of direct-patterned PZT(PbZr_0.52Ti_0.48O₃) films with 460 μm × 460 μm size and 510 nm thick were analyzed for applying to micro-detecting devices. A photosensitive solution containing ortho-nitrobenzaldehyde was used for the preparation of direct-patterned PZT film. PZT solution was coated on Pt(1 1 1)/Ti/SiO₂/Si(1 0 0) substrate for three times to obtain half-micron thick film and three times of direct-patterning process were repeated to define a pattern on multi-layer PZT film. Through intermediate and final anneal procedure of direct-patterned PZT film, any shrinkage along horizontal direction was not observed within this experimental condition, i.e., the size of the pattern was preserved after annealing, only a thickness reduction was observed after each annealing treatment. Ferroelectric properties of direct-patterned PZT film with 460 μm × 460 μm size and 510 nm thick were compared with those of un-patterned conventional PZT film and shown to be almost the same. Through this work, the high potentiality of direct-patternable PZT film for applying to micro-devices without the introduction of physical damages from dry-etching could be confirmed.     

Efficient multicast schemes for 3-D Networks-on-Chip

3-D Networks-on-Chip (NoCs) have been proposed as a potent solution to address both the interconnection and design complexity problems facing future System-on-Chip (SoC) designs. In this paper, two topology-aware multicast routing algorithms, Multicasting XYZ (MXYZ) and Alternative XYZ (AL + XYZ) algorithms in supporting of 3-D NoC are proposed. In essence, MXYZ is a simple dimension order multicast routing algorithm that targets 3-D NoC systems built upon regular topologies. To support multicast routing in irregular regions, AL + XYZ can be applied, where an alternative output channel is sought to forward/replicate the packets whenever the output channel determined by MXYZ is not available. To evaluate the performance of MXYZ and AL + XYZ, extensive experiments have been conducted by comparing MXYZ and AL + XYZ against a path-based multicast routing algorithm and an irregular region oriented multiple unicast routing algorithm, respectively. The experimental results confirm that the proposed MXYZ and AL + XYZ schemes, respectively, have lower latency and power consumption than the other two routing algorithms, meriting the two proposed algorithms to be more suitable for supporting multicasting in 3-D NoC systems. In addition, the hardware implementation cost of AL + XYZ is shown to be quite modest.     

Coarse-Grained Parallel Geometric Search

We present a parallel algorithm for solving thenext element search problemon a set of line segments, using a BSP-like model referred to as thecoarse grained multicomputer(CGM). The algorithm requiresO(1) communication rounds (h-relations withh=O(n/p)),O((n/p) log n) local computation, andO((n/p) log p) memory per processor, assumingn/p⩾p. Our result implies solutions to the point location, trapezoidal decomposition, and polygon triangulation problems. A simplified version for axis-parallel segments requires onlyO(n/p) memory per processor, and we discuss an implementation of this version. As in a previous paper by Develliers and Fabri (Int. J. Comput. Geom. Appl.6(1996), 487–506), our algorithm is based on a distributed implementation of segment trees which are of sizeO(n log n). This paper improves onop. cit.in several ways: (1) It studies the more general next element search problem which also solves, e.g., planar point location. (2) The algorithms require onlyO((n/p) log n) local computation instead ofO(log p*(n/p) log n). (3) The algorithms require onlyO((n/p) log p) local memory instead ofO((n/p) log n).     

Securing high resolution grayscale facial captures using a blockwise coevolutionary GA

In biometric systems, reference facial images captured during enrollment are commonly secured using watermarking, where invisible watermark bits are embedded into these images. Evolutionary Computation (EC) is widely used to optimize embedding parameters in intelligent watermarking (IW) systems. Traditional IW methods represent all blocks of a cover image as candidate embedding solutions of EC algorithms, and suffer from premature convergence when dealing with high resolution grayscale facial images. For instance, the dimensionality of the optimization problem to process a 2048 × 1536 pixel grayscale facial image that embeds 1 bit per 8 × 8 pixel block involves 49k variables represented with 293k binary bits. Such Large-Scale Global Optimization problems cannot be decomposed into smaller independent ones because watermarking metrics are calculated for the entire image. In this paper, a Blockwise Coevolutionary Genetic Algorithm (BCGA) is proposed for high dimensional IW optimization of embedding parameters of high resolution images. BCGA is based on the cooperative coevolution between different candidate solutions at the block level, using a local Block Watermarking Metric (BWM). It is characterized by a novel elitism mechanism that is driven by local blockwise metrics, where the blocks with higher BWM values are selected to form higher global fitness candidate solutions. The crossover and mutation operators of BCGA are performed on block level. Experimental results on PUT face image database indicate a 17% improvement of fitness produced by BCGA compared to classical GA. Due to improved exploration capabilities, BCGA convergence is reached in fewer generations indicating an optimization speedup.     

Fast binary and multiway prefix searches for packet forwarding

Backbone routers with tens-of-gigabits-per-second links are indispensable communication devices to deploy on the Internet. The IP lookup operation is the most critical task that must be improved in routers. In this paper, we first present a systematic method to compare prefixes of different lengths. The list of prefixes can then be sorted and stored in a sequential array, which is contrary to the linked lists used in most of trie-based structures. Next, fast binary and multiway prefix searches assisted by auxiliary prefixes are proposed. We also developed a 32-bit representation to encode the prefixes of different lengths. For the large routing tables currently available on the Internet, the proposed multiway prefix search can achieve the worst-case number of memory accesses of three and four if the sizes of the CPU cache lines are 64 bytes and 32 bytes, respectively. The IPv4 simulation results show that the proposed prefix searches outperform the existing IP lookup schemes in terms of lookup times and memory consumption. The simulations using IPv6 routing tables also show the performance advantages of the proposed binary prefix searches. We also analyze the performance of the existing lookup schemes by concurrently considering the lookup speed, the update speed, and the memory consumption. Although the update speed of the proposed prefix search is worse than the dynamic routing table schemes with log(N) complexity for a table of N prefixes, our analysis shows that the overall performance of the proposed binary prefix search outperforms all the existing schemes.