类同轴TSV的高频电学模型与分析

类同轴硅通孔(TSV)是射频三维(3D)集成电路(IC)中常用的垂直互连传输结构。针对该结构提出了一套通用的电阻-电感-电容-电导(RLCG)寄生参数计算公式,以及对应的高频等效电路模型。寄生参数是结构尺寸和材料特性的函数,可以方便地用于预测电学性能。使用三维全波仿真软件对所提出的模型进行了高达100 GHz的仿真验证,并分析了模型的散射参数与结构尺寸之间的关系。最后提出了特征阻抗的计算和优化方法,该方法可以为类同轴TSV的参数的确定提供参考。     

一种对三维芯片中硅通孔进行完整建模与寄生参数提取的有效方法

针对三维芯片中硅通孔（through-silicon via, TSV）的准确电学建模问题,本文提出了一种电阻电容（RC）电路模型以及相应的有效参数提取技术。该电路模型同时考虑了半导体效应与静电场影响,适合于低频与中频的电路信号范围。该方法采用一种基于悬浮随机行走（floating random walk, FRW）算法的静电场电容提取技术,然后将它与刻画半导体效应的MOS电容结合,形成等效电路模型。与Synopsys公司软件Sdevice所采用的对静电场/半导体效应进行完整仿真的方法相比,本文方法计算效率更高,并且也能处理一般的TSV电路版图。对多个含TSV的结构进行了计算实验,结果验证了本文方法在从10KHz到1GHz频率范围内的建模准确性,也显示出它相比Sdevice方法最多有47倍的加速比。     

一种考虑自热效应的互连线缓冲器插入优化模型

Considering the self-heating effect,an accurate expression for the global interconnection resistance per unit length in terms of interconnection wire width and spacing is presented.Based on the proposed resistance model and according to the trade-off theory,a novel optimization analytical model of delay,power dissipation and bandwidth is derived.The proposed optimal model is verified and compared based on 90 nm,65 nm and 40 nm CMOS technologies.It can be found that more optimum results can be easily obtained by the proposed model.This optimization model is more accurate and realistic than the conventional optimization models,and can be integrated into the global interconnection design of nano-scale integrated circuits.     

RF-CMOS建模:一种改进的累积型MOS变容管模型

提出一种改进的累积型MOS变容管射频模型,改进后模型方程可精确描述累积型MOS变容管全工作区域特性;模型方程连续,且任意阶次可导,至少三阶导数求解结果可实现与测试结果的精确拟合,解决了原模型可导但导数错误、变阻方程不连续等问题.模型最终应用到采用CSM(Chartered Semiconductor Manufacture Ltd)0.25μm RF-CMOS工艺制造的一30栅指(每指尺寸为长L=1μm,宽W=4.76μm)累积型MOS变容管建模中,测量和仿真所得C-V,R-V特性,品质因素以及高达39GHz S参数对比结果验证了模型的良好精度.     

RF-CMOS建模:一种改进的累积型MOS变容管模型

提出一种改进的累积型MOS变容管射频模型,改进后模型方程可精确描述累积型MOS变容管全工作区域特性;模型方程连续,且任意阶次可导,至少三阶导数求解结果可实现与测试结果的精确拟合,解决了原模型可导但导数错误、变阻方程不连续等问题.模型最终应用到采用CSM(Chartered Semiconductor Manufacture Ltd)0.25μm RF-CMOS工艺制造的一30栅指(每指尺寸为长L=1μm,宽W=4.76μm)累积型MOS变容管建模中,测量和仿真所得C-V,R-V特性,品质因素以及高达39GHz S参数对比结果验证了模型的良好精度.     

Capacitance characterization of tapered through-silicon-via considering MOS effect

In this paper, closed-form expression for the parasitic capacitance of tapered TSV (T-TSV) considering metal–oxide–semiconductor (MOS) effect is proposed by solving two-dimensional (2D) Poisson's equation. ANSYS Q3D Extractor is employed to verify the proposed model for the slope wall angle of 75°, 80°, 85° and 90°. It is shown that error is less than ~5%. The capacitance characterization of copper T-TSV is studied in detail, by taking slope wall angle of 80° for instance. The results show that the capacitance of T-TSV acts as that of MOS device in changing the bias voltage; the increases of the bottom radius of T-TSV (from 1 to 5 μm), dielectric liner thickness (from 0.1 to 0.5 μm), liner dielectric constant (from 1 to 5), T-TSV height (from 10 to 50 μm) and acceptor concentration (from 1×10¹⁵ to 5×10¹⁵ cm⁻³) cause increase of T-TSV capacitance by about 25 fF, −12 fF, 12 fF, 210 fF and 12 fF, respectively. Finally, the condition for T-TSV simplified to cylindrical TSV is obtained.     

双根锥形硅通孔结构的精确RLGC电路模型

A fast RLGC circuit model with analytical expression is proposed for the dual tapered through-silicon via （TSV） structure in three-dimensional integrated circuits under different slope angles at the wide frequency region. By describing the electrical characteristics of the dual tapered TSV structure, the RLGC parameters are extracted based on the numerical integration method. The RLGC model includes metal resistance, metal inductance, substrate resistance, outer inductance with skin effect and eddy effect taken into account. The proposed analytical model is verified to be nearly as accurate as the Q3D extractor but more efficient.     

Air-gap-based RF coaxial TSV and its characteristic analysis

Many 3D IC applications such as MEMS and RF systems require Through-Silicon Via （TSV） with operations for high-speed vertical communication. In this paper, we introduce a novel air-gap coaxial TSV that is suiTab, for such RF applications. Firstly, the detailed fabrication process is described to explain how to acquire such a structure. Then, an Resistor Inductance Conductance Capacitance （RLGC） model is developed to profile the transverse electromagnetic field effect of the proposed air-gap TSV. The model is further verified by a 3D field solver program through the S-parameter comparison. With reference to the numerically simulated results, this analytical model delivers a maximum deviation of less than 6%0, on the conditions of varying diameters, outer to inner radius ratios, and SU-8 central angles, etc. Taking advantages of scalability of the model, a number of air-gap-based TSV designs are simulated, providing 1.6-4.0 times higher bandwidth than the con- ventional coaxial TSVs and leading to an efficient high frequency vertical RF interconnection solution for 3D ICs.     

一种新的单边高压器件的模拟及参数提取方法

单边高压器件具有源、漏电阻不对称且与工作电压成非线形的依赖关系的特点 ,文中提出一种单边高压 MOS器件的模型 ,在不改变 BSIM3 V3模拟模型方程的基础上 ,对 BSIM3 V3模型参数的物理意义和取值进行重新的定义来表示单边高压器件的这些特点。同时使用模型参数提取软件 BSIMPro提取了该模型的参数 ,模拟结果与实验数据进行拟合 ,两者符合得很好 ,证明了改进模型的可行性。     

A transformer with high coupling coefficient and small area based on TSV

Transformer is an important passive device, which is widely used in radio frequency (RF) Integrated circuit (IC). In this paper, three-dimensional transformers with turn ratios of 1:1, 1:2, and 1:3 and with primary and secondary windings nested by TSV technology is proposed. To evaluate the characteristics, the proposed transformers are simulated by HFSS software. The simulation results show that their coupling coefficients are 0.966, 0.966, 0.967, and their area are 3.6 × 10⁻³, 6.0 × 10⁻³, 9.6 × 10⁻³mm². Compared with the other literature, the proposed transformers have good coupling and small area.     

A complete resistance extraction methodology and circuit models for typical TSV structures

Through-silicon via (TSV) is one of the key technologies on three-dimensional integration packaging. In this article, an experimental methodology with circuit models was proposed for electrical characteristic tests on typical TSV structures. To this end, self-developed test patterns such as the via chains, the snake interconnections and the Kelvin structures with different dimensions were designed and manufactured. Suitable electrical measurement methodologies were next employed to characterise the element behaviours of the patterns. Based on the experimental data, electrical circuit models for the TSV structures were introduced and the parameters of the model were exacted. The validity and accuracy of the electrical model were finally verified and the TSV characteristic measurements can be performed through a simpler process.     

Algorithms for TSV resource sharing and optimization in designing 3D stacked ICs

Under the current process and layer bonding technology for the TSV (through-silicon-via) based 3D ICs, it is known that the TSV resource is one of the major sources of the function failure of the chip. Furthermore, TSV takes much larger size and pitch than the normal logic components. For this reason, a careful allocation of the TSV resource has been required in 3D IC designs, and several works have been proposed to allocate minimal TSVs. This work also addresses the problem of TSV allocation and optimization, but overcomes one of the critical limitations of the previous works, which is the unawareness or no exploitation of the possibility of TSV resource sharing, previously merely resorting to a simple binding of the data transfers to TSVs. This is because the previous 3D layer partitioners have performed TSV allocation and minimization without any link to the data transfer information accessible from the high-level synthesis flow. This work proposes a set of TSV resource sharing and optimization algorithms (as a post-processing of 3D layer partitioning) by utilizing the life time information of the data transfers taken from the high-level synthesis. Specifically, we propose three algorithms for TSV resource sharing and optimization, which can be selectively applied depending on the sharing granularity and design complexity: (1) word-level TSV sharing, (2) bit-level TSV sharing, and (3) TSV refinement combined with register replication. Through experiments with benchmark designs, it is confirmed that our proposed algorithms are able to reduce the number of TSVs by 41.1% on average in word-level TSV sharing and 26.0% in bit-level TSV sharing compared with the results produced by the conventional layer partitioning with no TSV sharing while still meeting the timing constraint of designs.     

Scalable wideband equivalent circuit model for silicon-based on-chip transmission lines

A scalable wideband equivalent circuit model of silicon-based on-chip transmission lines is presented in this paper along with an efficient analytical parameter extraction method based on improved characteristic function approach, including a relevant equation to reduce the deviation caused by approximation. The model consists of both series and shunt lumped elements and accounts for high-order parasitic effects. The equivalent circuit model is derived and verified to recover the frequency-dependent parameters at a range from direct current to 50 GHz accurately. The scalability of the model is proved by comparing simulated and measured scattering parameters with the method of cascade, attaining excellent results based on samples made from CMOS 0.13 and 0.18μm process.