A hierarchical model for characterising spatial wafer variations

Silicon wafers are commonly used materials in the semiconductor manufacturing industry. Their geometric quality directly affects the production cost and yield. Therefore, improvement in the quality of wafers is critical for meeting the current competitive market needs. Conventional summary metrics such as total thickness variation, bow and warp can neither fully reflect the local variability within each wafer nor provide useful insight for root cause diagnosis and quality improvement. The advancement of sensing technology enables two-dimensional (2D) data mapping to characterise the geometric shapes of wafers, which provides more information than summary metrics. The objective of this research is to develop a statistical model to characterise the thickness variation of wafers based on 2D data maps. Specifically, the thickness variation of wafers is decomposed into macro-scale and micro-scale variations, which are modelled as a cubic curve and a first-order intrinsic Gaussian Markov random field, respectively. The models can successfully capture both the macro-scale mean trend and the micro-scale local variation, with important engineering implications for process monitoring, fault diagnosis and run-to-run control. A practical case study from a wafer manufacturing process is performed to show the effectiveness of the proposed methodology.     

大型硅晶片平面度精密纳米计量技术

描述了一种基于斜率传感器的大型硅晶片平面度扫描测量系统．采用二维斜率传感器对晶片表面扫描，以获得表面绕X和Y轴的倾斜度．斜率传感器装在X向滑板上，而晶片固定在可绕Z轴转动的主轴上．对斜率传感器Y向的输出积分，得到晶片表面各个同心圆上轮廓截面高度．对斜率传感器X向的输出积分，得到晶片表面沿X向的截面轮廓，从而获得各同心圆轮廓之间的关系．构建了一个包括基于自准直原理的小型斜率传感器、气浮主轴、气浮导轨的实验系统，提出一种斜率传感器现场标定方法，用此系统测量了直径300mm的硅晶片平面度。     

标准硅片厚度测量装置的研制

利用电感测微仪的高分辨率和红宝石工作台的高灵敏度,在对传感器进行非线性修正的基础上,提出了垂直于标准硅片表面方向的点对点测量方法,研制了标准硅片厚度测量装置.整套装置适用于直径不大于305 mm标准硅片的厚度校准,对不同的直径和厚度的标准硅片,测量不确定度达到0.2μm.通过对不同厚度的标准硅片进行测量和比对,验证了装置的测量不确定度,具有结构紧凑、操作简便、准确度高、可靠性好的特点,实现了标准硅片厚度的量值溯源.     

Markov Random Fields in Pattern Recognition for Semiconductor Manufacturing

Under the most general conditions of an anisotropic Markov random field, we model the two-dimensional spatial distribution of microchips on a silicon wafer. The proposed model improves on its predecessors as it stipulates the spatial correlation of different strengths in all eight directions. Its canonical parameters represent the intensity of failures, main effects, and interactions of neighboring chips. Explicit forms of conditional distributions are derived, and maximum pseudo-likelihood estimates of canonical parameters are obtained. This numerical characteristic summarizes general patterns of clusters of failing chips on a wafer, capturing their size, shape, direction, density, and thickness. It is used to classify incoming wafers to known root-cause categories by matching them to the closest pattern.     

A spatial variable selection method for monitoring product surface

Two-dimensional (2-D) data maps are generated in certain advanced manufacturing processes. Such maps contain rich information about process variation and product quality status. As a proven effective quality control technique, statistical process control (SPC) has been widely used in different processes for shift detection and assignable cause identification. However, charting algorithms for 2-D data maps are still vacant. This paper proposes a variable selection-based SPC method for monitoring 2-D wafer surface. The fused LASSO algorithm is firstly employed to identify potentially shifted sites on the surface; a charting statistic is then developed to detect statistically significant shifts. As the variable selection algorithm can nicely preserve shift patterns in spatial clusters, the newly proposed chart is proved to be both effective in detecting shifts and capable of providing diagnostic information for process improvement. Extensive Monte Carlo simulations and a real example have been used to demonstrate the effectiveness and usage of the proposed method.     

碳化硅粒径分布对单晶硅线切割的影响

研究不同粒度分布的碳化硅磨料对线切割硅片表面损伤的影响,利用激光粒度仪和扫描电镜对切割前后碳化硅粒径的变化及切割后硅片的形貌进行表征,通过实际切割过程分析,指出粒度分布不均引起的局部切割堵塞而导致的垂直于切割方向的左右侧滑振动,是导致表面损伤的主要原因。结果表明:当碳化硅的粒度分布窄时,线切割硅片表面损伤层浅,表面粗糙度小。     

Strength of silicon wafers: fracture mechanics approach

This paper describes a model to predict mechanical strength distribution of silicon wafers. A generalized expression, based on a multimodal Weibull distribution, is proposed to describe the strength of a brittle material with surface, edge, and bulk flaws. The specific case of a cast, unpolished photovoltaic (PV) wafer is further analyzed. Assuming that surface microcracks constitute the dominant mechanism of wafer breakage, this model predicts the strength distribution of PV silicon that matches well the experimental results available in the literature.     

Analysis of integrated circuit fault data using generalized linear models

Fault data for integrated circuits manufactured on silicon wafers are usually presented using wafer maps to indicate the spatial distribution of defects. This paper shows how this type of spatial data can be analyzed under the framework of generalized linear models. This provides a systematic method for monitoring the quality of a manufacturing process, and identifying fault sources with assignable causes that may possibly be eliminated with process improvement as a result. We consider models that account for different spatial patterns and, in particular, the observed phenomenon that the faults are distributed non‐uniformly across the wafer. Furthermore, we demonstrate how designed experiments can be used in optimizing the setting of important process parameters. Copyright © 2000 John Wiley & Sons, Ltd.     

A model-based clustering approach to the recognition of the spatial defect patterns produced during semiconductor fabrication

Defects on semiconductor wafers tend to cluster and the spatial defect patterns of these defect clusters contain valuable information about potential problems in the manufacturing processes. This study proposes a model-based clustering algorithm for automatic spatial defect recognition on semiconductor wafers. A mixture model is proposed to model the distributions of defects on wafer surfaces. The proposed algorithm can find the number of defect clusters and identify the pattern of each cluster automatically. It is capable of detecting defect clusters with linear patterns, curvilinear patterns and ellipsoidal patterns. Promising results have been obtained from simulation studies.     

Tantalum metallization and properties of silicon MOS structures under stress

Stresses at the surface of a silicon wafer and at the Si-SiO₂ interface were induced by the sputter deposition of tantalum films. The sputtering of tantalum produced deformation of the silicon wafers by bending, and the radius of curvature was a function of the tantalum sputtering voltage and the tantalum film thickness. The magnitude of the stress induced at the silicon surface was determined from automatic Bragg angle control measurements of the radius of curvature. The surface distribution of the strain field and its distribution in the bulk of the silicon wafer were observed by the use of X-ray transmission topography. The electrical properties of the MOS capacitor were studied as a function of the induced stress. It was found that the largest changes with induced stress occur in the values of recombination time and capture cross section, while the surface state charge density Q_ss and the surface state density N_ss are not significantly affected. Auger electron spectroscopy showed that implanted tantalum atoms diffuse through the SiO₂ and reach the silicon surface.     

A discrete spatial model for wafer yield prediction

Yield analysis is one of the key concerns in the fabrication of semiconductor wafers. An effective yield analysis model will contribute to production planning and control, cost reductions and the enhanced competitiveness of enterprises. In this article, we propose a novel discrete spatial model based on defect data on wafer maps for analyzing and predicting wafer yields at different chip locations. More specifically, based on a Bayesian framework, we propose a hierarchical generalized linear mixed model, which incorporates both global trends and spatially correlated effects to characterize wafer yields with clustered defects. Both real and simulated data are used to validate the performance of the proposed model. The experimental results show that the newly proposed model offers an improved fit to spatially correlated wafer map data.     

Using thin film stress to produce precision, figured X-ray optics

We are studying the possibility of producing precision, aspherical mirrors for X-rays and visible light. Our study examines the use of ultrastructure processing to replace mechanical methods of material removal. The method starts with a chemically-mechanically polished, flat silicon wafer. The aim is to preserve atomic scale smoothness of the surface wafer while the wafer is bent to a desired figure. We report measurements of the mechanical properties of various stressing layers. This involves measuring the deformation of several thin silicon wafers coated with chemically vapor deposited nickel and boron films of known thickness. We have found that, under normal conditions, the film does not add to the microroughness of the substrate on either the front or the back surfaces. Film and substrate thicknesses, however, vary by as much as 10%. This is the present limit on figure accuracy. We have developed a model that describes bending of B/Si and Ni/Si structures. The model relates stress and Young's modulus to the measured thickness of the film, and the thickness and curvature of the substrate. This approach is used to measure the stress and Young's modulus for boron and nickel films. The Young's modulus E_f was 3.05 x 10¹² Pa for the boron films and 1.4 x 10¹⁰ Pa for the nickel films. From the relationship developed and verified for predicting the radii of curvature of the substrate, if may be possible to define a film thickness pattern which would provide a desired optical figure.     

Simultaneous order-lot pegging and wafer release planning for semiconductor wafer fabrication facilities

In semiconductor wafer fabrication facilities, order-lot pegging is the process of assigning wafer lots to orders and meeting the due dates of orders is considered one of the most important operational issues. In many cases of order-lot pegging, some orders cannot be fulfilled with the current wafers in the lots being processed, necessitating the release of additional new wafer lots into the wafer fabrication facility. In this paper, we propose a simultaneous decision model for order-lot pegging and wafer release planning in semiconductor wafer fabrication facilities, and develop a Lagrangian heuristic for solving the model. The results of computational experiments conducted using randomly generated problem instances that mimic actual field data from a Korea semiconductor wafer fabrication facility indicate that the performance of the Lagrangian heuristic is superior to that of a practical greedy algorithm for practical-sized problem instances. The results also point to how sensitivity analysis can be used to answer important managerial questions for effective management of the semiconductor wafer fabrication process.     

Epitaxial silicon carbide on a 6″ silicon wafer

The results of the growth of silicon-carbide films on silicon wafers with a large diameter of 150 mm (6″) by using a new method of solid-phase epitaxy are presented. A SiC film growing on Si wafers was studied by means of spectral ellipsometry, SEM, X-ray diffraction, and Raman scattering. As follows from the studies, SiC layers are epitaxial over the entire surface of a 150-mm wafer. The wafers have no mechanical stresses, are smooth, and do not have bends. The half-width of the X-ray rocking curve (FWHM_ω?θ) of the wafers varies in the range from 0.7° to 0.8° across the thickness layer of 80–100 nm. The wafers are suitable as templates for the growth of SiC, AlN, GaN, ZnO, and other wide-gap semiconductors on its surface using standard CVD, HVPE, and MBE methods.     

硅晶圆磨削减薄工艺的磨削力模型

硅晶圆磨削减薄是一种有别于传统磨削的材料加工方式。磨削减薄过程中,硅晶圆和砂轮同时绕旋转轴旋转,砂轮沿垂直方向连续进给去除材料,其中磨削力是磨削质量的决定性因素。目前,尚缺少一个用于硅晶圆磨削减薄工艺的磨削力预测模型。为了得到磨削力模型,分析了磨削减薄过程中的硅晶圆材料去除机理,将磨削力分为摩擦力和切屑力,考虑了磨粒运动轨迹,分别计算了单颗磨粒在法向和切向上的摩擦力和切屑力,最后基于有效磨粒总数建立了总磨削力模型。模型综合考虑了磨削参数、砂轮和硅晶圆的几何参数和材料性质对磨削力的影响。讨论了砂轮进给速度、晶圆转速和砂轮转速三个主要磨削参数对磨削力的影响,讨论了硅晶圆上晶向对磨削力的影响,给出了磨削力在硅晶圆面上沿径向的分布情况。     

Influence of plasma heating of wafer substrates on SiO2 deposition rate in a TEOS/O2 high-density plasma CVD system

The influence of plasma heating of the Si and glass wafer substrates on silicon dioxide (SiO₂) deposition rates by a tetraethylorthosilicate/O₂ supermagnetron (high-density) plasma CVD were investigated. With a fixed RF power of 100 W supplied to both upper and lower electrodes, the SiO₂ deposition rate on the Si wafer substrate decreased with increasing wafer-stage temperature, showing a negative activation energy for the deposition rate. When Si and glass wafers were attached to the electrode using adherent thermal conductors, the film thickness increased almost linearly with regard to the deposition time, and both deposition rates became almost the same (about 310 Å/min). When both wafers were simply laid on the electrode without an adhesive bond and hence with poor thermal contact, the film thickness increased nonlinearly with deposition time, showing a gradual decrease in deposition rate with time, being as low as 80 and 150 Å/min, respectively for Si and glass wafers, for a deposition time of 15 min. The difference between the two deposition rates on Si and glass wafers in the case of poor thermal contact to the lower electrode is thought to be caused by plasma heating and related mainly to differences in optical absorption characteristics of the two wafer substrates. Variations in measured thickness distributions across the substrate surface were attributed to an antisymmetric plasma density distribution in the direction perpendicular to the magnetic field lines caused by E×B electron drift.     

A reclaiming process for solar cell silicon wafer surfaces

The low yield of epoxy film and Si3N4 thin-film deposition is an important factor in semiconductor production. A new design system using a set of three lamination-shaped electrodes as a machining tool and micro electro-removal as a precision reclaiming process of the Si3N4 layer and epoxy film removal from silicon wafers of solar cells surface is presented. In the current experiment, the combination of the small thickness of the anode and cathodes corresponds to a higher removal rate for the thin films. The combination of the short length of the anode and cathodes combined with enough electric power produces fast electroremoval. A combination of the small edge radius of the anode and cathodes corresponds to a higher removal rate. A higher feed rate of silicon wafers of solar cells combined with enough electric power produces fast removal. A precise engineering technology constructed a clean production approach for the removal of surface microstructure layers from silicon wafers is to develop a mass production system for recycling defective or discarded silicon wafers from solar cells that can reduce pollution and lower cost.     

Radiation thermometry of silicon wafers based on emissivity-invariant condition

An emissivity-invariant condition for a silicon wafer was determined by simulation modeling and it was confirmed experimentally. The p-polarized spectral emissivity at a wavelength of 900 nm and at temperatures over 900 K was constant at 0.83 at an angle of about 55.4° irrespective of large variations in the oxide layer thickness and the resistivity due to the different impurity doping concentrations of the silicon wafer. The expanded uncertainty, U(c) = ku(c) (k = 2), of the temperature measurement is estimated to be 4.9 K. This result is expected to significantly enhance the accuracy of radiometric temperature measurements of silicon wafers in actual manufacturing processes.     

Formation of subsurface cracks in silicon wafers by grinding

Single-crystal silicon is an important material in the semiconductor and optical industries.However,being hard and brittle,a silicon wafer is vulnerable to subsurface cracks(SSCs)during grinding,which is detrimental to the performance and lifetime of a wafer product.Therefore,studying the formation of SSCs is important for optimizing SSC-removal processes and thus improving surface integrity.In this study,a statistical method is used to study the formation of SSCs induced during grinding of silicon wafers.The statistical results show that grinding-induced SSCs are not stochastic but anisotropic in their distributions.Generally,when grinding with coarse abrasive grains,SSCs form along the cleavage planes,primarily the{111}planes.However,when grinding with finer abrasive grains,SSCs tend to form along planes with a fracture-surface energy higher than that of the cleavage planes.These findings provide a guidance for the accurate detection of SSCs in ground silicon wafers.     

金刚石线锯切割多晶硅片表面制绒工艺研

晶体硅片的制绒技术是太阳能电池制造工艺中的关键步骤。本研究以工业中酸制绒方法为基础, 研究了腐蚀时间、浓度对绒面结构以及反射率的影响。此外, 还采用金属催化化学腐蚀法进行制绒, 选用氢氟酸和硝酸银作为腐蚀液。而且对两种制绒方法效果进行了对比。研究获得的最优绒面结构及反射率结果的实验条件为: 氢氟酸浓度4.6 mol/L、硝酸银浓度0.02 mol/L, 室温下反应90 min, 得到的平均反射率为8%, 远低于目前多晶硅片制绒生产标准。