基于无冲突多项式交织器的高速并行Turbo解码器

提出了基于高次多项式无冲突交织器的Turbo码并行解码的优化实现方法,解码器采用MAX-Log-MAP算法,完成了从Matlab算法设计验证到RTL设计、FPGA验证,并在LTE无线通信链路中验证.设计的Turbo并行高速解码器半次迭代的效率为6.9 bit/cycle,在最高迭代为5.5次、时钟频率为309MHz下,达到207Mb/s的吞吐率,满足高速无线通信系统的要求,交织和解交织采用存储器映射方法.该设计节约了计算电路和存储量.     

Semi-Iterative Analog Turbo Decoding

Based on multiple-slice turbo codes, a novel semi-iterative analog turbo decoding algorithm and its corresponding decoder architecture are presented. This work paves the way for integrating flexible analog decoders dealing with frame lengths over thousands of bits. The algorithm benefits from a partially continuous exchange of extrinsic information to improve decoding speed and correction performance. The proposed algorithm and architecture are applied to design an analog decoder for double-binary codes. Taking full advantage of multiple slice codes, the on-chip area is shown to be reduced by ten when compared to a conventional fully parallelized analog slice turbo decoder. The reconfigurable analog core area for frames of 40 bits up to 2432 bits is 37 nm² in a 0.25-mum BiCMOS process.     

Design and Architecture of Low‐Latency High‐Speed Turbo Decoders

In this paper, we propose and present implementation results of a high‐speed turbo decoding algorithm. The latency caused by (de)interleaving and iterative decoding in a conventional maximum a posteriori turbo decoder can be dramatically reduced with the proposed design. The source of the latency reduction is from the combination of the radix‐4, center to top, parallel decoding, and early‐stop algorithms. This reduced latency enables the use of the turbo decoder as a forward error correction scheme in real‐time wireless communication services. The proposed scheme results in a slight degradation in bit error rate performance for large block sizes because the effective interleaver size in a radix‐4 implementation is reduced to half, relative to the conventional method. To prove the latency reduction, we implemented the proposed scheme on a field‐programmable gate array and compared its decoding speed with that of a conventional decoder. The results show an improvement of at least five fold for a single iteration of turbo decoding.     

Results on the Improved Decoding Algorithm for Low-Density Parity-Check Codes Over the Binary Erasure Channel

In this correspondence, we first investigate some analytical aspects of the recently proposed improved decoding algorithm for low-density parity-check (LDPC) codes over the binary erasure channel (BEC). We derive a necessary and sufficient condition for the improved decoding algorithm to successfully complete decoding when the decoder is initialized to guess a predetermined number of guesses after the standard message-passing terminates at a stopping set. Furthermore, we present improved bounds on the number of bits to be guessed for successful completion of the decoding process when a stopping set is encountered. Under suitable conditions, we derive a lower bound on the number of iterations to be performed for complete decoding of the stopping set. We then present a superior, novel improved decoding algorithm for LDPC codes over the binary erasure channel (BEC). The proposed algorithm combines the observation that a considerable fraction of unsatisfied check nodes in the neighborhood of a stopping set are of degree two, and the concept of guessing bits to perform simple and intuitive graph-theoretic manipulations on the Tanner graph. The proposed decoding algorithm has a complexity similar to previous improved decoding algorithms. Finally, we present simulation results of short-length codes over BEC that demonstrate the superiority of our algorithm over previous improved decoding algorithms for a wide range of bit error rates     

基于FPGA的Turbo译码交织器设计

介绍了一种Turbo译码交织器的现场可编程门阵列（Field Programmable Gate Array，FPGA）硬件实现方案，将交织算法的软件编程和FPGA内部的硬件存储块相结合，有效地降低了译码器的硬件实现复杂度，减小了译码延时，并且给出了具体的译码器内交织器FPGA实现原理框图。     

Turbo decoder

We propose an adaptive channel SNR estimation algorithm required for the iterative MAP decoding of turbo decoders. The proposed algorithm uses the extrinsic values generated within the iterative MAP decoder to update the channel SNR estimate toward its optimum value per each decoder iteration or per each turbo code frame     

An Efficient Stopping Criterion for Turbo Product Codes

In this letter, a stopping criterion using the error- detecting capability of linear block codes is proposed for the decoding of turbo product codes. The iterative decoding is stopped when the outputs from the Chase decoder are valid codewords for all rows and columns simultaneously. Simulation shows that the proposed method can reduce about one and half iterations compared with an existing stopping method, without noticeable BER performance loss. Some modification has also been discussed which may further reduce the decoding complexity.     

Double-Binary Circular Turbo Decoding Based on Border Metric Encoding

This brief presents an energy-efficient soft-input soft-output (SISO) decoder based on border metric encoding, which is especially suitable for nonbinary circular turbo codes. In the proposed method, the size of the branch memory is reduced to half and the dummy calculation is removed at the cost of a small-sized memory that holds encoded border metrics. Due to the infrequent accesses to the border memory and its small size, the energy consumed for SISO decoding is reduced by 26.2%. Based on the proposed SISO decoder and the dedicated hardware interleaver, a double-binary tail-biting turbo decoder is designed for the WiMAX standard using a 0.18-mum CMOS process, which can support 24.26 Mbps at 200 MHz.     

Stopping Set Analysis of Iterative Row-Column Decoding of Product Codes

In this paper, we introduce stopping sets for iterative row-column decoding of product codes using optimal constituent decoders. When transmitting over the binary erasure channel (BEC), iterative row-column decoding of product codes using optimal constituent decoders will either be successful, or stop in the unique maximum-size stopping set that is contained in the (initial) set of erased positions. Let C_p denote the product code of two binary linear codes C_c and C_r of minimum distances dc and d_r and second generalized Hamming weights d₂(C_c) and d₂(C_r), respectively. We show that the size s_min of the smallest noncode- word stopping set is at least mm(d_rd₂(C_c),d_cd₂(C_r)) > d_rd_c, where the inequality follows from the Griesmer bound. If there are no codewords in C_p with support set S, where S is a stopping set, then S is said to be a noncodeword stopping set. An immediate consequence is that the erasure probability after iterative row-column decoding using optimal constituent decoders of (finite-length) product codes on the BEC, approaches the erasure probability after maximum-likelihood decoding as the channel erasure probability decreases. We also give an explicit formula for the number of noncodeword stopping sets of size s_min, which depends only on the first nonzero coefficient of the constituent (row and column) first and second support weight enumerators, for the case when d₂(C_r) < 2d_r and d₂(C_c) < 2d_c. Finally, as an example, we apply the derived results to the product of two (extended) Hamming codes and two Golay codes.     

Iterative threshold decoding without interleaving for convolutional self-doubly orthogonal codes

A novel iterative error control technique based on the threshold decoding algorithm and new convolutional self-doubly orthogonal codes is proposed. It differs from parallel concatenated turbo decoding as it uses a single convolutional encoder, a single decoder and hence no interleaver, neither at encoding nor at decoding. Decoding is performed iteratively using a single threshold decoder at each iteration, thereby providing good tradeoff between complexity, latency and error performance.     

On the Performance and Implementation Issues of Interleaved Single Parity Check Turbo Product Codes

In this paper, both performance and complexity aspects of two-dimensional single parity check turbo product codes (I-SPC-TPC) are investigated. Based on the proposed I-SPC-TPC coding scheme, a parallel decoding structure is developed to increase the decoding throughput with minor performance degradation compared with the serial structure. For both decoding architectures, a new helical interleaver is constructed to further improve the coding gain. In terms of decoding algorithm, the extremely simple Sign-Min decoding is alternatively derived with only three additions needed to compute each bit's extrinsic information. For performance evaluation, (16, 14, 2)² single parity check turbo product code with code rate 0.766 over AWGN channel using QPSK modulation is considered. The simulation results using Sign-Min decoding show that it can achieve bit-error-rate of 10^?5 at signal-to-noise ratio of 3.8 dB with 8 iterations. Compared to the same rate and codeword length turbo product code composed of extended Hamming codes, the considered scheme can achieve similar performance with much less complexity. Important implementation issues such as the finite precision analysis, efficient sorting circuit design and interleaver memory management are also presented.     

Turbo multiuser detection for differentially modulated CDMA

In this letter, we study differentially modulated, iteratively decoded CDMA. The iterative multiuser receiver proposed consists of an additional soft-input soft-output (SISO) differential decoder, when compared to turbo multiuser detectors for absolutely modulated systems. Algorithms for iterative decoding with and without phase information at the receiver are developed. The resulting turbo receivers with differential modulation outperform coherent receivers with absolute modulation at moderate to high signal to noise ratios due to the interleaver gain associated with recursive inner encoders in serially concatenated encoding structures.     

APPLICATION OF TURBO CODES IN HIGH-SPEED REAL-TIME CHANNEL

I. Introduction Turbo code has obtained comprehensive atten-tion and research due to its near-Shannon perform-ance since it was proposed in 1993[1], and has be-come a research hotspot in information and coding theory area. Application and realization methods of turbo codes in various communication systems have also attracted great interest of researchers. The good BER performance of turbo codes provides it a wide application prospect in deep space and mobile com- munication systems. The IT…     

一种低开销双二元turbo译码器设计

设计一种低开销双二元turbo译码器,提出了一种能够适应滑动窗算法的交织器结构,通过与传统方案中的交织器联合使用,大大降低了交织与解交织过程所需要的存储单元.同时将取模归一化(modulo normalization)技术运用到双二元turbo译码器加比选(ACS)模块的设计上,缩短了关键路径的延时,提高了时钟频率和吞吐量.采用FPGA对译码器进行了验证,提出的译码器和传统的译码器相比,存储资源节省12%,和使用存储器存储交织/解交织地址的译码器相比,存储资源节省97%.     

Turbo decoding of quantized data

Much of the work on turbo decoding assumes that the decoder has access to infinitely soft (unquantized) channel data. In practice, however, a quantizer is used at the receiver and the turbo decoder must operate on finite precision, quantized data. Hence, the maximum a posteriori (MAP) component decoder which was designed assuming infinitely soft data is not necessarily optimum when operating on quantized data. We modify the well-known normalized MAP algorithm taking into account the presence of the quantizer. This algorithm is optimum given any quantizer and is no more complex than quantized implementations of the MAP algorithm derived based on unquantized data. Simulation results on an additive white Gaussian noise channel show that, even with four bits of quantization, the new algorithm based on quantized data achieves a performance practically equal to the MAP algorithm operating on infinite precision data     

A Decoding Algorithm for Turbo Product Codes Using Optimality Test and Amplitude Clipping

This paper presents an iterative soft-input/soft-output (SISO) decoderfor product code using optimality test and amplitude clipping. A modifiedexpression for computing the soft-output of SISO decoder is proposed.The correlation discrepancy is employed to provide an optimality teston the decision codeword. The optimality test is performed in rowand column decoding to evaluate the reliability of row and columndecision codewords. Based on the optimality test, the variable reliabilityfactor is introduced for optimization of turbo decoding. A stoppingcriterion with very little performance degradation is also designedfor turbo decoding of product codes by using the optimality test.Besides, the amplitude clipping is employed to improve the performanceof turbo product code. Simulation results on the performance of theintroduced SISO decoder are presented.     

Improved Turbo Decoding Using Soft Combining Principle

One great challenge in wireless communication systems is to ensure reliable communications. Turbo codes are known by their interesting capabilities to deal with transmission errors. In this paper, we present a novel turbo decoding scheme based on soft combining principle. Our method improves decoding performance using soft combining technique inside the turbo decoder. Working on Max-Log-Maximum a Posteriori (Max-Log-MAP) turbo decoding algorithm and using an Additive White Gaussian Noise (AWGN) channel model and 16 Quadrature Amplitude Modulation (16QAM), simulation results show that the suggested solution is efficient and outperforms the conventional Max-Log-MAP algorithm in terms of Bit Error Rate (BER). The performance analysis is carried out in terms of BER by varying parameters such as the Energy per bit to Noise power spectral density ratio ( \(\text {E}_{\text {b}}/\text {N}_{\text {o}}\) ), and decoding iterations number. We call our proposed solution Soft Combined Turbo Codes.     

一种短延时Turbo编码调制系统的设计

本文设计了一种比传统体制减少了一半延时的Turbo编码调制系统,介绍了交织器的相关限制.提出了一种在译码过程中对信道值的估计方法,使得外信息的计算更加趋于精确,从而提高了译码性能.这种迭代译码算法是标准格码调制译码算法的一种自然推广,同时也类似于二元Turbo码在BPSK调制下的逐比特译码算法.采用吞吐率为2bits/s/Hz的8PSK调制,比特错误率为10^-5所需的信噪比与Shannon限相距不到0.4dB.