MPEG-2音频实时压缩编解码的一种快速算法

采用一片ＴＩ公司的数字信号处理芯片ＴＭＳ３２０Ｃ３１实现了ＭＰＥＧ－２音频Ｌａｙｅｒ－１,Ｌａｙｅｒ－２的实时压缩编解码器。为了达到实时的目的,对ＭＰＥＧ建议的子带分析和子带合成方案分别提出了一种新的快速算法,采用该算法的运算量分别是ＭＰＥＧ标准建议算法运算量的１／５和１／１０。另外,对心理声学模型也做了一些有助于节省运算的改进,所有算法都经过了软件模拟和硬件实时仿真,通过仿真器装载一片ＴＭＳ３２     

Adsp-21060的主机接口在实时图像处理中的应用

简要介绍了数字信号处理器Adsp 2 10 6 0和大规模可编程逻辑器件EP1K5 0。详细讨论了Adsp 2 10 6 0的主机接口工作模式以及一个实时图像跟踪处理器的硬件组成原理 ,在这个系统中EP1K5 0充当了主机。调试结果表明 ,所提出的硬件结构设计思想工作效率高 ,完全能够胜任实时图像处理的实际需要。     

星载SAR实时成像处理器的FPGA实现

本文提出了一种用FPGA实现星载合成孔径雷达实时成像处理器的方法,用来实现星载SAR的CS算法(或RMA算法).该实时成像处理器由7片Xilinx公司的商业FPGA实现,其中4片作为并行的处理单元;一片为CS因子的生成单元;一片为SDRAM控制单元;一片为系统的控制单元.该系统将流水处理和并行处理相结合,从而极大的减少了处理时间.同时根据算法各运算对数据的精度要求不同,将浮点运算和定点运算结合在一块,减少了硬件开销.该系统工作在100MHz时,33秒左右能完成16k*16k星载样本点的成像,并对加拿大Radarsat的雷达原始信号进行成像处理,成像质量能达到要求.     

A floating-point advanced cordic processor

In this paper, a novel architecture of a floating-point digital signal processor is presented. It introduces a single hardware structure with a full set of elementary arithmetic functions which includessin, cos, tan, arctanh, circular rotation andvectoring, sinh, cosh, tanh, arctanh, hyperbolic rotation andvectoring, square root, logarithm, exponential as well asaddition, multiplication anddivision. The architecture of the processor is based on the COordinate Rotation DIgital Computer (CORDIC) and the Convergence Computing Method (CCM) algorithms for computing arithmetic functions and it is fully parallel and pipelined. Its advanced functionality is achieved without significant increase in hardware, in comparison to ordinary CORDIC processor, and makes it an ideal processing element in high speed multiprocessor applications, e.g. real time Digital Signal Processing (DSP) and computer graphics.     

Hardware‐Aware Rate Monotonic Scheduling Algorithm for Embedded Multimedia Systems

Many embedded multimedia systems employ special hardware blocks to co‐process with the main processor. Even though an efficient handling of such hardware blocks is critical on the overall performance of real‐time multimedia systems, traditional real‐time scheduling techniques cannot afford to guarantee a high quality of multimedia playbacks with neither delay nor jerking. This paper presents a hardware‐aware rate monotonic scheduling (HA‐RMS) algorithm to manage hardware tasks efficiently and handle special hardware blocks in the embedded multimedia system. The HA‐RMS prioritizes the hardware tasks over software tasks not only to increase the hardware utilization of the system but also to reduce the output jitter of multimedia applications, which results in reducing the overall response time.     

基于硬件实现的基因算法的研究

本文提出了一种VLSI实现的硬件基因算法.研究了基因算法的各种变种,探讨了它们的性能及硬件实现的可能性.提出了一个能进行群体存储、父本选择、交叉、变异等操作且易于硬件实现的结构.在硬件实现上,用VHDL描述了整个算法.所作的设计是一个通用的VLSI结构,通过流水线结构和并行化操作获得了很好的性能.硬件实现基因算法有效地缩短运行时间,为实时应用提供了可能.整个设计用Altera公司的FLEX10K40型号的芯片进行了FPGA实现,它完全可以用VLSI来实现.     

嵌入式多核系统中断负载均衡研究

针对嵌入式多核系统对中断响应处理的高实时性需求,引入系统运行时中断负载动态计算方法,在此方法基础上,提出多核之间中断负载均衡的方法。在系统运行过程中,将中断交由当前中断负载最低的处理器核处理,避免中断拥塞问题,使得中断能够在最短的时间内得到处理,提高了系统的中断响应处理的实时性。     

A new parallel hardware architecture for high-performance stereo matching calculation

In this paper, we propose a hardware (H/W) architecture to find disparities for stereo matching in real time. After analyzing the arithmetic characteristic of stereo matching, we propose a new calculating method that reuses the intermediate results to minimize the calculation load and memory access. From this, we propose a stereo matching calculation cell and a new H/W architecture. Finally, we propose a new stereo matching processor. The implemented H/W can operate at the clock frequency of 250 MHz at least in the FPGA (field programmable gate array) environment and produce about 120 disparity images per second for HD stereo images.     

A single-chip programmable platform based on a multithreaded processor and configurable logic clusters

This paper presents a single-chip programmable platform that integrates most of hardware blocks required in the design of embedded system chips. The platform includes a 32-bit multithreaded RISC processor (MT-RISC), configurable logic clusters (CLCs), programmable first-in-first-out (FIFO) memories, control circuitry, and on-chip memories. For rapid thread switch, a multithreaded processor equipped with a hardware thread scheduling unit is adopted, and configurable logics are grouped into clusters for IP-based design. By integrating both the multithreaded processor and the configurable logic on a single chip, high-level language-based designs can be easily accommodated by performing the complex and concurrent functions of a target chip on the multithreaded processor and implementing the external interface functions into the configurable logic clusters. A 64-mm/sup 2/ prototype chip integrating a four-threaded MT-RISC, three CLCs, programmable FIFOs, and 8-kB on-chip memories is fabricated in a 0.35-/spl mu/m CMOS technology with four metal layers, which operates at 100-MHz clock frequency and consumes 370 mW at 3.3-V power supply.     

用于会议电视MCU的交换处理单元

介绍了交换处理单元 (SPU)的一种实现方案 ,该交换处理单元用于会议电视多点控制器(MCU)中 ;描述了交换处理单元 (SPU)板的硬件结构设计、硬件接口、工作原理及板上软件实现方法 ,并对用于SPU和处理机之间的命令、响应信息进行了说明 ;依据该方案制作的SPU板可完成视频、音频、数据的切换和多点会议的控制、系统时钟的锁定以及语声选大功能     

实时DIS网络接口部件的设计与实现

计算机网络是分布交互仿真（ＤＩＳ）的关键支撑技术之一。ＤＩＳ的交互性和实时性对计算机网络的实时特性提出了很高的要求。本文简要介绍了ＤＩＳ的实时要求和网络提供实时性采用的措施，重点提出了支持实时传输的网络接口部件的结构，给出了硬件积木式和软件模块化设计的方法，并描述了各部分的功能和实现     

基于DSP的自动调焦系统

由于数字图像处理理论的逐渐成熟和完善,现今的自动调焦系统已由原基于光学系统的自动调焦转换为基于各种数字图像处理方法的自动调焦.由此介绍一种基于DSP芯片TMS320C6416为核心处理器进行图像采集、预处理和实施控制的自动调焦系统.TMS320C6416芯片的总体性能可比C62xx提高一个数量级.重点说明了该实时数字图像处理系统的硬件组成、工作原理和软件算法.结果表明该系统具有高度的实时性和稳定性,能够快速准确的完成自动调焦.     

基于硬件加速的实时二值图像连通域标记算法

针对光学成像制导武器系统对图像处理的实时性要求,该文提出了一种基于硬件加速的2次扫描连通域标记算法。算法结合基于像素和基于游程扫描算法的优点,以像素为基本的扫描单元,以线段为基本的标号单元,在第1次扫描过程中建立临时标号的树形拓扑结构,并输出线段作为结果。第2次扫描对线段进行标号替换完成连通域标记。通过在FPGA+DSP平台中进行实验证明,该文算法的硬件加速实现占用资源少,能够达到较高的性能和执行效率,保证了系统的实时性,具有较高的实用价值。     

一种应用于多带正交频分复用超宽带的IFFT/FFT处理器

针对多带正交频分复用超宽带(MB-OFDM UWB)系统,提出了一种高吞吐量、混合字长、混合基、4并行数据路径的128点IFFT/FFT处理器结构.该处理器采用具有误差补偿的改进Booth定长乘法器和CSD常量乘法器,有效地提高了精度和减少了硬件的复杂度.通过分析,本方案比混合基多路径延迟反馈(MRMDF)结构减少了49%的乘法器资源,在硬件开销相当的情况下,比双并行数据路径结构减少了30%的存储器资源和提高了33%的吞吐量,使该处理器在精度、硬件开销和速度上做了最好的折衷.在0.18μm COMS工艺下,该处理器的最大工作频率达到300 MHz,吞吐量为1.2 Gsamples/s,满足了吉比特无线个人域网络(WPAN)的要求.     

A digital filter bank with polyphase network and FFT hardware: Measurements and applications

Measurements about the frequency and time domain characteristics of two “multi-rate” filter banks: a pure DFT, realized by an FFT processor, and a combination of a special polyphase network with the FFT are reported on. The theoretical comparison and the hardware of both systems were described in a previous paper [1]; this contribution details the measuring arrangement and equipment. Applications are demonstrated, using not only well defined test sequences, but also “real world” signals. Modifications, necessary for possible ameliorations or other applications, are addressed.     

Wireless Communications Transmitter Performance Enhancement Using Advanced Signal Processing Algorithms Running in a Hybrid DSP/FPGA Platform

This paper deals with digital base band signal processing algorithms, which are seen as enabling technologies for software-enabled radios, that are intended for the correction of the analog front end. In particular, this paper focuses on the design, optimization and testability of predistortion functions suitable for the linearization of narrowband and wideband transmitters developed with a hybrid DSP/FPGA platform. To select the best algorithm for the identification of the predistortion function, singular value decomposition, recursive least squares (RLS), and QR-RLS algorithms are implemented on the same digital signal processor; and, the computation complexity, time, accuracy and the required resources are studied. The hardware implementation of the predistortion function is then carefully performed, in order to meet the real time execution requirements.     

A High-Speed Microprogrammable Digital Signal Processor Employing Distributed Arithmetic

This paper describes a gesteral-purpose digital-signal processor which is constructed with 4 bit bipolar microprocessor slices. The signal processor is microprogrammable and contains special features which allow it to employ distributed arithmetic. Hence, the processor can achieve high sampling rates without using a hardware multiplier unit. The processor's architecture is presented and its micro-order structure is examined. The processor wordlength is 16 bit; its basic cycle time, 300 ns; its data memory size, 2K words; its control store size, 256 x 56 bits. It consumes 48 W of power and has special address processing hardware. Experimental results with a twelfth-order digital filter are demonstrated. The signal processor is also compared with several other signal processors of its class described in the literature.     

同步数据转以太网的接口设计

介绍了无人机测控系统中将同步遥测数据转发到以太网中的接口设计,给出了具体的硬件接口设计和详细的软件设计。该设计采用了嵌入式处理器(AT91SAM7X256)和实时操作系统(μC/OS-Ⅱ),编写了TCP/IP服务器/客户端程序,做到了体积小、功耗低、响应快。实验证明该系统运行稳定可靠。     

New continuous-flow mixed-radix (CFMR) FFT Processor using novel in-place strategy

The paper proposes a new continuous-flow mixed-radix (CFMR) fast Fourier transform (FFT) processor that uses the MR (radix-4/2) algorithm and a novel in-place strategy. The existing in-place strategy supports only a fixed-radix FFT algorithm. In contrast, the proposed in-place strategy can support the MR algorithm, which allows CF FFT computations regardless of the length of FFT. The novel in-place strategy is made by interchanging storage locations of butterfly outputs. The CFMR FFT processor provides the MR algorithm, the in-place strategy, and the CF FFT computations at the same time. The CFMR FFT processor requires only two N-word memories due to the proposed in-place strategy. In addition, it uses one butterfly unit that can perform either one radix-4 butterfly or two radix-2 butterflies. The CFMR FFT processor using the 0.18 /spl mu/m SEC cell library consists of 37,000 gates excluding memories, requires only 640 clock cycles for a 512-point FFT and runs at 100 MHz. Therefore, the CFMR FFT processor can reduce hardware complexity and computation cycles compared with existing FFT processors.     

基于广义互补编码的目标识别处理器

提出一种广义互补编码方法,用于一步实现数学形态学击中击不中变换,并以非相干光相关器为光学实现硬件,利用液晶投影板作为实时空间光调制器,研制了一台光电混合目标识别处理器。实验结果表明识别率大于９０％,并对带有４０％噪声,５０％缺损和６°以内旋转的图像甚至不同表情的人脸图像均能识别。