CMOS active pixel image sensor

A new CMOS active pixel image sensor is reported. The sensor uses a 2.0 μm double-poly, double-metal foundry CMOS process and is realized as a 128×128 array of 40 μm×40 μm pixels. The sensor features TTL compatible voltages, low noise and large dynamic range, and will be useful in machine vision and smart sensor applications     

VLSI implementation of a focal plane image processor-a realizationof the near-sensor image processing concept

The near-sensor image processing concept, which has earlier been theoretically described, is here verified with an implementation. The NSIP describes a method to implement a two-dimensional (2-D) image sensor array with processing capacity in every pixel. Traditionally, there is a contradiction between high spatial resolution and complex processor elements, In the NSIP concept we have a nondestructive photodiode readout and we can thereby process binary images without loosing gray-scale information. The global image processing is handled by an asynchronous Global Logical Unit. These two features makes it possible to have efficient image processing in a small processor element. Electrical problems such as power consumption and fixed pattern noise are solved. All design is aimed at a 128×128 pixels NSIP in a 0.8 μm double-metal single-poly CMOS process. We have fabricated and measured a 32×32 pixels NSIP. We also give examples of image processing tasks such as gradient and maximum detection, histogram equalization, and thresholding with hysteresis. In the NSIP concept automatic light adaptivity within a 160 dB range is possible     

A Nyquist-rate pixel-level ADC for CMOS image sensors

A multichannel bit-serial (MCBS) analog-to-digital converter (ADC) is presented. The ADC is ideally suited to pixel-level implementation in a CMOS image sensor. The ADC uses successive comparisons to output one bit at a time simultaneously from all pixels. It is implemented using a 1-bit comparator/latch pair per pixel or per group of neighboring pixels, and a digital-to-analog-converter/controller shared by all pixels. The comparator/latch pair operates at very slow speeds and can be implemented using simple robust circuits. The ADCs can be fully tested by applying electrical signals without any optics or light sources. A CMOS 320×256 sensor using the MCBS ADC is described. The chip measures 4.14×5.16 mm². It achieves 10×10 μm² pixel size at 28% fill factor in 0.35 μm CMOS technology. Each 2×2 pixel block shares an ADC. The pixel block circuit comprises 18 transistors. It operates in subthreshold to maximize gain and minimize power consumption. The power consumed by the sensor array is 20 mW at 30 frames/s. The measured integral nonlinearity is 2.3 LSB, and differential nonlinearity is 1.2 LSB at eight bits of resolution. The standard deviation of the gain and offset fixed pattern noise due to the ADC are 0.24 and 0.2%, respectively     

Wide intrascene dynamic range CMOS APS using dual sampling

A CMOS active pixel sensor (APS) that achieves wide intrascene dynamic range using dual sampling is reported. A 64×64 element prototype sensor with dual output architecture was fabricated using a 1.2 μm n-well CMOS process with 20.4 μm pitch photodiode-type active pixels. The sensor achieves an intrascene dynamic range of 109 dB without nonlinear companding     

A 256×256 pixel smart CMOS image sensor for line-based stereovision applications

This paper presents a 256×256 pixel smart CMOS image sensor for line based vision applications. By combining the edge-based analog processing technique with an active pixel array, a dense and fast on-chip analog image processing has been achieved. The on-chip processing unit includes (1) an analog histogram equalizer, (2) a programmable recursive Gaussian filter, (3) a spatio-temporal differentiator, and (4) a local extrema extractor. An electronic shutter is applied to the active pixel sensor array in order to adapt the exposure time as a function of global illumination. The on-chip histogram equalizer extends the image into a constant and optimal range for all the following processing operators and gives a stable and predictable precision of the analog processing. A prototype chip has been designed and fabricated in a standard 0.8-μm CMOS process with double poly and double metal, giving a pixel pitch of 20 μm and die size of 7×7 mm². A line processing time is compatible with TV line scan period. The worst case power consumption measures 40 mA at 5 V     

Arbitrated address-event representation digital image sensor

An 80×60 pixels arbitrated address-event imager has been designed and fabricated in a 0.6 μm CMOS process. The output bandwidth is allocated according to the pixel's demand. The imager has a large dynamic range: 200 dB (pixel) and 120 dB (array). The power consumption is 3.4 mW in uniform indoor light. The imager is capable of 8.3 K effective frames per second     

A computational image sensor with adaptive pixel-based integrationtime

An image sensor is proposed in which the pixel adapts its integration time to motion and light. The integration time of each pixel is shortened if motion is detected in the pixel or pixel intensity becomes saturated. The adaptivity of motion and light significantly enhances temporal resolution and dynamic range of the sensor. Because the integration time differs pixel-by-pixel, a scene containing both a bright and a dark region will be captured by pixels of shorter and longer integration times. Because the integration time adapts to motion, higher temporal resolution is obtained in a moving area and a higher signal-to-noise ratio in a static area. The control of the integration time is done on the sensor focal plane, with column parallel processing circuits integrated in CMOS image sensor. A prototype of 32×32 pixels has been fabricated by using 1-poly 2-metal CMOS 1-μm process. The fundamental functions have been verified. By the experiments, it has been verified that the sensor can reduce motion blur by adapting the integration time to motion and achieve wide dynamic range by adapting to light when the minimum integration interval is 680 μs     

A logarithmic response CMOS image sensor with on-chip calibration

CMOS image sensors with logarithmic response are attractive devices for applications where a high dynamic range is required. Their strong point is the high dynamic range. Their weak point is the sensitivity to pixel parameter variations introduced during fabrication. This gives rise to a considerable fixed pattern noise (FPN) that deteriorates the image quality unless pixel calibration is used. In the present work a technique to remove the FPN by employing on-chip calibration is introduced, where the effect of threshold voltage variations in pixels is cancelled. An image sensor based on an active pixel structure with five transistors has been designed, fabricated, and tested. The sensor consists of 525×525 pixels measuring 7.5 μm×10 μm, and is fabricated in a 0.5-μm CMOS process. The measured dynamic range is 120 dB while the FPN is 2.5% of the output signal range     

Computational sensor for visual tracking with attention

This paper presents a VLSI embodiment of an optical tracking computational sensor which focuses attention on a salient target in its field of view. Using both low-latency massive parallel processing and top-down sensory adaptation, the sensor suppresses interference front features irrelevant for the task at hand, and tracks a target of interest at speeds of up to 7000 pixels/s. The sensor locks onto the target to continuously provide control for the execution of a perceptually guided activity. The sensor prototype, a 24×24 array of cells, is built in 2-μm CMOS technology. Each cell occupies 62 μm×62 μm of silicon, and contains a photodetector and processing electronics     

Design and analysis of a 512×768 current-mediated activepixel array image sensor

Current-mediated, current-output active pixels offer the advantages of compact size and simple operation in designing large format CMOS image sensors, with performance limited by spatial fixed pattern noise. In this paper, a thorough noise analysis is made of the expected performance of a current-output pixel image sensor. This analysis is compared with experimental results from a 512×768 array imager fabricated in a 0.7 μm process, and the effectiveness of basic error correction techniques are explored. The goal of this study was to determine the performance limits of this device and to gain insight into the design issues needed to develop a high-quality current-output imager     

Space-variant nonorthogonal structure CMOS image sensor design

A CMOS log-polar image sensor has been designed and fabricated. As a result, a systematic approach has been proposed to design space-variant sensors and layouts. The pixels in this sensor are distributed in a polar fashion; the image plane consists of concentric rings containing the elementary sensing cells. Such a structure, where polygons use any space orientation, does not match very well with current design tools and CMOS fabrication processes. An approach to design nonorthogonal repetitive structures using standard fabrication processes and computer-aided design (CAD) tools is presented. The result of this work is an image sensor, with log-polar structure, suitable for image processing since the log-polar mapping has interesting mathematical and image data reduction properties     

基于FPGA的大面阵CMOS相机高速率电子学系统设计

目前深空遥感探测多采用CCD作为高分辨率相机的传感器,相较于CCD,面阵CMOS驱动更简单、功耗更低、抗辐射能力更强,是深空遥感探测目前的发展趋势。为此,本文基于CMOSIS公司生产的型号为CMV20000,图像分辨率为5 120×3 840的CMOS探测器,设计完成了一个大面阵CMOS高分辨率相机,图像分辨率为5 120×3 840。详细阐述了以FPGA为核心的电子学系统的整体结构,结合CMV20000的工作模式和时序电路,实现了高分辨图像的高速传输以及数据校正。试验结果表明,设计的相机系统方案合理,解决了CMV20000数据无法对齐的数据校正问题,系统运行稳定可靠,安装光学系统后能够获取高质量图像。     

A single-chip fingerprint sensor and identifier

A chip architecture that integrates a fingerprint sensor and an identifier in a single chip is proposed. The fingerprint identifier is formed by an array of pixels, and each pixel contains a sensing element and a processing element. The sensing element senses capacitances formed by a finger surface to capture a fingerprint image. An identification is performed by the pixel-parallel processing of the pixels. The sensing element is built above the processing element in each pixel. The chip architecture realizes a wide-area sensor without a large increase of chip size and ensures high sensor sensitivity while maintaining a high image density. The sensing element is covered with a hard film to prevent physical and chemical degradation and surrounded by a ground wall to shield it. The wall is also exposed on the chip surface to protect against damage by electrostatic discharges from the finger contacting the chip. A 15×15 mm² single-chip fingerprint sensor/identifier LSI was fabricated using 0.5-μm standard CMOS with the sensor process. The sensor area is 10.1×13.5 mm². The sensing and identification time is 102 ms with power consumption of 8.8 mW at 3.3 V. Five hundred tests confirmed a stranger-rejection rate of the chip of more than 99% and a user-rejection rate of less than 1%     

Vertically integrated sensors for advanced imaging applications

A thin film on ASIC (TFA) image sensor is fabricated depositing an amorphous silicon thin-film detector onto a CMOS ASIC. With regards to advanced imaging systems, TFA provides enhanced performance and more flexibility than conventional technologies. Extensive on-chip signal processing is feasible, as well as small pixels for high resolution imagers. Two new TFA imager prototypes have recently been fabricated. High-resolution image sensor (HIRISE II) with 1024×128 pixels is an active pixel sensor suited for digital photography. Local autoadaptiver sensor (LARS II) with 368×256 pixels splits the illumination information into two signals, thereby providing a dynamic range of more than 120 dB, as required by automotive applications. Both prototypes include correlated double sampling and double delta sampling for efficient suppression of fixed pattern noise     

Random addressable 2048×2048 active pixel image sensor

In this paper, we discuss the design, design issues, fabrication, and performance of a 2048×2048 active pixel image sensor in a 0.5-μm standard CMOS process. Each pixel, 7.5×7.5 μm² , consists of three transistors and a photo diode, resulting in a 12-million transistor chip with a die size of 16.3×16.5 mm. The pixel has a nonintegrating direct readout architecture, with a logarithmic light-to-voltage conversion. This allows the array to be fully random accessible, both in space and time. The sensor has eight analog outputs, each with a pixel rate of 4.5 MHz, which implies a maximum frame rate of eight full frames per second. Sub-sampling or windowing makes higher frame rates possible. The yield of the sensor is high if one accepts a small number of bad pixels     

A small pixel CMD image sensor

A charge modulation device (CMD) imager with pixel dimensions of 7.3 μm(H)×7.6 μm(V) was designed, fabricated, and examined. These pixel dimensions are suitable for an HDTV imager with a 1-in image format. The optical aperture ratio is 34%. The effective number of pixels in the imager is 660 horizontal and 492 vertical. The saturation signal current is 17 μA/pixel at an exposure of 1 lx-s with good linearity of photoconversion characteristics. The peak of its spectral response occurs at a wavelength of 575 nm. The blooming suppression ratio of the CMD was measured to be -122 dB. The sensor produces a high-quality image with no degradation in spatial resolution and no image lag. These features show that the CMD imager is eminently suitable for a further high-resolution imager sensor     

CMOS active pixel image sensors for highly integrated imagingsystems

A family of CMOS-based active pixel image sensors (APSs) that are inherently compatible with the integration of on-chip signal processing circuitry is reported. The image sensors were fabricated using commercially available 2-μm CMOS processes and both p-well and n-well implementations were explored. The arrays feature random access, 5-V operation and transistor-transistor logic (TTL) compatible control signals. Methods of on-chip suppression of fixed pattern noise to less than 0.1% saturation are demonstrated. The baseline design achieved a pixel size of 40 μm×40 μm with 26% fill-factor. Array sizes of 28×28 elements and 128×128 elements have been fabricated and characterized. Typical output conversion gain is 3.7 μV/e^- for the p-well devices and 6.5 μV/e^- for the n-well devices. Input referred read noise of 28 e^- rms corresponding to a dynamic range of 76 dB was achieved. Characterization of various photogate pixel designs and a photodiode design is reported. Photoresponse variations for different pixel designs are discussed     

A photodiode cell for applications to position and motionestimation sensors

An optical cell has been designed and fabricated using standard digital 1.6 μm CMOS technology. It has been designed for applications to sensors where the image acquisition time of fast moving objects or documents is of primary importance. The cell contains a photodiode working in storage mode and a shielded MOS capacitor acting as analog frame buffer. A chip prototype containing 64 linear arrays of 64 cells whose size is 36×36 μm² has been tested and measurements have proved the functionality down to microsecond-range of exposure times. By virtue of the proposed read-out technique, the sensor architecture provides simultaneous image acquisition of irregular moving objects allowing precise detection of position and motion     

A 1/4-inch 330 K square pixel progressive scan CMOS active pixelimage sensor

In this paper, three pixel structures have been studied as candidates to realize high density CMOS active pixel sensors. A novel cell structure, the “I-shaped” cell, in which the active regions are formed along a straight line, has been proposed for high-packing density devices. The “I-shaped” cells can realize minimum cell area of 16F², 14F², and 14F ² (F: design rule) for three-transistor-type, two-transistor-type, and one-transistor-type pixels, respectively. A 1/4-inch format progressive scan CMOS active pixel sensor with 640 (H)×480 (V) pixels has been fabricated using a 0.6-μm CMOS process. The sensor operates with 5.0 V single power supply, and power consumption is below 30 mW     

Design and fabrication of AlGaInP LED array with integrated GaAsdecode circuits

A two-dimensional (2-D) AlGaInP light-emitting diode (LED) array with monolithic integration of one-to-four GaAs MESFET decode circuits has been developed as an image source for portable virtual displays. The epitaxial layers of AlGaInP LEDs with light emission at a wavelength of 605 nm were grown on a semi-insulating GaAs substrate by organometallic vapor phase epitaxy. LED arrays consisting of 240 columns and 144 rows for a total of 34560 pixels were then fabricated on such epitaxial wafers. One-to-four GaAs MESFET decode circuits consisting of eight MESFET's for each decode circuit and a total of 768 MESFET's for a 34 K decode array were fabricated on the semi-insulating GaAs substrate with removal of LED epitaxial layers around the periphery of the LED array. LED arrays with the integrated decode circuits provide a great reduction in I/O terminals. The I/O count of the demonstrated 34 K decode LED array is 104, which is much less than 384 for a comparable array without the integrated decode circuits. The pixel pitch of the LED array is 20 μm and each LED pixel has 10×10 μm² emitting area. The output power of LED pixel is 50 nW at an operation current of 50 μA. The address voltages used to activate the column decode circuits are 3 V for high and -3 V for low, while the address voltages used to activate the row decode circuits are 0 V for high and -3 V for low. The operating voltage of the decode LED array ranges from 3 to 5 V, and the total power dissipation of the decode LED array is less than 16 mW