Electronic structure of Co islands grown on the √3 × √3-Ag/Ge(111) surface

By means of room temperature scanning tunneling spectroscopy (RT STS), we have studied the electronic structure of two different Ag/Ge(111) phases as well as Co islands grown on the √3 × √3-Ag/Ge (111) forming either √13 × √13 or 2 × 2 patterns. The spectrum obtained from 4 × 4-Ag/Ge(111) structure shows the existence of a shoulder at 0.7 V which is also present in the electronic structure of the Ge(111)-c2 × 8 and indicates donation of Ge electrons to electronic states of the Ag-driven phase. However, this fact is not supported by the electronic spectrum taken from the √3 × √3-Ag/Ge (111). The complexity of the Co-√13 × √13 islands bonding with the substrate is mirrored by a large number of peaks in their electronic spectra. The spectra obtained from the Co-2 × 2 islands which had grown on the step differ from those taken from Co-2 × 2 islands located along the edge of the terrace by a number of peaks at negative sample bias. This discrepancy is elucidated in terms of dissimilarities of Co-substrate interaction accompanying Co islands growth on different areas of the stepped surface.     

Fabrication of high quality Ge virtual substrates by selective epitaxial growth in shallow trench isolated Si (001) trenches

To further boost the CMOS device performance, Ge has been successfully integrated on shallow trench isolated Si substrates for pMOSFET fabrication. However, the high threading dislocation densities (TDDs) in epitaxial Ge layers on Si cause mobility degradation and increase in junction leakage. In this work, we studied the fabrication of Ge virtual substrates with low TDDs by Ge selective growth and high temperature anneal followed by chemical mechanical polishing (CMP). With this approach, the TDDs in both submicron and wider trenches were simultaneously reduced below 1 × 10⁷ cm^− 2 for 300 nm thick Ge layers. The resulting surface root-mean-square (RMS) roughness is about 0.15 nm. This fabrication scheme provides high quality Ge virtual substrates for pMOSFET devices as well as for III-V selective epitaxial growth in nMOSFET areas. A confined dislocation network was observed at about 50 nm above the Ge/Si interface. This dislocation network was generated as a result of effective threading dislocation glide and annihilation. The separation between the confined threading dislocations was found in the order of 100 nm.     

Removal of stacking faults in Ge grown on Si through nanoscale openings in chemical SiO2

Nucleation and eventual coalescence of Ge islands, grown out of 5 to 7 nm diameter openings in chemical SiO₂ template and epitaxially registered to the underlying Si substrate, have been shown to generate a low density of threading dislocations (?10⁶ cm^− 2). This result compares favorably to a threading dislocation density exceeding 10⁸ cm^− 2 in Ge films grown directly on Si. However, the coalesced Ge film contains a relatively high density of stacking faults (5 × 10⁷ cm^− 2), and subsequent growth of GaAs leads to an adverse root-mean-square roughness of 36 nm and a reduced photoluminescence intensity at 20% compared to GaAs grown on Ge or GaAs substrates. Herein, we find that annealing the Ge islands at 1073 K for 30 min before their coalescence into a contiguous film completely removes the stacking faults. However, the anneal step undesirably desorbs any SiO₂ not covered by existing Ge islands. Further Ge growth results in a threading dislocation density of 5 × 10⁷ cm^− 2, but without any stacking faults. Threading dislocations are believed to result from the later Ge growth on the newly exposed Si where the SiO₂ has desorbed from areas uncovered by Ge islands. The morphology and photoluminescence intensity of GaAs grown on the annealed Ge is comparable to films grown on GaAs or Ge substrates. Despite this improvement, the GaAs films grown on the annealed Ge/Si exhibit a threading dislocation density of 2 × 10⁷ cm^− 2 and a minority carrier lifetime of 67 ps compared to 4 to 5 ns for GaAs on Ge or GaAs substrates. A second oxidation step after the high temperature anneal of the Ge islands is proposed to reconstitute the SiO₂ template and subsequently improve the quality of Ge film.     

Molecular beam epitaxy grown GeSn p-i-n photodetectors integrated on Si

GeSn p-i-n photodetectors with a low Sn mole fraction made by molecular beam epitaxy on Si substrates show higher optical responsivities for wavelength λ > 1400 nm compared with p-i-n photodetectors made from pure Ge. The Sn incorporation in Ge is done by a low temperature growth step in order to minimize Sn segregation. The Sn incorporation and the alloy content are investigated by μ-Raman spectroscopy and calibrated Secondary Ion Mass Spectrometry. The photodetectors are manufactured with sharp doping transitions and are realized as double mesa structures with diameters from 1.5 μm up to 80 μm. The optical measurements are carried out with a broadband super continuum laser from λ = 1200 nm up to λ = 1700 nm. At a wavelength of λ = 1550 nm the optical responsivity of these vertical GeSn diodes is 0.1 A/W. In comparison with a pure Ge detector of the same geometrical dimensions the optical responsivity is increased by factor of three as a result of Sn caused band gap reduction.     

Manifestations of strain-relaxation in the structure of nano-sized Co-2 × 2 islands grown on Ag/Ge(111)-√3 × √3 surface

We have examined strain-relaxation of Co-2 × 2 islands grown on the Ag/Ge(111)-√3 × √3 surface by analyzing scanning tunneling microscopy images. We have found that the Co-2 × 2 islands commonly adopt a more compact arrangement as compared to that of the Ge(111) substrate, however they differ in a degree of an atomic compactness. We have not found a distinct relation between strain-relaxation and the island height. Three groups of islands have been identified upon analyzing a correspondence between strain-relaxation and the island size: (i) small islands (not bigger than 80 nm²) with a high atomic compactness, displaying fixed inter-row distances, (ii) small islands with unfixed distances between atomic rows, and (iii) big islands (bigger than 80 nm²) with fixed inter-row distances, but with a less compact atomic arrangement compared to that of the first two groups. We propose a model to account for the relation between the relaxation and the island size.     

Nanoscale interfacial engineering to grow Ge on Si as virtual substrates and subsequent integration of GaAs

We have demonstrated the scalability of a process previously dubbed as Ge “touchdown” on Si to substantially reduce threading dislocations below 10⁷/cm² in a Ge film grown on a 2 inch-diameter chemically oxidized Si substrate. This study also elucidates the overall mechanism of the touchdown process. The 1.4 nm thick chemical oxide is first formed by immersing Si substrates in a solution of H₂O₂ and H₂SO₄. Subsequent exposure to Ge flux creates 3 to 7 nm-diameter voids in the oxide at a density greater than 10¹¹/cm². Comparison of data taken from many previous studies and ours shows an exponential dependence between oxide thickness and inverse temperature of void formation. Additionally, exposure to a Ge or Si atom flux decreases the temperature at which voids begin to form in the oxide. These results strongly suggest that Ge actively participates in the reaction with SiO₂ in the void formation process. Once voids are created in the oxide under a Ge flux, Ge islands selectively nucleate within the void openings on the newly exposed Si. Island nucleation and growth then compete with the void growth reaction. At substrate temperatures between 823 and 1053 K, nanometer size Ge islands that nucleate within the voids continue to grow and coalesce into a continuous film over the remaining oxide. Coalescence of the Ge islands is believed to result in the creation of stacking faults in the Ge film at a density of 5 × 10⁷/cm². Additionally, coalescence results in films of 3 µm thickness having a root-mean-square roughness of 8 to 10 nm. We have found that polishing the films with dilute H₂O₂ results in roughness values below 0.5 nm. However, stacking faults originating at the Ge-SiO₂ interface and terminating at the Ge surface are polished at a slightly reduced rate, and show up as 1 to 2 nm raised lines on the polished Ge surface. These lines are then transferred into the subsequent growth morphology of GaAs deposited by metal-organic chemical vapor deposition. Room temperature photoluminescence shows that films of GaAs grown on Ge-on-oxidized Si have an intensity that is 20 to 25% compared to the intensity from GaAs grown on commercial Ge or GaAs substrates. Cathodoluminescence shows that nonradiative defects occur in the GaAs that spatially correspond to the stacking faults terminating at the Ge surface. The exact nature of these nonradiative defects in the GaAs is unknown, however, GaAs grown on annealed samples of Ge-on-oxidized Si, whereby annealing removes the stacking faults, have photoluminescence intensity that is comparable to GaAs grown on a GaAs substrate.     

Hot wire CVD deposition of nanocrystalline silicon solar cells on rough substrates

In silicon thin film solar cell technology, frequently rough or textured substrates are used to scatter the light and enhance its absorption. The important issue of the influence of substrate roughness on silicon nanocrystal growth has been investigated through a series of nc-Si:H single junction p-i-n solar cells containing i-layers deposited with Hot-wire CVD. It is shown that silicon grown on the surface of an unoptimized rough substrate contains structural defects, which deteriorate solar cell performance. By introducing parameter v, voids/substrate area ratio, we could define a criterion for the morphology of light trapping substrates for thin film silicon solar cells: a preferred substrate should have a v value of less than around 1 × 10^- 6, correlated to a substrate surface rms value of lower than around 50 nm. Our Ag/ZnO substrates with rms roughness less than this value typically do not contain microvalleys with opening angles smaller than ~ 110°, resulting in solar cells with improved output performance. We suggest a void-formation model based on selective etching of strained Si-Si atoms due to the collision of growing silicon film surface near the valleys of the substrate.     

Optical sensor with transparent conductive oxides electrodes for microposition detection applications

This paper presents an optical sensor structure for microposition detection application using transparent electrodes of indium doped ZnO (IZO). The optical microsensor consists of two linear arrays of metal - semiconductor - metal (MSM) silicon photodetectors with IZO transparent electrodes integrated with a polymer optical waveguide.IZO layers with a thickness of 460-580 nm have been deposited by dc magnetron sputtering technique on silicon epitaxial wafers of 30-50 Ω cm resistivity and a thickness of 23 µm. Due to their high optical transmittance (> 90%) over the 0.4-0.9 µm spectral range, these layers contributed to an increased responsivity of the MSM photodiode structure of about 0.34 A/W, thus improving the optical position microsensor sensitivity.     

High sensitivity and wide bandwidth image sensor using CuIn1 − xGaxSe2 thin films

We have fabricated a novel image sensor using Cu(In,Ga)Se₂ (CIGS). A combined process of dry etching using HBr and Ar gasses and wet etching using dilute HCl solution was developed as isolation process of CIGS photodiode deposited at 400 °C. Etchant residues of the dry etching, which consist of Cu complex, were almost completely cleaned using the wet etching process and favorable vertical side wall of CIGS films was obtained without mechanical damages. As a result, high performance image sensors with low leakage current of ~ 10^− 8 A/cm² and wide wavelength range up to ~ 1240 nm were achieved. The developed image sensor consisted of 352 × 288 pixels with 10 µm × 10 µm pixel sizes, was able to capture clear images of night scenes.     

High quality Ge epitaxial layers on Si by ultrahigh vacuum chemical vapor deposition

Flat, relaxed Ge epitaxial layers with low threading dislocation density (TDD) of 1.94 × 10⁶ cm^− 2 were grown on Si(001) by ultrahigh vacuum chemical vapor deposition. High temperature Ge growth at 500 °C on 45 nm low temperature (LT) Ge buffer layer grown at 300 °C ensured the growth of a flat surface with RMS roughness of 1 nm; however, the growth at 650 °C resulted in rough intermixed SiGe layer irrespective of the use of low temperature Ge buffer layer due to the roughening of LT Ge buffer layer during the temperature ramp and subsequent severe surface diffusion at high temperatures. Two-dimensional Ge layer grown at LT was very crucial in achieving low TDD Ge epitaxial film suitable for device applications.     

Surface structure of Au/InSb(0 0 1) system investigated with scanning force microscopy

Dynamic force microscopy and Kelvin probe force microscopy (KPFM) have been used to study 0.2 ML Au deposited on clean c(8×2) InSb(0 0 1) surface. Rectangular islands of typical size of 9 nm across have been observed. Upon annealing at 650 K these islands preserve their initial shape. KPFM has shown that the islands are made of material chemically different from that of the surrounding substrate surface. However, the change of LEED pattern to c(4×4) strongly suggests conversion of substrate surface between the islands from In-rich to Sb-rich probably due to alloying of surface indium with gold in the islands.     

Textured surface boron-doped ZnO transparent conductive oxides on polyethylene terephthalate substrates for Si-based thin film solar cells

Textured surface boron-doped zinc oxide (ZnO:B) thin films were directly grown via low pressure metal organic chemical vapor deposition (LP-MOCVD) on polyethylene terephthalate (PET) flexible substrates at low temperatures and high-efficiency flexible polymer silicon (Si) based thin film solar cells were obtained. High purity diethylzinc and water vapors were used as source materials, and diborane was used as an n-type dopant gas. P-i-n silicon layers were fabricated at ~ 398 K by plasma enhanced chemical vapor deposition. These textured surface ZnO:B thin films on PET substrates (PET/ZnO:B) exhibit rough pyramid-like morphology with high transparencies (T ~ 80%) and excellent electrical properties (Rs ~ 10 Ω at d ~ 1500 nm). Finally, the PET/ZnO:B thin films were applied in flexible p-i-n type silicon thin film solar cells (device structure: PET/ZnO:B/p-i-n a-Si:H/Al) with a high conversion efficiency of 6.32% (short-circuit current density J_SC = 10.62 mA/cm², open-circuit voltage V_OC = 0.93 V and fill factor = 64%).     

Growth of heavily doped monocrystalline and polycrystalline SiGe-based quantum dot superlattices

Various SiGe-based Quantum Dot Superlattices (QDSLs) were grown using an industrial Chemical Vapor Deposition tool with the intent to develop efficient thermoelectric thin films at a large scale. We report first on the growth of monocrystalline SiGe-based QDSLs. We were able to control the SiGe spacer width and the sizes and densities of Ge dots. A vertical ordering behavior was observed for large dot structures, but not for those with the smallest dots (30-70 nm wide, 3 nm high). In situ B doping operated during growth led to hole densities of 5 × 10¹⁹ to 1 × 10²⁰ cm^− 3. We also report on the growth of polycrystalline SiGe-based QDSLs with the same equipment. We show in particular that vertically aligned Ge dots were formed in a similar way as in monocrystalline structures despite the presence of stacking faults and grain boundaries. A heavy p doping was also obtained on some of these structures.     

The effects of low temperature buffer layer on the growth of pure Ge on Si(001)

We investigated the effects of low temperature (LT) Ge buffer layers on the two-step Ge growth by varying the thickness of buffer layers. Whereas the two-step Ge layers using thin (< 40 nm) Ge buffer layers were roughened due to the formation of SiGe alloy, pure and flat Ge layers were grown by using thick (> 50 nm) LT Ge buffer layers. The lowest threading dislocation density of 1.2 × 10⁶ cm⁻² was obtained when 80-nm-thick LT Ge buffer layer was used. We concluded that the minimum thickness of buffer layer was required to grow uniform two-step Ge layers on Si and its quality was subject to the thickness of buffer layer.     

Sb mediated formation of Ge/Si quantum dots: Growth and properties

The phenomenon of surfactant (Sb) mediated formation of Ge/Si(100) islands (quantum dots) by means of molecular beam epitaxy is discussed. The limited diffusivity of Si and Ge adatoms caused by the Sb layer leads to a reduction of the size of Ge islands, the increase in the island density, and the sharpening of the interfaces of Ge islands. Thereby, a thin Sb layer is considered to be a powerful tool that provides more freedom in designing Ge quantum dot features. Ge quantum dots, grown via a thin Sb layer and embedded coherently in a Si p-n junction, are revealed to be the origin of the intense photo- and electroluminescence in the spectral range of about 1.5 μm at room temperature.     

Experiments on high excitation density, quenching, and radiative kinetics in CsI:Tl scintillator

Information on quenching as a function of electron-hole density through the range of 10¹⁹ to 2×10²⁰ e-h/cm³ typically deposited towards the end of an electron track has been acquired using 0.5 ps pulses of 5.9 eV light to excite in the band-to-band or high-exciton region of CsI and CsI:Tl. A streak camera records partially quenched luminescence from self-trapped excitons (STE) and excited activators (Tl^+?). Both the Tl^+? and STE luminescence exhibit decreasing light yield versus excitation density N_max, but it is only the 302 nm STE luminescence that exhibits decay time quenching dependent on N_max. Fitting the STE decay time data to a model of dipole-dipole quenching yields the time-dependent bimolecular rate constant for quenching of STEs (and Tl^+? light yield) in CsI at room temperature: k₂(t)=2.4×10⁻¹⁵ cm³ s^−1/2 (t^−1/2).     

One-dimensional optical materials of microfibers by electrospinning

Optical microfibers of PMMA were fabricated by electrospinning. The fibers with the diameter ranging from 300 nm to 1000 nm were obtained by electrospinning the solutions such as PMMA/DMF, PMMA/DMF/formic acid and PMMA/formic acid. The morphology and the diameter of the fibers were analyzed by scanning electron microscopy (SEM). Results showed that the sidewalls of the fibers were smooth and the diameters were uniform. The light with the wavelength of 488 nm, 532 nm and 650 nm could be launched into the fibers and guide along them. The simulation and experimental results showed that the fibers exhibited excellent optical properties. This method provided an effective and convenient way to fabricate highly uniform micro/nano scale optical waveguide neither using expensive equipments nor involving complex procedures.     

Low temperature growth of single crystalline germanium nanowires

Ge nanowires have been prepared at a low temperature by a simple hydrothermal deposition process using Ge and GeO₂ powders as the starting materials. These as-prepared Ge nanowires are single crystalline with the diameter ranging from 150 nm to 600 nm and length of several dozens of micrometers. The photoluminescence spectrum under excitation at 330 nm shows a strong blue light emission at 441 nm. The results of the pressure and GeO₂ content dependences on the formation and growth of Ge nanowires show that the hydrothermal pressure and GeO₂ content play an essential role on the formation and growth of Ge nanowires under hydrothermal deposition conditions. The growth of Ge nanowires is proposed as a solid state growth mechanism.     

High performance infra-red detectors based on Si/SiGe multilayers quantum structure

Recently, single crystalline (Sc) Si/SiGe multi quantum structure has been recognized as a new low-cost thermistor material for IR detection. Higher signal-to-noise (SNR) ratio and temperature coefficient of resistance (TCR) than existing thermistor materials have converted it to a candidate for infrared (IR) detection in night vision applications. In this study, the effects of Ge content, C doping and the Ni silicidation of the contacts on the performance of SiGe/Si thermistor material have been investigated. Finally, an uncooled thermistor material with TCR of −4.5%/K for 100 μm × 100 μm pixel sizes and low noise constant (K_1/f) value of 4.4 × 10⁻¹⁵ is presented. The outstanding performance of the devices is due to Ni silicide contacts, smooth interfaces, and high quality multi quantum wells (MQWs) containing high Ge content.     

Thin film photodiodes fabricated by electrostatic self-assembly of aqueous colloidal quantum dots

We demonstrate a thin film photodiode structure consisting of multi layers of colloidal quantum dots (QDs) which has application in photovoltaics and photodetection. The CdTe QDs with either positively or negatively charged capping ligands are self-assembled layer-by-layer on an indium tin oxide (ITO) substrate by electrostatic attraction in aqueous solution. A photolithographically patterned photoresist window defines the device active area and an evaporated aluminum (Al) thin film serves as the top electrode. The built-in electric field due to the work function difference between Al and ITO separates photo-excited electron-hole pairs and generates photocurrent. Since the ligands used for QD synthesis are short (less than 0.5 nm), no additional steps of ligand exchange or annealing is needed for enhancing the thin film photoconductivity. Thiol passivation and self-assembly in an inert environment help reduce surface traps, leading to less fermi-level pinning which also improves the device performance.