一种基于FPGA的压控晶振同步频率控制系统

晶振时钟信号存在长期稳定度差和累积误差的问题。本文是利用GPs提供的1pps秒脉冲信号,在FPGA的基础上利用干扰秒脉冲信号消除和偏差频率平均运算等方法,减少外围电路,既消减了GPS时钟信号的随机干扰误差,又消除了本地晶振时钟信号的累计误差,从而控制本地压控晶振输出频率,提高晶振的长期稳定性。     

数字时钟设计

数字钟是采用数字电路实现对“时”、“分”、“秒”数字显示的计时装置,由振荡器、分频器、计数器、译码器、数码显示器等几部分组成。其本质是一个对标准频率（IHz）进行计数的计数电路。振荡器产生的时钟信号经分频器形成秒脉冲信号,然后秒脉冲信号输入计数器进行计数,并把累计结果以“时”、“分”、“秒”的数字显示出来。为了精确计时,该电路还有校正功能。同时计时过程要具有报时功能,当时间到达整点前,蜂鸣器便开始报时。在此次设计中,电路具有显示时间、实现对时间的调整开耐艮时的功能。     

流量标准装置前端脉冲信号处理方法

针对流量标准装置前端脉冲信号处理经常遇到的两种问题提出了解决方案。针对流量计输出的脉冲信号幅度随厂家、原理而不同的特征,设计了可变比较门限的脉冲整形电路,相比固定比较值的方法大大提高了装置对不同流量计脉冲信号的适应性;针对脉冲输出类流量计极易受干扰的情况,设计了电容滤波与脉冲宽度滤波相结合的形式,大大提高了装置的抗干扰能力。最后通过实验验证:整体处理电路可在(1~12)V范围内任意更改比较门限,对4KHz以上脉冲信号可完全滤波。     

基于采样原理的直流电能表校准装置

介绍了一套自行研制的直流电能表校准装置,对输出的直流功率信号中的电压、电流分别变换后进行采样并卷积,得到一段时间内的平均功率标准值,采用相同的外触发信号同步采样测量被检直流电能表的脉冲输出,得到与被检直流电能表输出相关的频率值,并用LabVIEW编写了自动测试计算软件得到测量结果。该方法利用3458A数字多用表直流信号采样准确度高的特性,有效地克服了测量信号稳定性、测量噪声和分流器发热不稳对测量结果的影响,为建立高准确度的标准直流电能表校准装置提供了一种技术解决方案,为直流电能量值溯源提供了技术保障。     

超高清数字视频基带信号抖动测量技术研究

针对数字超高清视频基带信号的抖动参数测量开展研究,设计了高速串行数字接口(SDI)信号的测量方法,采用改进后的双狄拉克模型来测量信号中的抖动,并解调SDI中的时钟信号作为测量时间基准。该方法可以准确地分析SDI信号中不同的抖动分量,采用时域测量方法,将信号抖动测量溯源到时域脉冲波形参数。通过实验验证了该方法的可行性,测量结果表明,该方法比直接频谱测量法具有更高的测量精度。     

基于GPS的目标飞行时间异地高精度测量技术

针对远程目标异地作用的特性以及异地时间测量对时间统一标准的严格要求,提出了一种基于GPS的高精度异地目标光信号时间测量系统.该系统将GPS授时与本地温补晶振时钟结合起来,利用GPS授时秒脉冲1 pps进行时间同步,由本地时钟结合GPS的标准时间测量出飞行目标启动和停止的精确时间及时间间隔;同时设计了高精度的授时方案,对GPS秒脉冲进行监控和补偿,有效提高了系统的可靠性.实验表明,该系统测量在400 s内所产生的累积测量误差小于300μs,等效精度达到7.5×10-7.     

外触发方式下相机同步抓拍系统研究

脉冲激光检测系统中,由于激光器发射的激光脉冲频率低,且脉宽仅为纳秒级,所以在远距离测试时,很难控制数字CCD(Charge Coupled Device)相机的精准曝光时刻.为了克服触发信号与激光脉冲信号不同步的问题,本文提出了"光触发,电同步"与"超前预测"相结合的方法.以BD2(BeiDou2 Navigation Satellite System)/GPS(Global Positioning System)模块提供的精确秒脉冲pps(pulse per second)信号作为时钟基准,同时结合FPGA(Field Programmable Gate Array)高速的特点,实现数字CCD相机对激光光斑图像的准确捕获,控制数字CCD相机的最佳积分时间.实验结果表明,该方法不仅提高了数字CCD相机的抓拍精度,也提高了图像的信噪比.     

电磁流量计仪表系数的误差分析

电磁流量计是一种根据法拉第电磁感应定律来测量管内导电介质体积流量的感应式仪表。目前多数流量计都设计有提供脉冲信号的输出,本文就使用静态质量法水流量标准装置对使用脉冲信号输出的电磁流量计进行检定中,选取仪表系数K进行讨论并对其误差来源进行分析,评定其测量值的不确定度。     

气体脉冲压力的激光干涉法测量

对气体动态压力的非接触测量和溯源方法进行了研究。研制了基于激光干涉法测量气体脉冲压力的实验装置,通过光程与压力关系计算分析出气体脉冲压力的幅值和脉宽。建立了动态压力测量模型,并对测量不确定度进行了分析。开展了气体脉冲压力激光干涉测量实验,使用动态压力传感器和激光器进行同步测量,激光干涉法测量结果偏差较小,验证了装置测量的准确性。结果表明：本装置产生的脉冲压力信号稳定可靠,光学测量信号准确度高,具有实时性、非接触、可溯源等优点,可实现气体脉冲压力的测量,装置测量结果的相对标准偏差小于0.8%,测量结果的不确定度小于2%(k=2)。     

便携式光电转速表的硬件选型

介绍一种用于高校实训中转速测量的红外光电转速测量装置——便携式光电转速表,对其硬件选择分析,以红外光作为光源,使光电输出的电信号经过前置放大、整形处理电路及锁相倍频后,由单片机进行计算处理。单片机采用测量脉冲周期和测量脉冲信号个数相结合的方法计算转速,既能保证检测的实时性,测量精度也高,转速测量值可以通过五位LED显示出结果。     

Digital Frequency Multiplier for Spectrum Measurement of Periodic Signals

Frequency multipliers find applications in the Fourier and Walsh spectrum measurements of periodic signals. Earlier digital frequency multipliers use two counters: 1) An upcounter which is partitioned into a fractional counter of kbits in cascade with an integral counter. This determines the period of the input signal by the number of clock pulses that are accumulated in a period of the signal. 2) A downcounter which is next fed from the same clock, and which is periodically preset to the contents of the integral counter whenever the downcounter reaches zero. In this process an error is introduced in the output frequency because the fractional counter contents are ignored in the frequency multiplication phase. To minimize this error, a high clock frequency is required so that the fractional count is small compared with the integral count. The maximum output pulse frequency is limited by the speed of the counters used. A new method is described which also uses the contents of the fractional counter. The clock frequency is reduced substantially and the maximum output pulse frequency is limited by the settling time of a D/A converter: If the settling time is 200 ns, the maximum output frequency is ten times that of earlier methods.     

Capacity upgrade in short-reach optical fibre networks: simultaneous 4-PAM 20 Gbps data and polarization-modulated PPS clock signal using a single VCSEL carrier

In this work, a four-level pulse amplitude modulation (4-PAM) format with a polarization-modulated pulse per second (PPS) clock signal using a single vertical cavity surface emitting laser (VCSEL) carrier is for the first time experimentally demonstrated. We propose uncomplex alternative technique for increasing capacity and flexibility in short-reach optical communication links through multi-signal modulation onto a single VCSEL carrier. A 20 Gbps 4-PAM data signal is directly modulated onto a single mode 10 GHz bandwidth VCSEL carrier at 1310 nm, therefore, doubling the network bit rate. Carrier spectral efficiency is further maximized by exploiting the inherent orthogonal polarization switching of the VCSEL carrier with changing bias in transmission of a PPS clock signal. We, therefore, simultaneously transmit a 20 Gbps 4-PAM data signal and a polarization-based PPS clock signal using a single VCSEL carrier. It is the first time a signal VCSEL carrier is reported to simultaneously transmit a directly modulated 20 Gbps 4-PAM data signal and a polarization-based PPS clock signal. We further demonstrate on the design of a software-defined digital signal processing (DSP)-assisted receiver as an alternative to costly receiver hardware. Experimental results show that a 3.21 km fibre transmission with simultaneous 20 Gbps 4-PAM data signal and polarization-based PPS clock signal introduced a penalty of 3.76 dB. The contribution of polarization-based PPS clock signal to this penalty was found out to be 0.41 dB. Simultaneous distribution of data and timing clock signals over shared network infrastructure significantly increases the aggregated data rate at different optical network units (ONUs), without costly investment.     

Optimal Synchronization of Local Clocks by GPS 1PPS Signals Using Predictive FIR Filters

In this paper, we discuss optimal synchronization of local clocks using Global Positioning System (GPS) one-pulse-per-second (1PPS) timing signals. To eliminate sawtooth errors that are peculiar to the 1PPS signals and optimally steer the clock errors each $M$ seconds, we propose the use of a ramp-predictive finite-impulse-response (FIR) filter that is known to be optimal for clock models on large averaging horizons. A low-pass filter is used to smooth the hold filter output between the optimally predicted points. A GPS-locked crystal clock has been investigated in detail in terms of the time interval error, Allan deviation, and precision time protocol (PTP) variance. A high-efficiency implementation of the proposed synchronization algorithm is experimentally demonstrated.      

All-optical wavelength reuse with simultaneous upstream data and PPS timing signal transfer for flexible optical access networks

All-optical wavelength reuse is a viable approach for realization of low cost colourless ONUs. We experimentally demonstrate a novel all-optical wavelength reuse technique with simultaneous upstream data and pulse-per-second signal transfer, exploiting EDFA gain saturation with a holding beam. A DFB laser is modulated with 8.5 Gbps data and transmitted downstream over 24.7 km fibre. A saturated EDFA located at the ONU is adopted to reduce the extinction ratio of the downstream data from 6.2 dB to 839.1 mdB. This allows for data rewrite and wavelength reuse for upstream transmission. Receiver sensitivities of ?20.19 dBm and ?19.60 dBm are achieved at back-to-back analysis and 24.7 km downstream link respectively. A holding beam is further exploited to attain simultaneous carrier reuse and PPS clock upstream transfer. PPS jitter stability of 1.01 × 10^-08 ns and 6.64 × 10^-08 ns are attained respectively. This work offers a convenient all-optical wavelength reuse solutions for optical access networks.     

A Digital Instantaneous Frequency Meter

A basic instrument is described which produces a parallel digital output proportional to frequency once per cycle, i.e., instantaneously. This is achieved by means of a reciprocal time generator which continuously generates digitally the reciprocal of the time elapsed between successive incoming pulses and the output of which is sampled and held at the end of each cycle. The meter is a 12-bit instrument having an accuracy of ±1 count plus clock stability. An analog output and a digital readout can be readily obtained. The range of the instrument is from zero to fc × 2-12 Hz, where fc is the clock frequency in hertz. Thus the range can be varied by appropriate adjustment of fc. An additional circuit to provide an analog output proportional to rate of change of frequency, also on a cycle-to-cycle basis, is suggested.     

双STC时钟恢复电路的设计与实现

针对数字电视机顶盒的重要功能——多节目解码对播放同步的需求,设计了一种双时钟计数器(STC)的时钟恢复电路,并在支持先进音视频编码标准(AVS)的高清解码芯片中得到实现。该电路使用主从两个STC,主STC由一个混合型的锁相环驱动,该锁相环产生的27MHz时钟同时用于产生音视频解码时钟;从STC则由一个全数字的锁相环驱动,它仅用于与展示时间戳(PTS)比较产生显示同步控制信号。同时提出了一个硬件的低通滤波算法,该算法保证了STC在稳态下追踪传输流中的节目时钟参考(PCR)的变化,并且提供稳定的时钟输出,同时有效降低了主控CPU的负荷。仿真实验结果表明,所提出的时钟恢复电路和低通滤波算法具有较好的性能和较低的计算复杂度,并有效地降低了硬件开销。     

高速光纤通信用定时恢复判决电路

对光纤通信用定时恢复判决电路进行了研究,设计了由1μm耗尽型GaAs金属－半导体势垒场效应晶体管（MESFET）器件构成的判决电路和时钟提取电路。判决电路的基本单元为源耦合场效应晶体管逻辑（SCFL）电路,时钟提取电路由预处理器和锁相环构成。模拟分析表明,时钟提取电路可从输入信号中提取判决电路所需的时钟脉冲,频率达2．5GHz,判决电路可对输入信号进行正确的“0”、“1”判决,并经时钟抽样后,输出正确的数字信号,传输速率达2．5Gbit/s。实测电路可正确判决,时钟抽样后,输出正确的数字信号,传输速率达2．5Gbit/s。     

Direct digital synthesizer with jittered clock

Since the direct digital synthesizer (DDS) can potentially be used as a flexible clock source, it is of interest to study its spectrum purity as well as jitter characteristic. In this paper, we investigate the jitter transfer characteristic of the DDS clock driven by a jittered digital-to-analog converter (DAC) clock. We first derive the dosed form expressions of the spectrum of the DAC output signal with jittered driving clock. These expressions are then used to investigate the spectral structure of the DDS clock. Equations are derived for the calculation of the SNR. For a small phase noise power in the driving clock, the DDS clock SNR is obtained in a simple closed form and is shown to be lower than that of the input driving clock by the amount of 20 log(f_s/d_d) dB, where f_s is the nominal driving clock frequency and f_d is the desirable DDS output clock frequency     

Time Transfer by Passive Listening Over a 10-Gb/s Optical Fiber

A technique for time and frequency transfer over an asynchronous fiber optical transmission control protocol (TCP)/IP network is being developed in Sweden by SP Measurement Technology together with STUPI. The technique is based on passive listening to existing data traffic at 10 Gb/s in the network. Since the network is asynchronous, intermediate supporting clocks will be located and compared at each router. We detect, with a specially designed high-speed optoelectronic device, a header recognizer, the frame alignment bytes of the synchronous optical network (SONET)/synchronous digital hierarchy (SDH) protocol, as a reference for the supporting clock comparison. The goal of the project is to establish a time transfer system with an accuracy on the nanosecond level. In this paper, we present the results of a time transfer over a distance of 5 km. We have compared two clocks: a cesium clock at the Swedish National Laboratory for time and frequency and a remote rubidium clock. The results of the time transfer with the fiber link have been simultaneously compared to measurements with a Global Positioning System (GPS) carrier phase link in terms of precision and stability. The root-mean-square (rms) difference between the time difference measured with the fiber link and the GPS link is approximately 300 ps. A large part of the difference is due to the heating of the GPS antenna cable, which introduces daily delay variations on the order of 1 ns from peak to peak. For one of the days with small day-to-day variations in temperature, the corresponding rms difference is 72 ps, and the Allan deviation is below 30 ps for averaging times longer than 5 min.     

A 1.2-V 0.25-/spl mu/m clock output pixel architecture with wide dynamic range and self-offset cancellation

A 10T/pixel CMOS digital pixel sensor with clock count output, ultra low supply voltage, and wide dynamic range is presented. The pixel fabricated by a standard 0.25-/spl mu/m CMOS logic process comprises a reset transistor, a photo-diode, a comparator, and an inverter with pixel size of 9.4/spl times/9.4 /spl mu/m/sup 2/ and 24% fill factor. The amplified logarithmic output response similar to the light response of human eye is demonstrated in this work. The pixel can operate at a supply voltage as low as 1.2 V without affecting its output characteristics. The dynamic range of this cell limited by either the subsequent analog-to-digital circuit resolution or the rising and falling time of output clock is higher than 90 dB with an 8-bit resolution.