带寄生及匹配约束的CMOS模拟电路模块的STACK生成优化方法

模拟电路的性能紧密依赖于版图的寄生参数和匹配特性 .提出了用以描述分布式的寄生电容和由于工艺梯度变化而产生的寄生参数不匹配以及 STACK内连线的不匹配的模型 .基于该模型 ,一种新的 STACK生成方法用来控制版图的寄生参数和匹配特性 ,优化 STACK的形状和确保为所给出的模拟电路模块生成相映的欧拉图 .一个 OPA电路的例子说明了所提出的版图优化方法可以提高诸如单位增益带宽和相位余量等电路性能     

粒子群算法优化特征和神经网络的模拟电路故障诊断

模拟电路受到自身特性和外界环境的影响,故障变化具有非线性、时变性,针对当前模拟电路故障诊断模型的特征和分类器参数不匹配的难题,提出一种粒子群算法选择特征和神经网络的模拟电路故障诊断模型。首先对当前模拟电路故障诊断现状进行分析,指出它们存在的缺陷;然后提取模拟电路故障诊断特征,利用神经网络作为模拟电路故障诊断分类器;最后采用粒子群算法对模拟电路故障特征与神经网络参数进行优化,在Matlab 2012平台进行了仿真实验。结果表明,该模型的模拟电路故障诊断性能要远远优于其他参比模型,具有广泛的应用前景。     

标准单元电路-版图设计自动优化技术

提出了一种标准单元的电路-版图设计自动优化技术.根据目标电学性能等确定电路中器件的参数值,然后根据参数变化微调现有的标准单元版图,快速自动生成符合设计规则的新版图.该技术可从新版图中获取电路寄生参数,对电路的电学性能进行评估,进一步提高电路-版图设计自动优化速度.测试表明,该技术既可以用于加速标准单元建库和设计移植,也可以支持对更高层的SOC设计进行延时和功耗的在位优化,加速设计收敛,可缩短开发周期.     

CMOS模拟开关中的闭锁现象及消除方法

本 文描述了CMOS集成电路中的闭锁现象的机理,分析了寄生PnPn可控硅的触发条件.提出了防止CMOS模拟开关电路闭锁的措施,以及本电路的版图设计和工艺设计的原则,从而实现消除闭锁现象的目的.最后介绍了研制中的CMOS模拟开关的抗闭锁性能和电路性能.     

利用正多项式响应曲面模型实现模拟电路参数自动生成

提出一种基于仿真的模拟电路参数自动生成方法,通过利用模拟电路性能仿真数值结果生成描述电路性能与电路参数之间关系的正多项式响应曲面模型(polynomial response surface models),再利用若干性能曲面模型协同求出满足全部性能要求的模拟电路的参数配置.这种方法的本质是将电路参数化问题转化为几何规划(geometric program)问题,为线性或非线性电路生成达到Spice器件仿真级精度的性能正多项式响应曲面.文中提出的正多项式响应曲面模型的待求参数包括正实数系数和任意实数指数,其回归分析过程中如果模型无法满足精度要求,可通过自动修改模型的多项式结构最终获得理想结果.最后以运算放大器电路为例,生成精确描述电路性能的正多项式响应曲面模型,并通过若干正多项式响应曲面模型得到满足性能要求的参数配置.     

利用正多项式响应曲面模型实现模拟电路参数自动生成

提出一种基于仿真的模拟电路参数自动生成方法,通过利用模拟电路性能仿真数值结果生成描述电路性能与电路参数之间关系的正多项式响应曲面模型(polynomial response surface models),再利用若干性能曲面模型协同求出满足全部性能要求的模拟电路的参数配置.这种方法的本质是将电路参数化问题转化为几何规划(geometric program)问题,为线性或非线性电路生成达到Spice器件仿真级精度的性能正多项式响应曲面.文中提出的正多项式响应曲面模型的待求参数包括正实数系数和任意实数指数,其回归分析过程中如果模型无法满足精度要求,可通过自动修改模型的多项式结构最终获得理想结果.最后以运算放大器电路为例,生成精确描述电路性能的正多项式响应曲面模型,并通过若干正多项式响应曲面模型得到满足性能要求的参数配置.     

低失配CMOS差分放大器的后端版图设计研究

器件尺寸的缩小提高了晶体管的原始速度,但是集成电路不同模块间有害的相互干扰和版图的非理想性都限制了系统的工作速度和精度。理想的差分放大器电路参数是完全对称的,但实际电路中,由于制造工艺每道工序的不确定性,标称相同的器件都存在有限的不匹配。本文在设计差分电路的版图时通过讨论制造工艺和版图结构对电路性能的影响,设计了失配较小,寄生效应小的单管版图结构,并在全局布局时充分考虑了对称性对电路性能的影响得到了比较理想的差分放大器版图。     

信号流驱动的模拟电路版图综合方法

提出了一种新的基于信号流分析的模拟电路版图综合方法.电路分析子系统采用新提出的信号流分析方法再结合已有的电路拓扑分析和电路灵敏性分析方法生成布图约束控制电路性能的衰减.由于考虑了电路中有关信号流的启发式信息,该方法的复杂性较一般的纯粹性能驱动方法小.然后分别在器件生成子系统、布图子系统和布线子系统中实现这些约束,使得这些约束在最容易实现的阶段得到满足.实际的电路例子已经证明了这一方法可以获得出色的电路性能.     

差分放大器中的不匹配效应及消除方法

叙述模拟集成电路设计中关于MOS管不匹配特性的一些基本概念,以及随着加工尺寸的不断减小,MOS管所引起的一系列短沟道效应,进而描述整个MOS管模型的发展历史,以此说明一个精确模型对模拟电路设计的重要意义.然后进一步阐述因MOS管失配而引起电路性能变差,尤其是对整个D/A转换器性能的影响;进而采用改进技术,并对其进行了进一步验证.针对放大器引起的失调,介绍通过版图设计消除失配的原理,并且运用电路设计方法进行消除,采用TSMC0.25μm标准CMOS工艺参数对其进行仿真验证.针对D/A的电流源失配引起的电路性能变差,采用了电流源自校准技术,并对这种方法进行了仿真验证,取得了不错的成果.     

S－域行为描述的模拟集成电路综合方法

本文提出了一种通用的、从Ｓ－域传输函数入手进行模拟集成电路结构级综合的方法，并详细地讨论了提高电路性能和合格率的电路技巧。此外，本文还给出了生成物理版图的一点建议，本文采用该方法完成了切比雪夫滤波器的综合，ＳＰＩＣＥ模拟结果表明该方法是可行的。     

Automated hierarchical CMOS analog circuit stack generation withintramodule connectivity and matching considerations

An efficient automated layout for CMOS transistors in analog circuits is described. The matching requirements are used as the primary constraint on the analog layout; however, parasitic capacitances and area considerations are also included. A designer-chosen arbitrary circuit partition from the schematic can be used to generate the corresponding layout as an optimum stack of transistors with complete intramodule connectivity. The transistor stack generation is performed by representing the circuit with a diffusion graph and recursively fragmenting the graph until the base constructs are reached. For each of the modules, the port structures are also created. These port structures are considered as part of the module area and parasitic optimization procedure. With aspect-ratio-related constraints, the procedure allows optimal floorplanning. The results are demonstrated through several examples     

一种SAR ADC电容失配自测量与数字校准技术

为了解决高分辨率逐次逼近模数转换器(SAR ADC)中,电容式数模转换器(DAC)的电容失配导致精度下降的问题,提出了一种电容失配自测量方法,以及一种可适用于各种差分电容DAC设计的低复杂度的前台数字校准方法。该方法利用自身电容阵列及比较器完成位电容失配测量,基于电容失配的转换曲线分析,对每一位输出的权重进行修正,得到实际DAC电容大小对应的正确权重,完成数字校准。数模混合电路仿真结果表明,引入电容失配的16位SAR ADC,经该方法校准后,有效位数由10.74 bit提高到15.38 bit。     

Directly performance-constrained template-based layout retargeting and optimization for analog integrated circuits

Due to intrinsic intricacy, layout parasitics exhibit a significant impact on the performance of analog integrated circuits. In this paper a directly performance-constrained parasitic-aware automatic layout retargeting and optimization algorithm is presented. Unlike the conventional sensitivity analysis, a general central-difference based scheme using any simulator for sensitivity computation is deployed. We propose a piecewise sensitivity model to enforce more accurate sensitivity computation during parasitic optimization. Moreover, mixed-integer performance constraints due to parasitics are included in the formulated mixed integer nonlinear programming problem rather than through either indirect parasitic-bound constraints or inaccurate worst-case sensitivities. A graph technique and mixed-integer nonlinear programming are effectively combined to solve the formulated parasitic optimization problem. The automatically generated target layouts can satisfy performance constraints to ensure the desired specifications. The experimental results show that the proposed algorithm can achieve effective retargeting of analog circuits with less layout area and significant reduction in execution time.     

Automatic layout synthesis of analog ICs using circuit recognition and constraint analysis techniques

A systematic method for automatic layout synthesis of analog integrated circuit modules is presented. This method uses analog circuit recognition and critical net analysis techniques to derive proper layout constraints for analog circuit performance optimization. These layout constraints are analyzed and prioritized according to the recognized analog circuit topologies and classified net sensitivities. The weighted constraints are then used to drive the physical layout generation process to obtain a high-quality custom circuit layout. An efficient, constraint-driven analog floorplanning technique based on a zone-sensitivity partitioning algorithm is specially developed to generate a slicing floorplan incorporating the layout constraints. This layout synthesis approach has three key advantages. First, it can produce a satisfactory analog circuit performance with negligible degradation due to the layout-introduced parasitic effects. Second, it allows a complete automation for netlist-to-layout synthesis so that the layout tool can be used by VLSI system designers. Finally, this method is quite general and can be applied to handle a wide variety of analog circuits. Experimental results in CMOS operational amplifiers and a comparator are presented.     

Sub-millimeter-Wave Equivalent Circuit Model for External Parasitics in Double-Finger HEMT Topologies

We present a novel distributed equivalent circuit that incorporates a three-way-coupled transmission line to accurately capture the external parasitics of double-finger high electron mobility transistor (HEMT) topologies up to 750 GHz. A six-step systematic parameter extraction procedure is used to determine the equivalent circuit elements for a representative device layout. The accuracy of the proposed approach is validated in the 90–750 GHz band through comparisons between measured data (via non-contact probing) and full-wave simulations, as well as the equivalent circuit response. Subsequently, a semi-distributed active device model is incorporated into the proposed parasitic circuit to demonstrate that the three-way-coupled transmission line model effectively predicts the adverse effect of parasitic components on the sub-mmW performance in an amplifier setting.     

时间交叉模数转换系统的时间失配补偿

时间交叉模数转换结构是提高模数转换系统采样率的一种有效途径。由于制造工艺的局限和布线的差异,这种结构会引入通道失配而限制系统的性能。通道失配包括偏置失配、增益失配和时间失配。文中提出了一种基于快速傅里叶变换（Fast Fourier Transform,FFT）计算时间失配并采用有限冲激响应（Finite Impusle Response,FIR）滤波器对它进行补偿的方法,并通过Matlab仿真验证了算法的有效性和可行性。     

使用大规模存储器电路的PEX技术研究

随着集成电路(IC)制造工艺向深亚微米逐渐深入,寄生参数对IC的性能影响越来越大,因此对寄生参数的提取及分析(后仿真)也就显得愈发重要。文章以寄生参数提取的原理及基本方法为引入,分析寄生RC参数产生机制和计算方法,并以含有大规模存储单元的IC设计为例,研究如何利用现有的提取工具解决提取效率的问题,提出了模块划分、重复利用、参数定位和反标配置等操作方案,重点分析基于calibre XRC的PEX在IC设计中遇到的问题,并结合实际情况给出合适的解决方案。     

ALGA: Automated layout generator for analog CMOS circuits

A computer-aided design (CAD) system called ALGA for an analog circuit layout is presented. The main contribution of this paper is to construct a weight graph that represents the topological connectivity of a given analog circuit. By using the weight graph, some efficient techniques can be designed to avoid devices mismatch and place all devices according to the device size constraints. Moreover, an algorithm is presented to perform the device placement step and propose an effective approach to reduce noise coupling in the routing step. A design method has been implemented in several Complementary Metal Oxide Semiconductor (CMOS) analog circuits. It is seen that the proposed system can generate good analog circuit design.     

Operational-amplifier compilation with performance optimization

A method for designing analog circuits in which topological design is followed by simultaneous device sizing and layout design is described. By merging circuit and layout design into a single design process, analog circuits can be optimally designed taking layout parasitics fully into account. Using the method, a CMOS operational-amplifier compiler (OAC) has been developed. Given a set of performance specifications and process parameters, OAC generates a layout with circuit performance optimized to meet specified performance constraints. A procedural layout technique is employed to generate a compact and practical layout. A nonlinear optimization method for device sizing which relies on the results of simulations based on the circuit extracted from the layout is applied. Design experiments have shown that OAC can produce satisfactory results with respect to both circuit performance and layout density