Wide tuning-range CMOS VCO based on a tunable active inductor

In this paper, a wide tuning-range CMOS voltage-controlled oscillator (VCO) with high output power using an active inductor circuit is presented. In this VCO design, the coarse frequency is achieved by tuning the integrated active inductor. The circuit has been simulated using a 0.18-µm CMOS fabrication process and presents output frequency range from 100 MHz to 2.5 GHz, resulting in a tuning range of 96%. The phase noise is –85 dBc/Hz at a 1 MHz frequency offset. The output power is from –3 dBm at 2.55 GHz to +14 dBm at 167 MHz. The active inductor power dissipation is 6.5 mW and the total power consumption is 16.27 mW when operating on a 1.8 V supply voltage. By comparing this active inductor architecture VCO with general VCO topology, the result shows that this topology, which employs the proposed active inductor, produces a better performance.     

A -119.2 dBc/Hz at 1 MHz, 1.5 mW, fully integrated, 2.5-GHz, CMOS VCO using helical inductors

This letter presents an implementation to reduce area occupation in designing voltage-controlled oscillators (VCOs) using a filtering technique. We applied a helical inductor to the noise filter in a 2.5-GHz CMOS VCO to reduce area occupation. Because a helical inductor has less area occupation, a small silicon area was achieved. This VCO operates in the 2.5-GHz band with power consumption of 1.5 mW and phase noise of -119.2 dBc/Hz at 1-MHz. Our VCO displays an excellent performance of phase noise in relation to power consumption.     

UTSi CMOS: A Complete RF SOI Solution

Fully integrated frequency synthesizers are comprised of three major blocks: a voltage controlled oscillator (VCO), a phase locked loop (PLL) and a loop filter between them. In this paper we discuss the technology and design issues necessary to make fully integrated synthesizers capable of meeting the demanding specifications of GSM and CDMA systems. All elements of the synthesizer will be discussed. Two of the most difficult elements to integrate are the inductor and varactor in the resonant circuit of the VCO; we will discuss these devices at length. CMOS/SOI on a sapphire substrate has shown to significantly improve RF device characteristics. Reduced floating body effects; achievement of high Q on chip components; excellent isolation; and high performance RF circuits enable high performance fully integrated synthesizers on SOS substrates.     

A 1.0 V differential VCO in 0.13 μm CMOS technology

A differential complementary LC voltage controlled oscillator(VCO) with high Q on-chip inductor is presented.The parallel resonator of the VCO consists of inversion-mode MOS(I-MOS) capacitors and an on-chip inductor.The resonator Q factor is mainly limited by the on-chip inductor.It is optimized by designing a single turn inductor that has a simulated Q factor of about 35 at 6 GHz.The proposed VCO is implemented in the SMIC 0.13μm 1P8M MMRF CMOS process,and the chip area is 1.0×0.8 mm~2.The free-running frequency is from 5.73 to 6.35 GHz.When oscillating at 6.35 GHz,the current consumption is 2.55 mA from a supply voltage of 1.0 V and the measured phase noise at 1 MHz offset is -120.14 dBc/Hz.The figure of merit of the proposed VCO is -192.13 dBc/Hz.     

Floating active inductor based Class-C VCO with 8 digitally tuned sub-bands

A fully integrated floating active inductor based voltage-controlled oscillator (VCO) is presented. The active inductor employs voltage differencing transconductance amplifier (VDTA) as a building block. The designed VCO achieves frequency tuning by varying the bias current through the VDTA and utilizes a Class-C topology for improving the phase noise performance. The inductor-less VCO is designed and implemented in a 45-nm CMOS process and its performance is estimated using Virtuoso ADE of Cadence. Operating at a supply voltage of ±1 V, the proposed VCO consumes 0.44–1.1 mW corresponding to the oscillation frequency of 1.1–1.8 GHz thereby exhibiting a tuning range of 48.27%. The phase noise of the VCO lies in the range of −94.12 to −98.37 dBc/Hz at 1 MHz offset resulting in a FOM of −172.14 to −176.69 dBc/Hz.     

A phase-noise reduction technique for RF CMOS voltage-controlled oscillator with a series LC resonator

This paper proposes a novel phase-noise reduction technique for high performance voltage-controlled oscillator (VCO) using a cross-coupled series LC resonator, rather than parallel LC resonator. The proposed technique makes a time difference between the zero crossing point of the drain node voltages and that of the gate node voltages of the switching pair. By adding cross coupled PMOS loading, the drain voltages are made close to a rectangular shape, which makes an ideal on–off switching of the VCO. Since the current source contributes large portion of noise to the output, it is removed in the proposed VCO to further improve the noise performance. While the series connected inductor and capacitor enhances the fundamental frequency swing at the LC connection node, it gives a cleaner spectral purity output and suppresses the overall noise at the drain node of the cross-coupled switching cell.     

A 0.35-/spl mu/m CMOS 2-GHz VCO in wafer-level package

This letter presents a complementary metal oxide semiconductor (CMOS) voltage-controlled oscillator (VCO) with a high-Q inductor in a wafer-level package for the LC-resonator. The on-chip inductor is implemented using the redistribution metal layer of the wafer-level package (WLP), and therefore it is called a WLP inductor. Using the thick passivation and copper metallization, the WLP inductor has high quality-factor (Q-factor). A 2-nH inductor exhibits a Q-factor of 8 at 2 GHz. The center frequency of the VCO is 2.16 GHz with a tuning range of 385 MHz (18%). The minimum phase noise is measured to be -120.2 dBc/Hz at an offset frequency of 600 kHz. The dc power consumed by the VCO-core is 1.87 mW with a supply voltage of 1.7 V and a current of 1.1 mA. The output power with a 50-/spl Omega/ load is -12.5/spl plusmn/1.3 dBm throughout the whole tuning range. From the best of our knowledge, compared with recently published 2-GHz-band 0.35 /spl mu/m CMOS VCOs in the literature, the VCO in this work shows the lowest power consumption and the best figure-of-merit.     

考虑衬底涡旋电流的CMOS射频电路电感元件的快速提取算法及实现

本文描述了一个采用复镜像方法来解析计算CMOS射频电路中衬底涡旋电流对螺旋电感元件的影响.其基本思路是将衬底里分布着的涡旋电流等效为电感金属绕组的一个镜像,但是这个镜像所处的位置是一个复数.通过把计算出的部分电感和部分电容矩阵组装成一个PEEC(部分元件等效电路)的办法,能够进一步算出螺旋电感的交流小信号参数.基于该算法实现的程序(称为SCAPE)的正确性已经通过大量的例子测试,并跟一些广泛使用的软件(如UC Berkeley的ASITIC和Agilent的ADS Momentum)进行了比较,结果证明了SCAPE具有精度高、运算速度快的优势.     

硅微机械悬浮结构电感的设计与制作工艺研究

本文系统分析了影响平面螺旋电感Q值的主要因素,并制作出一种应用于射频通信的硅微机械悬浮结构电感.在考虑趋肤效应、涡流损耗等高频电磁场效应对电感Q值的影响后,获得了微机械电感的简化电学模型,得到了具有较高Q值电感的优化结构.在制作硅微机械电感的工艺过程中,采用多孔硅作为牺牲层材料,将螺旋结构铝线圈制作在二氧化硅薄膜上,在使用添加了硅粉和过硫酸铵的TMAH溶液释放牺牲层之后,得到设计值为4nH的悬浮结构微机械平面螺旋电感.实验结果证明,整个工艺流程可靠,并与CMOS工艺兼容.     

A 1.9-GHz CMOS VCO with micromachined electromechanically tunablecapacitors

This paper presents a 1.9-GHz CMOS voltage-controlled oscillator (VCO) where the resonant circuit consists of micromachined electromechnically tunable capacitors and a bonding wire inductor. The tunable capacitors were implemented in a MUMP's polysilicon surface micromachining process. These devices have a nominal capacitance of 2.1 pF and a quality factor (Q-factor) of 9.3 at 1.9 GHz. The capacitance is variable from 2.1 pF to 2.9 pF within a 4-V control, voltage range. The active circuits were fabricated in a 0.5-μm CMOS process. The VCO was assembled in a ceramic package where the MUMP's and CMOS dice were bonded together. The experimental VCO achieves a phase noise of -98 dBc/Hz and -126 dBc/Hz at 100 kHz and 600 kHz offsets from the carrier, respectively. The tuning range of the VCO is 9%. The VCO circuit and the output buffer consume 15 mW and 30 mW from a 2.7-V power supply, respectively     

差分LC VCO的设计方法

通过分析振荡器的两种典型相位噪声模型,给出了振荡器相位噪声与电路参数的关系。在此基础上,提出了优化VCO相位噪声的设计方法：设计高Q值电感;调整尾电流的大小;调整nMOS管和pMOS管的尺寸。文章最后给出了一个2．4GHz全集成VCO的设计,仿真结果表明在2．4GHz时VCO的相位噪声为-120．4dBc／Hz@600kHz,证明该方法对于VCO的设计具有较好的指导作用。     

Analysis and synthesis of on-chip spiral inductors

This paper presents a physically based compact model for estimating high-frequency performance of spiral inductors. The model accurately accounts for skin and proximity effects in the metal conductors as well as eddy current losses in the substrate. The model shows excellent agreement with measured data mostly within 10% across a variety of inductor geometries and substrate dopings up to 20 GHz. A web-based spiral inductor synthesis and analysis tool COILS, which makes use of the compact models, is presented. An optimization algorithm using binary searches speeds up the synthesis of inductor designs.     

Modeling and characterization of a 5.2 GHz VCO for UWB applications in 0.13 μm CMOS process

This paper describes a 5.2 GHz voltage-controlled oscillator (VCO) as a key component in RF transceivers. The circuit includes a complementary cross-coupled MOSFET as a negative conductance, beside a tank circuit which consists of an optimal on-chip spiral inductor (L), and an accumulation mode MOS varactor (C(V)). A model for phase noise and figure merit is introduced and verified through simulation in a standard 0.13 μm CMOS process. The VCO core drew a 4.2 mA of current from a 1.2 V power supply and a phase noise of −98.5 dBc/Hz at 1 MHz offset from the 5.2 GHz carrier was calculated. The whole performance of the circuit specifically the tuning range was found to be 26%.     

A Novel Broad-Band MMIC VCO Using an Active Inductor

This paper proposes a novel broad-band MMIC VCO using an active inductor. This VCO is composed of a serial resonant circuit, in which the capacitor is in series with an active inductor that has a constant negative resistance. Since the inductance value of this active inductor is inversely proportional to the square of the transconductance and can vary widely with the FETs gate bias control, a broad-band oscillation tuning range can be obtained. Furthermore, since this active inductor can generate a constant negative resistance of more than 50 , the proposed VCO can oscillate against a 50- output load immediately without using additional impedance transformers. We have fabricated the VCO using a GaAs MESFET process. A frequency tuning range of more than 50%, from 1.56 to 2.85 GHz, with an output power of 4.4±1.0 dBm, was obtained. With a carrier of 2.07 GHz, the phase noise at 1-MHz offset was less than –110 dBc/Hz. The chip size was less than 0.61 mm², and the power consumption was 80 mW. This broad-band analog design can be used at microwave frequencies in PLL applications as a compact alternative to other types of oscillator circuits.     

Physical modeling of spiral inductors on silicon

This paper presents a physical model for planar spiral inductors on silicon, which accounts for eddy current effect in the conductor, crossover capacitance between the spiral and center-tap, capacitance between the spiral and substrate, substrate ohmic loss, and substrate capacitance. The model has been confirmed with measured results of inductors having a wide range of layout and process parameters. This scalable inductor model enables the prediction and optimization of inductor performance     

A 1?mW power-efficient high frequency CML 2:1 divider

In this study, a low power high operating frequency current mode logic (CML) 2:1 divider is presented. Because the latching transistor pair is biased in low current mode, the proposed divider is power-saving. In this divider, each latch has only one clock transistor, which means that the capacitive load to the former stages is reduced. This makes the buffer of the voltage controlled oscillator (VCO) or VCO be easily designed in phase locked loops. Besides, an active inductor is used in this circuit to resonate with parasitic capacitances and thus endows this topology a high-speed capability. The measurement results indicate that the proposed divider achieves an operation band from 10 to 15?GHz with only 1mW power dissipation.     

A 2-GHz low-phase-noise integrated LC-VCO set with flicker-noiseupconversion minimization

A fully integrated 2-GHz very low-phase-noise LC-tank voltage-controlled oscillator (VCO) set with flicker noise upconversion minimization is presented. Using only integrated planar inductors, the measured phase noise is as low as -125.1 dBc/Hz at 600-kHz offset and -138 dBc/Hz at 3 MHz. The excellent phase-noise performance is achieved by means of an in-house-developed integrated inductor simulator optimizer. To minimize the upconversion of flicker noise to 1/f³ phase noise, a flicker-noise upconversion factor is defined, which can easily be extracted from circuit simulation. The technique is applied to demonstrate the relationship between the flicker-noise upconversion and the overdrive level of the oscillators' MOS cross-coupled pair and to develop circuit balancing techniques to even further reduce the flicker-noise upconversion. The 1/f³ phase-noise corner is minimized to be less than 15 kHz. The VCO's are implemented in a three-metal layer, 0.65-μm BiCMOS process, using only MOS active devices     

Design of wide-band CMOS VCO for multiband wireless LAN applications

In this paper, a general design methodology of low-voltage wide-band voltage-controlled oscillator (VCO) suitable for wireless LAN (WLAN) application is described. The applications of high-quality passives for the resonator are introduced: 1) a single-loop horseshoe inductor with Q > 20 between 2 and 5 GHz for good phase noise performance; and 2) accumulation MOS (AMOS) varactors with C/sub max//C/sub min/ ratio of 6 to provide wide-band tuning capability at low-voltage supply. The adverse effect of AMOS varactors due to high sensitivity is examined. Amendment using bandswitching topology is suggested, and a phase noise improvement of 7 dB is measured to prove the concept. The measured VCO operates on a 1-V supply with a wide tuning range of 58.7% between 3.0 and 5.6 GHz when tuned between /spl plusmn/0.7 V. The phase noise is -120 dBc/Hz at 3.0 GHz, and -114.5 dBc/Hz at 5.6 GHz, with the nominal power dissipation between 2 and 3 mW across the whole tuning range. The best phase noise at 1-MHz offset is -124 dBc/Hz at the frequency of 3 GHz, a supply voltage of 1.4 V, and power dissipation of 8.4 mW. When the supply is reduced to 0.83 V, the VCO dissipates less than 1 mW at 5.6 GHz. Using this design methodology, the feasibility of generating two local oscillator frequencies (2.4-GHz ISM and 5-GHz U-NII) for WLAN transceiver using a single VCO with only one monolithic inductor is demonstrated. The VCO is fabricated in a 0.13-/spl mu/m partially depleted silicon-on-insulator CMOS process.     

LC-VCOs using spiral inductors with single- and dual-layer patterned floating shields: a comparative study

This letter studies and compares class-B VCOs using spiral inductors with the proposed dual-layer patterned floating shield (DL-PFS) and conventional single-layer patterned floating shield (SL-PFS). The proposed DL-PFS technique utilizes two lowest metal layers to effectively reduce the capacitive induced current to the substrate in an on-chip spiral inductor, thereby boosts its Q-factor by 40% when compared with the conventional SL-PFS approach. We fabricated, as a proof of concept, the class-B LC-VCOs using the DL-PFS and SL-PFS in 0.13 µm CMOS. Operating at 10 GHz, the VCO with the DL-PFS inductor measures a 3.6 dB phase noise (PN) improvement at the same power consumption of 2.12 mW. Specifically, the VCO with DL-PFS inductor is tunable from 9.3-to-10.1 GHz and measured PN at 10 GHz is ?132.5 dBc/Hz at 10 MHz offset while consuming 2.12 mW at the lowest 0.6 V supply. The achieved figure-of-merit (187.4 dBc/Hz@1 MHz offset) compares favorably with the recent state-of-the-art.     

All-active monolithic InP-based HBT VCO with tunable HEMT inductor

A novel HEMT-HBT VCO is presented; it is the first all-active analogue VCO demonstrated using InP HEMT-HBT integrated MMIC technology. The MMIC monolithically integrates an InP common-collector HBT oscillator with a tunable InP HEMT active inductor using selective MBE. The novel HEMT-HBT VCO can provide performance advantages over analogue VCOs such as the multi-vibrator, and has direct implications for high speed clock recovery circuits needed in InP based optoelectronic IC applications