多标准宏块预测与边界强度计算的VLSI架构及应用

提出一种支持H.264 High Profile 4.1和AVS JiZhun Profile 6.0的多标准宏块预测与边界滤波强度计算的VLSI架构,该架构根据解码器的算法特点,实现了H.264和AVS标准中控制占优的帧内模式预测、帧间运动矢量预测以及边界滤波强度计算算法,能应用于当前的可重构多媒体系统.对该架构进行实现后,采用TSMC 65nm工艺综合,工作频率可达到312 MHz,解码一个H.264和AVS宏块最大分别消耗351和189个时钟周期,能够满足H.264和AVS高清(1080p)实时处理的需求.     

Efficient Memory Architecture and Implementation of Motion Compensation for Multi-Standard Video Decoder

设计了一种适用于多标准视频解码器的存储架构,采用并行多级流水线用以实现AVS,MPEG -2,H.264标准中不同模式的图像预测计算,缓存机制避免了频繁访问外部存储器SDRAM,提高了运动补偿计算性能,减少了计算周期.使用90nm的CMOS工艺库,在135 MHz的工作频率下综合,电路规模为45 kgate(千门)左右,处理一宏块需要大约520个时钟周期,结果表明该设计满足高清视频处理的要求.     

多标准视频解码器运动补偿存储架构设计

设计了一种适用于多标准视频解码器的存储架构,采用并行多级流水线用以实现AVS,MPEG-2,H.264标准中不同模式的图像预测计算,缓存机制避免了频繁访问外部存储器SDRAM,提高了运动补偿计算性能,减少了计算周期。使用90 nm的CMOS工艺库,在135 MHz的工作频率下综合,电路规模为45 kgate(千门)左右,处理一宏块需要大约520个时钟周期,结果表明该设计满足高清视频处理的要求。     

一种多模视频解码SoC的运动矢量预测器设计

设计一种可应用于多模视频解码SoC的运动矢量预测器,能灵活支持MPEG-4 AVC/H.264和AVS视频编解码标准.介绍了设计特点,并以Xilinx Virtex2系列XC2V6000为目标器件进行仿真,结果表明该设计能正确支持1080i 50 Hz高清码流的实时解码.     

基于快速预测映射的H.264到AVS转码

对H.264和AVS标准进行了比较,在总结几种通用的模式和运动矢量复用方法基础上,提出一种更简单也略微提高效率的H.264到AVS的快速预测转码方案,可有效降低算法复杂度.实验证明,此转码方案可以在PSNR损失极少的前提下提高编码效率.     

基于改进KNN算法的AVS到H.264/AVC 快速转码方法

尽管音视频编码标准(Audio and Video Coding Standard,AVS)的编码性能可以与H.264相媲美,但是H.264的应用范围更加广泛,因此视频由AVS标准转码成H.264标准具有很大的应用前景.目前,主流的转码方法是将AVS的分块模式与H.264的分块模式映射的方式降低转码复杂度,但是技术之间的差异导致这两种标准之间的分块模式并不是一一映射的关系,因此会导致编码效率大幅度降低.提出一种基于改进KNN(K最邻近节点)算法的AVS到H.264/AVC快速转码方法.充分利用了AVS码流中的各种信息,通过改进的KNN算法建立了中间信息和H.264分块模式之间的映射模型.根据AVS中运动矢量信息的差异自适应确定H.264可能的分块模式,实验结果表明上述问题得到有效解决,该算法在保证H.264编码效率的前提下大幅降低了转码复杂度.     

一种快速的半像素运动矢量搜索算法

提出了一种基于梯度预测的快速半像素运动矢量搜索算法.实验结果表明,在H.263编码器中使用该算法的运算量,比在相同量化阶下的半像素运动矢量搜索算法下降45%,并且图像的PSNR和码率变化很小.该算法可以很容易地应用到H.264的1/4像素运动矢量搜索中.     

用于AVS和H.264可变长解码器的设计与实现

可变长解码广泛用于各种视频压缩标准中。本文提出了一种适用于AVS和H．264两种标准的可变长解码器。由于支持两个标准并且为了节省硬件，该结构采用模块的复用。采用桶型移位器，实现并行解码，提高解码速度。对解析AVS和CAVLC的码流进行了周期的分析，证实该设计能够实现实时的高清解码。本设计通过了FPGA验证。     

基于矢量预测的快速运动估计搜索算法

基于H.264视频编码标准的编解码过程中,运动估计的时间大概要占总编码时间的70%(1个参考帧)到90%(5个参考帧)。对于H.264标准的新特点,传统的全搜索算法的精度高,但计算量太大,不能应用于实时处理;经典的菱形等算法搜索模式简单,易于实现,但容易陷入局部无穷小。采用了一种基于运动矢量预测的快速运动估计搜索算法。该方法首先利用运动矢量的时、空间相关性得到预测矢量,然后利用非对称十字型搜索确定运动估计的起始点,最后采用经典的菱形算法进行运动估计。实验结果表明,相比UMHexagonS快速搜索算法,该算法能够在码率增加不超过1%,信噪比下降不超过0.1 dB的情况下,运动估计速度有较大提高。     

面向高清和3D电视的视频编解码标准AVS+

介绍了AVS+(GY/T 257-2012 《广播电视先进音视频编解码第1部分:视频》)标准的制定背景与过程,重点介绍了AVS+新增加的编码工具以及新特性,介绍了AVS+与AVS、AVC/H.264 HP(High Profile,高级档次)的性能对比,说明了AVS+与AVC HP性能相当.AVS+在多个部委的支持与推进下,将在中国高清与立体电视播出中得到应用.     

Platform-independent MB-based AVS video standard implementation

AVS1-P2 is the newest video standard of Audio Video coding Standard (AVS) workgroup of China, which provides close performance to H.264/AVC main profile with lower complexity. In this paper, a platform-independent software package with macroblock-based (MB-based) architecture is proposed to facilitate AVS video standard implementation on embedded system. Compared with the frame-based architecture, which is commonly utilized for PC platform oriented video applications, the MB-based decoder performs all of the decoding processes, except the high-level syntax parsing, in a set of MB-based buffers with adequate size for saving the information of the current MB and the neighboring reference MBs to minimize the on-chip memory and to save the time consumed in on-chip/off-chip data transfer. By modifying the data flow and decoding hierarchy, simulating the data transfer between the on-chip memory and the off-chip memory, and modularizing the buffer definition and management for low-level decoding kernels, the MB-based system architecture provides over 80% reduction in on-chip memory compared to the frame-based architecture when decoding 720p sequences. The storage complexity is also analyzed by referencing the performance evaluation of the MB-based decoder. The MB-based decoder implementation provides an efficient reference to facilitate development of AVS applications on embedded system. The complexity analysis provides rough storage complexity requirements for AVS video standard implementation and optimization.     

An architecture of entropy decoder,inverse quantiser and predictor for multi-standard video decoding

A VLSI architecture for entropy decoder, inverse quantiser and predictor is proposed in this article. This architecture is used for decoding video streams of three standards on a single chip, i.e. H.264/AVC, AVS (China National Audio Video coding Standard) and MPEG2. The proposed scheme is called MPMP (Macro-block-Parallel based Multilevel Pipeline), which is intended to improve the decoding performance to satisfy the real-time requirements while maintaining a reasonable area and power consumption. Several techniques, such as slice level pipeline, MB (Macro-Block) level pipeline, MB level parallel, etc., are adopted. Input and output buffers for the inverse quantiser and predictor are shared by the decoding engines for H.264, AVS and MPEG2, therefore effectively reducing the implementation overhead. Simulation shows that decoding process consumes 512, 435 and 438 clock cycles per MB in H.264, AVS and MPEG2, respectively. Owing to the proposed techniques, the video decoder can support H.264 HP (High Profile) 1920 × 1088@30fps (frame per second) streams, AVS JP (Jizhun Profile) 1920 × 1088@41fps streams and MPEG2 MP (Main Profile) 1920 × 1088@39fps streams when exploiting a 200 MHz working frequency.     

一种支持H.264与AVS的高效环路滤波器设计

提出一种高效的多模环路滤波器,支持H.264 BP/MP/HP和AVS的视频解码.为实现H.264和AVS滤波结构的复用,对宏块中需要滤波的边界作了修正;使用新颖的混合滤波顺序和宏块分割策略,提高数据的重用率,减小片上缓存;采用并行流水处理等技术提高数据吞吐量.使用65 nm的CMOS工艺库,在200 MHz的工作频率...     

An efficient VLSI architecture for CBAC of AVS HDTV decoder

Context-based Binary Arithmetic Coding (CBAC) is a normative part of the newest X Profile of Advanced Audio Video coding Standard (AVS). This paper presents an efficient VLSI architecture for CBAC decoding in AVS. Compared with CBAC in H.264/AVC, the simpler binarization methods and context selection schemes are adopted in AVS. In order to avoid the slow multiplications, the traditional arithmetic calculation is transformed to the logarithm domain. Although these features can obtain better balance between the compression gain and implementation cost, it still brings huge challenge for high-throughput implementation. The fact that current bin decoding depends on previous bin results in long latency and limits overall system performance. In this paper, we present a software–hardware co-design by using bin distribution feature. A novel pipeline-based architecture is proposed where the arithmetic decoding engine works in parallel with the context maintainer. A finite state machine (FSM) is used to control the decoding procedure flexibly and the context scheduling is organized carefully to minimize the access times of context RAMs. In addition, the critical path is optimized for the timing. The proposed implementation can work at 150 MHz and achieve the real-time AVS CBAC decoding for 1080i HDTV video.     

A Power-Efficient and Self-Adaptive Prediction Engine for H.264/AVC Decoding

Prediction, including intra prediction and inter prediction, is the most critical issue in H.264/AVC decoding in terms of processing cycles and computation complexity. These two predictions demand a huge number of memory accesses and account for up to 80% of the total decoding cycles. In this paper, we present the design and VLSI implementation of a novel power-efficient and highly self-adaptive prediction engine that utilizes a 4 times 4 block level pipeline. Based on the different prediction requirements, the prediction pipeline stages, as well as the correlated memory accesses and datapaths, are fully adjustable, which helps to reduce unnecessary decoding operations and energy dissipation while retaining the fixed real-time throughput. Compared with conventional designs, this paper has the advantage of higher efficiency and lower power consumption due to the elimination of all redundant operations and the wide employment of the pipeline and parallel processing. Under different prediction modes, our design is able to decode each macroblock within 500 cycles. A prototype H.264/AVC baseline decoder chip that utilizes the proposed prediction engine is fabricated with UMC 0.18-mu CMOS 1P6 M technology. The prediction engine contains 79 K gates and 2.8 kb single-port on-chip SRAM, and occupies half of the whole chip area. When running at 1.5 MHz for QCIF 30 f/s real-time decoding, the prediction engine dissipates 268 muW at a 1.8-V power supply.     

Fast Interframe mode decision algorithm based on mode mapping and MB activity for MPEG-2 to H.264/AVC transcoding

Recently the latest video coding standard H.264/AVC is widely used for the mobile and low bitrate video codec in the various multimedia terminals. On the other hand, the MPEG-2 MP@HL codec has become the center of digital video contents since it is the standard codec for the Digital TV (DTV). To provide the bridge between the contents in MPEG-2 and mobile terminals, the transcoding of MPEG-2 contents into H.264/AVC format is an inevitable technology in the digital video market. The main bottleneck in the process lies in the computational complexity. In H.264/AVC, the variable block size (VBS) mode decision (MD) is used in the Interframe for the improved performance in the motion compensated prediction. For the macroblock (MB) which cannot be accurately predicted with one motion vector (MV), it is partitioned into smaller blocks and predicted with different MVs. In addition, SKIP and Intra modes are also permitted in the Interframe MD of H.264/AVC to further ameliorate the encoding performance. With the VBS MD technology, the Inter prediction accuracy can be improved significantly. However, the incidental side-effect is the high computational complexity. In this paper, we propose a fast Interframe MD algorithm for MPEG-2 to H.264/AVC transcoding. The relationships between SKIP and Intra modes are detected at first to map these two kinds of modes directly from MPEG-2 to H.264/AVC. And then the MB activity will be scaled by the residual DCT energy obtained from the MPEG-2 decoding process to estimate the block sizes of the MB mode for H.264/AVC Interframe MD. In our proposed method, the original redundant candidate modes can be eliminated effectively, resulting in the reduction of the computational complexity. It can reduce about 85% Rate-to-Distortion Cost (RDCost) computing and 45% entire processing time compared with the well-known cascaded transcoder while maintaining the video quality.     

Bandwidth Optimized and High Performance Interpolation Architecture in Motion Compensation for H.264/AVC HDTV Decoder

In this paper, we present high performance motion compensation architecture for H.264/AVC HDTV decoder. The bottleneck of efficient motion compensation implementation primarily rests on the high memory bandwidth demand and six-tap fractional interpolation complexity. To solve the bottleneck for H.264/AVC HD applications, three combined bandwidth optimization strategies are proposed to minimize the memory bandwidth for MB-based decoding process. To improve the interpolation hardware utilization and reduce the interpolation cycles, an interpolation classification scheme is proposed. By classifying the fifteen fractional pixels into five types and processing correspondingly, the interpolation cycles decrease significantly. A direct mapping memory cache characterized with circular addressing, byte-aligned addressing and horizontal and vertical parallel access is designed to support the proposed scheme. The hardware of proposed motion compensation is implemented at 100 M with 31.841 K logic gates, averagely 70–80% reduced memory bandwidth can be offered and the interpolation hardware can be fully utilized and interpolate one MB within 304 cycles, which can satisfy the real time constraint for H.264/AVC HD (1,920 × 1,088) 30 fps decoder. The design is implemented under UMC 0.18 μm technology, and the synthesis results and comparisons are shown.

Rate distortion optimization for H.264 interframe coding: a general framework and algorithms.

Rate distortion (RD) optimization for H.264 interframe coding with complete baseline decoding compatibility is investigated on a frame basis. Using soft decision quantization (SDQ) rather than the standard hard decision quantization, we first establish a general framework in which motion estimation, quantization, and entropy coding (in H.264) for the current frame can be jointly designed to minimize a true RD cost given previously coded reference frames. We then propose three RD optimization algorithms--a graph-based algorithm for near optimal SDQ in H.264 baseline encoding given motion estimation and quantization step sizes, an algorithm for near optimal residual coding in H.264 baseline encoding given motion estimation, and an iterative overall algorithm to optimize H.264 baseline encoding for each individual frame given previously coded reference frames-with them embedded in the indicated order. The graph-based algorithm for near optimal SDQ is the core; given motion estimation and quantization step sizes, it is guaranteed to perform optimal SDQ if the weak adjacent block dependency utilized in the context adaptive variable length coding of H.264 is ignored for optimization. The proposed algorithms have been implemented based on the reference encoder JM82 of H.264 with complete compatibility to the baseline profile. Experiments show that for a set of typical video testing sequences, the graph-based algorithm for near optimal SDQ, the algorithm for near optimal residual coding, and the overall algorithm achieve on average, 6%, 8%, and 12%, respectively, rate reduction at the same PSNR (ranging from 30 to 38 dB) when compared with the RD optimization method implemented in the H.264 reference software.