Electrical characteristics of highly reliable ultrathin hafniumoxide gate dielectric

Electrical and reliability properties of ultrathin HfO₂ have been investigated. Pt electroded MOS capacitors with HfO₂ gate dielectric (physical thickness ~45-135 Å and equivalent oxide thickness ~13.5-25 Å) were fabricated. HfO₂ was deposited using reactive sputtering of a Hf target with O₂ modulation technique. The leakage current of the 45 Å HfO₂ sample was about 1×10^-4 A/cm ² at +1.0 V with a breakdown field ~8.5 MV/cm. Hysteresis was <100 mV after 500°C annealing in N₂ ambient and there was no significant frequency dispersion of capacitance (<1%/dec.). It was also found that HfO₂ exhibits negligible charge trapping and excellent TDDB characteristics with more than ten years lifetime even at V_DD=2.0 V     

Furnace nitridation of thermal SiO2 in pureN2O ambient for ULSI MOS applications

Furnace nitridation of thermal SiO₂ in pure N₂ O ambient for MOS gate dielectric application is presented. N₂O-nitrided thermal SiO₂ shows much tighter distribution in time-dependent dielectric breakdown (TDDB) characteristics than thermal oxide. MOSFETs with gate dielectric prepared by this method show improved initial performance and enhanced device reliability compared to those with thermal gate oxide. These improvements are attributed to the incorporation of a small amount of nitrogen (~1.5 at.%) at the Si-SiO₂ interface without introducing H-related species during N₂O nitridation     

Transistor characteristics with Ta2O5 gatedielectric

As the gate oxide thickness decreases below 2 nm, the gate leakage current increases dramatically due to direct tunneling current. This large gate leakage current will be an obstacle to reducing gate oxide thickness for the high speed operation of future devices. A MOS transistor with Ta₂O₅ gate dielectric is fabricated and characterized as a possible replacement for MOS transistors with ultra-thin gate silicon dioxide. Mobility, I_d-V_d, I_d-V_g, gate leakage current, and capacitance-voltage (C-V) characteristics of Ta₂O₅ transistors are evaluated and compared with SiO₂ transistors. The gate leakage current is three to five orders smaller for Ta₂O₅ transistors than SiO₂ transistors     

Electrical characteristics of high quality La2O3 gate dielectric with equivalent oxide thickness of 5 Å

Electrical and reliability properties of ultrathin La₂O ₃ gate dielectric have been investigated. The measured capacitance of 33 Å La₂O₃ gate dielectric is 7.2 μF/cm² that gives an effective K value of 27 and an equivalent oxide thickness of 4.8 Å. Good dielectric integrity is evidenced from the low leakage current density of 0.06 A/cm² at -1 V, high effective breakdown field of 13.5 MV/cm, low interface-trap density of 3×10¹⁰ eV^-1/cm², and excellent reliability with more than 10 years lifetime even at 2 V bias. In addition to high K, these dielectric properties are very close to conventional thermal SiO₂      

Metal–Oxide–High-$kappa$ Dielectric–Oxide–Semiconductor (MOHOS) Capacitors and Field-Effect Transistors for Memory Applications

Metal-oxide-high-kappa dielectric-oxide-silicon capacitors and transistors are fabricated using HfO₂ and Dy₂O₃ high-kappa dielectrics as the charge storage layer. The programming speed of Al/SiO₂/Dy₂O₃/ SiO₂/Si transistor is characterized by a DeltaV _th shift of 1.0 V with a programming voltage of 12 V applied for 10 ms. As for retention properties, the Al/SiO₂/Dy₂O₃/ SiO₂/Si transistors can keep a DeltaV _th window of 0.5 V for 2 times10⁸ s. The corresponding numbers for Al/ SiO₂/HfO₂/SiO₂/Si transistors are 100 ms and 2 times10⁴ s, respectively. The better performance of the Al/SiO₂/Dy₂O₃/ SiO₂/Si transistors is attributed to the larger conduction band offset at the Dy₂O₃/SiO₂ interface.     

AlGaN/GaN Metal–Oxide–Semiconductor High-Electron Mobility Transistors Using Oxide Insulator Grown by Photoelectrochemical Oxidation Method

A photoelectrochemical oxidation method was used to directly grow oxide layer on AlGaN surface. The annealed oxide layer exhibited beta-Ga₂O₃ and alpha-Al₂O₃ crystalline phases. Using a photoassisted capacitance-voltage method, a low average interface-state density of 5.1 times 10¹¹ cm^-2. eV^-1 was estimated. The directly grown oxide layer was used as gate insulator for AlGaN/GaN MOS high-electron mobility transistors (MOS-HEMTs). The threshold voltage of MOS-HEMT devices is -5 V. The gate leakage currents are 50 and 2 pA at forward gate bias of VGS = 10 V and reverse gate bias of V_GS = -10 V, respectively. The maximum value of g_m is 50 mS/mm of VGs biased at -2.09 V.     

Nitridation and post-nitridation anneals of SiO2 forultrathin dielectrics

A technique of post-oxidation annealing to improve the properties and long-term reliability of ultrathin (<100 Å) MOS gate dielectrics is discussed. In this technique, after oxidation, nitridation is done in NH₃, followed by a light reoxidation in O₂, and then an inert anneal in Ar or N₂. Using this technique, both optimum performance and reliability can be obtained without sacrificing either. NH₃ anneal of SiO₂ improved the hot-electron immunity, but degraded the interface quality. Good properties could be obtained by a strong reoxidation of the nitrided films, at the expense, however, of a substantial increase in the film thickness. Nitrogen and argon ambients were found to be equally effective at improving film properties. By annealing the film in an inert ambient following reoxidation of the nitroxide, fixed charge can be further decreased with little oxide grown, electron mobility in NMOS FETs increases further, and the hot-electron lifetime is much longer than that of the starting oxide     

High-quality MOSFETs with ultrathin LPCVD gate SiO2

MOSFETs and MOS capacitors with ultrathin (65 Å) low-pressure chemical vapor deposition (LPCVD) gate SiO₂ have been fabricated and compared to those with thermal SiO₂ of identical thickness. Results show that the devices with LPCVD SiO₂ have higher transconductance and current drivability, better channel hot-carrier immunity, lower defect density, and better time-dependent dielectric breakdown (TDDB) characteristics than devices with conventional thermal SiO₂     

High-current small-parasitic-capacitance MOSFET on a poly-Siinterlayered (PSI:Ψ) SOI wafer

A new type of silicon-on insulator (SOI) structure has been fabricated by using direct bonding technology to bury multilayered films consisting of poly-Si and SiO₂. A device with an ideal epitaxial channel structure was fabricated using a conventional MOS process on this novel multilayered SOI (100-nm SOI/10-nm SiO₂/poly-Si/500-nm SiO₂) wafer. In this device, the highly concentrated p⁺ poly-Si just beneath the nMOS channel region acts as a punchthrough stopper, and the buried thin backgate oxide under the SOI layer acts as an impurity diffusion barrier, keeping the impurity concentration in the SOI film at its original low level. The device fabricated was an ultrathin SOI MOSFET capable of operating at a current 1.5 times that of conventional hundred-nm devices at low voltages     

Effects of minute impurities (H, OH, F) on SiO2/Siinterface as investigated by nuclear resonant reaction and electron spinresonance

The effects of minute amounts of impurities (H, OH, and F) in SiO ₂ are investigated to obtain a guideline for improving the reliability of MOS devices. To examine the behavior of hydrogen, deuterium (D) is adopted as a tracer. The quantity of deuterium dissolved in SiO₂ is measured by the D(³He,p)⁴He nuclear resonant reaction (NRR) technique. The Influence of the impurities on the SiO₂-Si interface structure is studied by electron spin resonance (ESR) measurement. Hot-carrier injection with MOS capacitors and transistors are examined to determine the effects of minute impurities on the electrical characteristics of gate SiO₂ and the correlation of this effect with the NRR and ESR experimental results. It was found that significant amounts of D₂O are diffused into SiO₂ , even at 200°C, and these dissolved D₂O molecules are eliminated at temperatures above 700°C. The number of unpaired bonds at the interface increases with decrease of dissolved water in SiO ₂. The disappearance of the interface traps after high-temperature annealing above 800°C is thought to be due to the viscous flow of SiO₂ and to the interface reoxidation. Reducing the hydrogen and relaxing the interface strain are essential for improving the MOS device endurance against hot carriers     

Design optimization of stacked layer dielectrics for minimum gate leakage currents

An effective model to evaluate the leakage currents for different stacked gates deep submicron MOS transistors is presented. For a given equivalent oxide thickness of a stacked gate, the gate leakage current decreases with an increase of high-k dielectric thickness or a decrease of interlayer thickness. Turning points at high gate biases of the I–V curves are observed for Si₃N₄/SiO₂, Ta₂O₅/SiO₂, Ta₂O₅/SiO_2−yN_y, Ta₂O₅/Si₃N₄, and TiO₂/SiO₂ stacked gates except for Al₂O₃/SiO₂ structure. Design optimization for the stacked gate architecture to obtain the minimum gate leakage current is evaluated.     

Low thermal-budget ultrathin NH3-annealedatomic-layer-deposited Si-nitride/SiO2 stack gate dielectricswith excellent reliability

We present novel ultrathin (EOT = 2.1 nm) atomic-layer-deposited (ALD) Si-nitride/SiO₂ stack gate dielectrics annealed in NH ₃ at a moderate temperature of 550°C. MOS capacitors are fabricated using the proposed dielectrics. Excellent performance in electrical stressing experiments is shown by the dielectrics. They also exhibit better interface quality, low bulk-trap density, low trap generation rate, and high long-term reliability in comparison with ALD Si-nitride/SiO₂ stack dielectrics without NH₃-annealing and conventional thermal SiO₂ dielectrics. The proposed stack-gate dielectrics appear to be very promising for ULSI devices     

Thin-gate SiO2 films formed by in situ multiple rapidthermal processing

A reliable method of forming very thin SiO₂ films (<10 nm) has been developed by rapid thermal processing (RTP) in which in situ multiple RTP sequences have been employed. Sub-10-nm-thick SiO₂ films formed by single-step RTP oxidation (RTO) are superior to conventional furnace-grown SiO₂ on the SiO₂ /Si interface characteristics, dielectric strength, and time-dependent dielectric-breakdown (TDDB) characteristics. It has been confirmed that the reliability of SiO₂ film can be improved by pre-oxidation RTP cleaning (RTC) operated at 700-900°C for 20-60 s in a 1%HCl/Ar or H₂ ambient. The authors discuss the dielectric reliability of the SiO₂ films formed by single-step RTO in comparison with conventional furnace-grown SiO₂ films. The effects and optimum conditions of RTC prior to RTO on the TDDB characteristics are demonstrated. The dielectric properties of nitrided SiO₂ films formed via the N₂O-oxynitridation process are described     

Low-temperature polysilicon TFT with two-layer gate insulator usingphoto-CVD and APCVD SiO2

The performance of polysilicon thin-film transistors (TFTs) formed by a 600°C process was improved using a two-layer gate insulator of photochemical-assisted vapor deposition (photo-CVD) SiO₂ and atmospheric-pressure chemical vapor deposition (APCVD) SiO₂. The photo-CVD SiO₂, 100 Å thick, was deposited on polysilicon and followed by APCVD SiO₂ of 1000 Å thickness. The TFT had a threshold voltage of 8.3 V and a field-effect mobility of 35 cm²/V-s, which were higher than those of the conventional TFT with a single-layer gate SiO₂ of APCVD. Hydrogenation by hydrogen plasma was more effective for the new TFT than for the conventional device     

Silicon–O–M–O–silicon superlattice

The success of heterojunction quantum wells and quantum dots in III–Vs has not been extended to silicon because the ideal barrier, SiO₂, is amorphous, preventing the formation of quantum structures with silicon. The possibility of a few monolayers of oxide inserted between adjacent silicon layers was proposed and realized with a superlattice (SL) structure consisting of Si–Si–O–Si–Si–Si, having a monolayer of oxygen in each period introduced by adsorption onto the 2×1 reconstructed surface along the Si(1 0 0). Reduction of the period leads to a slight up-shift of the energy of the emitted light, indicating that the essential objective of boosting the optical transition by promoting direct transitions has not been realized. Annealing in H₂+O₂ results in significant improvement in PL and EL, showing that specific defects, e.g., Si–O complexes may be responsible for the observed light emission. The role of Si–O complex being the origin of emission is further supported by the observation that the emission of visible light from polycrystalline Si and SiO₂ structure is similar to the epitaxial superlattice with oxygen. The computed strain in a new type of superlattices consisting of SiO₂, and GeO₂ is much lower than the Si–O SL. The EL in Si–O superlattice with the use of a Schottky barrier to provide electron–hole accumulation allows double injection into states higher in energy than the bandgap of Si, a prerequisite for injection laser without the need to use a wide-band pn-junction.     

Optimized silicon-rich oxide (SRO) deposition process for 5 V onlyflash EEPROM applications

A process for depositing in-situ very-thin (<10 nm) SiO₂ films on top of a silicon-rich oxide (SRO) layer in a standard low-pressure chemical vapor deposition (LPCVD) reactor has been optimized. Polysilicon-gate MOS capacitors using this stacked dielectric have shown high tunneling current at low voltages and an extraordinary endurance to electrical stress. Capacitors with 7 nm LPCVD SiO₂ on top of 10 nm SRO did not show any relevant shift on either the low or high portion of the I-V characteristic, after a fluence of more than 500 C/cm² at J=0.1 A/cm² . The results add further support to the usefulness of implementing these stacked dielectric structures in a variety of nonvolatile memory devices     

Modeling and simulation of stress-induced leakage current inultrathin SiO2 films

This paper presents a new model fur stress-induced leakage current (SILC) in ultrathin SiO₂ films, that is able to explain and accurately represent the experimental data obtained with MOS capacitors fabricated with different technologies and oxide thickness in the 3-7 nm range     

A new model of gate capacitance as a simple tool to extract MOSparameters

This paper tackles the difficult task to extract MOS parameters by a new model of the gate capacitance that takes into account both poly-Si depletion and charge quantization and includes temperature effects. A new fast and iterative procedure, based on this simplified self-consistent model, will be presented to estimate simultaneously the main MOS system parameters (oxide thickness, substrate, and poly-Si doping) and oxide field, surface potentials at the Si/SiO₂ and at the poly-Si/SiO₂ interfaces. Its effectiveness will be demonstrated by comparing oxide field and oxide thickness to those extracted by other methods proposed in the literature. Moreover, these methods are critically reviewed and we suggest improvements to reduce their errors. The agreement between CV simulation and experimental data is good without the need of any free parameter to improve the fitting quality for several gate and substrate materials combinations. Finally, a simple law to estimate substrate and poly-Si doping in n⁺/n ⁺ MOS capacitors from CV curves is proposed     

Effect of physical stress on the degradation of thinSiO2 films under electrical stress

In this work, we demonstrate that for ultrathin MOS gate oxides, the reliability is closely related to the SiO₂/Si interfacial physical stress for constant current gate injection (V_g^- ) in the Fowler-Nordheim tunneling regime. A physical stress-enhanced bond-breaking model is proposed to explain this. The oxide breakdown mechanism is very closely related to the Si-Si bond formation from the breakage of Si-O-Si bond, and that is influenced by the physical stress in the film. The interfacial stress is generated due to the volume expansion from Si to SiO₂ during the thermal oxidation, and it is a strong function of growth conditions, such as temperature, growth rate, and growth ambient. Higher temperatures, lower oxidation rates, and higher steam concentrations allow faster stress relaxation through viscous flow. Reduced disorder at the interface results in better reliability. Fourier transform infrared spectroscopy (FTIR) technique has been used to characterize stress in thin oxide films grown by both furnace and rapid thermal process (RTP). In conjunction with the Gibbs free energy theory, this model successfully predicts the trends of time-to-breakdown (t_bd) as a function of oxide thickness and growth conditions. The trends of predicted t_bd values agree well with the experimental data from the electrical measurement     

Carrier Transport in High-Mobility III–V Quantum-Well Transistors and Performance Impact for High-Speed Low-Power Logic Applications

DC and high-frequency device characteristics of In_0.7Ga_0.3As and InSb quantum-well field-effect transistors (QWFETs) are measured and benchmarked against state-of- the-art strained silicon (Si) nMOSFET devices, all measured on the same test bench. Saturation current (I_on) gam of 20% is observed in the In_0.7Ga_0.3As QWFET over the strained Si nMOSFET at (V_g - V_t) = 0.3 V, V_ds = 0.5 V, and matched I_off, despite higher external resistance and large gate-to-channel thickness. To understand the gain in I_on, the effective carrier velocities (v_eff) near the source-end are extracted and it is observed that at constant (V_g - V_t) = 0.3 V and V_ds = 0.5 V, the v_eff of In_0.7Ga_0.3As and InSb QWFETs are 4-5times higher than that of strained silicon (Si) nMOSFETs due to the lower effective carrier mass in the QWFETs. The product of v_eff and charge density (n_s), which is a measure of "intrinsic" device characteristics, for the QWFETs is 50%-70% higher than strained Si at low-voltage operation despite lower ns in QWFETs. Calibrated simulations of In_0.7Ga_0.3As QWFETs with reduced gate-to-channel thickness and external resistance matched to the strained Si nMOSFET suggest that the higher v_eff will result in more than 80% I_on increase over strained Si nMOSFETs at V_ds = 0.5 V, (V_g - V_t) = 0.3 V, and matched I_off, thus showing promise for future high-speed and low-power logic applications.