Asymmetric halo and symmetric Single‐Halo Dual‐Material Gate and Double‐Halo Dual‐Material Gate n‐MOSFETs characteristic parameter modeling

This paper presents an analytical subthreshold surface potential model of novel structures called asymmetric pocket‐implanted Double‐Halo Dual‐Material Gate (DHDMG) and Single‐Halo Dual‐Material Gate (SHDMG) Metal Oxide Semiconductor Field Effect Transistor (MOSFET), which combines the advantages of both the channel engineering (halo) and the gate engineering techniques (dual‐material gate) to effectively suppress the short‐channel effects (SCEs). The model is derived using the pseudo‐2D analysis by applying the Gauss's law to an elementary rectangular box in the channel depletion region, considering the surface potential variation with the channel depletion layer depth. The asymmetric pocket‐implanted model takes into account the effective doping concentration of the two linear pocket profiles at the source and the drain ends. The inner fringing field capacitances are also considered in the model for accurate estimation of the subthreshold surface potential at the two ends of the MOSFET. The same model is used to find the characteristic parameters for dual‐material gate with single‐halo and double‐halo implantations. It is concluded that the DHDMG device structure exhibits better suppression of the SCEs and the threshold voltage roll‐off than a pocket‐implanted and SHDMG MOSFET after investigating the characteristics parameter improvement. In order to validate our model, the modeled expressions have been extensively compared with the simulated characteristics obtained from the 2D device simulator DESSIS. A nice agreement is achieved with a reasonable accuracy over a wide range of device parameter and bias condition. Copyright © 2012 John Wiley & Sons, Ltd.     

Accurate prediction of the volume inversion impact on undoped Double Gate MOSFET capacitances

This paper demonstrates the capability of our previously published undoped Double‐Gate (DG) MOSFET explicit and analytical compact model to also forecast the effect of the volume inversion (VI) on the intrinsic capacitances. For that purpose, we present simulation results for these capacitances. We show now that the model presents an accurate dependence on the silicon layer thickness, consistent with two‐dimensional numerical simulations, for both thin and thick silicon films. As opposed to our previous work, here we test the capacitance model for three different film thicknesses and also show that the transition from VI regime to dual gate behaviour is well simulated. We demonstrate in this paper that even if the current drive and transconductance are enhanced in VI regime, our results show that intrinsic capacitances are higher as well, which may limit the high‐speed (delay time) behaviour of DG MOSFETs under VI regime. The good agreement between the numerical simulations and our model shows the high potential of our complete DG MOSFET model. Copyright © 2010 John Wiley & Sons, Ltd.     

Monte Carlo analysis of dynamic characteristics and high‐frequency noise performances of nanoscale double‐gate MOSFETs

In this paper, a full‐band Monte Carlo simulator is employed to study the dynamic characteristics and high‐frequency noise performances of a double‐gate (DG) metal–oxide–semiconductor field‐effect transistor (MOSFET) with 30 nm gate length. Admittance parameters (Y parameters) are calculated to characterize the dynamic response of the device. The noise behaviors of the simulated structure are studied on the basis of the spectral densities of the instantaneous current fluctuations at the drain and gate terminals, together with their cross‐correlation. Then the normalized noise parameters (P, R, and C), minimum noise figure (NF_min), and so on are employed to evaluate the noise performances. To show the outstanding radio‐frequency performances of the DG MOSFET, a single‐gate silicon‐on‐insulator MOSFET with the same gate length is also studied for comparison. The results show that the DG structure provides better dynamic characteristics and superior high‐frequency noise performances, owing to its inherent short‐channel effect immunity, better gate control ability, and lower channel noise. Copyright © 2012 John Wiley & Sons, Ltd.     

Investigation of multi‐layered‐gate electrode workfunction engineered recessed channel (MLGEWE‐RC) sub‐50 nm MOSFET: A novel design

In this paper, a two‐dimensional (2D) analytical sub‐threshold model for a novel sub‐50 nm multi‐layered‐gate electrode workfunction engineered recessed channel (MLGEWE‐RC) MOSFET is presented and investigated using ATLAS device simulator to counteract the large gate leakage current and increased standby power consumption that arise due to continued scaling of SiO₂‐based gate dielectrics. The model includes the evaluation of surface potential, electric field along the channel, threshold voltage, drain‐induced barrier lowering, sub‐threshold drain current and sub‐threshold swing. Results reveal that MLGEWE‐RC MOSFET design exhibits significant enhancement in terms of improved hot carrier effect immunity, carrier transport efficiency and reduced short channel effects proving its efficacy for high‐speed integration circuits and analog design. Copyright © 2008 John Wiley & Sons, Ltd.     

Development of 3‐D equivalent‐circuit modelling with decoupled L‐ILU factorization in semiconductor‐device simulation

In this paper, we develop a three‐dimensional (3‐D) device simulator, which combines a simplified, decoupled Gummel‐like method equivalent‐circuit model (DM) with levelized incomplete LU (L‐ILU) factorization. These complementary techniques are successfully combined to yield an efficient and robust method for semiconductor‐device simulation. The memory requirements are reduced significantly compared to the conventionally used Newton‐like method. Furthermore, the complex voltage‐controlled current source (VCCS) is simplified as a nonlinear resistor. Hence, the programming and debugging for the nonlinear resistor model is much easier than that for the VCCS model. Further, we create a connection‐table to arrange the scattered non‐zero fill‐ins in sparse matrix to increase the efficiency of L‐ILU factorization. Low memory requirements may pave the way for the widespread application in 3‐D semiconductor‐device simulation. We use the body‐tied silicon‐on‐insulator MOSFET structure to illustrate the capability and the efficiency of the 3‐D DM equivalent‐circuit model with L‐ILU factorization. Copyright © 2007 John Wiley & Sons, Ltd.     

Implementation of the symmetric doped double‐gate MOSFET model in Verilog‐A for circuit simulation

Recently we developed a model for symmetric double‐gate MOSFETs (SDDGM) that, for the first time, considers the doping concentration in the Si film in the complete range from 1×10¹⁴ to 3×10¹⁸ cm⁻³. The model covers a wide range of technological parameters and includes short channel effects. It was validated for different devices using data from simulations, as well as measured in real devices. In this paper, we present the implementation in Verilog‐A code of this model, which allows its introduction in commercial simulators. The Verilog‐A implementation was optimized to achieve reduction in computational time, as well as good accuracy. Results are compared with data from 2D simulations, showing a very good agreement in all transistor operation regions. Copyright © 2009 John Wiley & Sons, Ltd.     

Potential‐based threshold voltage and subthreshold swing models for junctionless double‐gate metal‐oxide‐semiconductor field‐effect transistor with dual‐material gate

On the basis of quasi‐two‐dimensional solution of Poisson's equation, an analytical threshold voltage model for junctionless dual‐material double‐gate (JLDMDG) metal‐oxide‐semiconductor field‐effect transistor (MOSFET) is developed for the first time. The advantages of JLDMDG MOSFET are proved by comparing the central electrostatic potential and electric field distribution with those of junctionless single‐material double‐gate (JLSMDG) MOSFET. The proposed model explicitly shows how the device parameters (such as the silicon thickness, oxide thickness, and doping concentration) affect the threshold voltage. In addition, the variations of threshold voltage roll‐off, drain‐induced barrier lowering (DIBL), and subthreshold swing with the channel length are investigated. It is proved that the device performance for JLDMDG MOSFET can be changed flexibly by adjusting the length ratios of control gate and screen gate. The model is verified by comparing its calculated results with those obtained from three‐dimensional numerical device simulator ISE. Copyright © 2015 John Wiley & Sons, Ltd.     

Continuity equation based nonquasi-static charge model for independent double gate MOSFET

Using the numerical device simulation we show that the relationship between the surface potentials along the channel in any double gate (DG) MOSFET remains invariant in QS (quasistatic) and NQS (nonquasi-static) condition for the same terminal voltages. This concept along with the recently proposed ‘piecewise charge linearization’ technique is then used to develop the intrinsic NQS charge model for a Independent DG (IDG) MOSFET by solving the governing continuity equation. It is also demonstrated that unlike the usual MOSFET transcapacitances, the inter-gate transcapacitance of a IDG-MOSFET initially increases with the frequency and then saturates, which might find novel analog circuit application. The proposed NQS model shows good agreement with numerical device simulations and appears to be useful for efficient circuit simulation.     

NEGF simulations of the effect of strain on scaled double gate nanoMOSFETs

The effect of biaxial strain on double gate (DG) nanoscaled Si MOSFET with channel lengths in the nanometre range is investigated using Non-Equilibrium Green’s Functions (NEGF) simulations. We have employed fully 2D NEGF simulations in order to answer the question at which body thickness the effects of strain is masked by the confinement impact. Following ITRS, we start with a 14 nm gate length DG MOSFET having a body thickness of 9 nm scaling the transistors to gate lengths of 10, 6 and 4 nm and body thicknesses of 6.1, 2.6 and 1.3 nm. The simulated I _D–V _G characteristics show a 6% improvement in the on-current for the 14 nm gate length transistor mainly due to the energy separation of the Δ valleys. The strain effect separates the 2 fold from the 4 fold valleys thus keeping mostly operational transverse electron effective mass in the transport direction. However, in the device with an extreme body thickness of 1.3 nm, the strain effect has no more impact on the DG performance because the strong confinement itself produces a large energy separation of valleys.     

Drain current model of double‐gate MOSFETs considering both electrons and holes

We present a rigorously derived current solution for undoped double‐gate (DG) MOSFETs with two carriers, which is based on surface potentials. The third‐order Newton–Raphson (NR) method is used to solve the surface‐potential equations resulting from the application of the boundary conditions to the general Poisson solution, with an initial guess very close to the true solution. The results demonstrate surface‐potential solutions for DG MOSFETs with 2–7 iterations to achieve an accuracy of 10⁻¹⁵. The drain current model for two carriers is presented as a benchmark to test the accuracy of one‐carrier current approximation. © 2014 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

Converter Using SiC‐MOSFET for Ultra‐High‐Speed Elevator

In this study, we developed a converter based on SiC (Silicon Carbide)‐MOSFET for use in ultra‐high‐speed elevators, with a reduced volume of 15% compared with the conventional converter. We succeeded in reducing the power loss of the converter unit by 56% compared to the conventional converter in one round trip under high temperature condition. Recently, because of their useful characteristics, wide‐gap semiconductors, such as SiC and GaN, have gained considerable attention for use in various applications in the power electronics systems. Therefore, we studied the use of a converter in elevator systems based on SiC‐MOSFET. We used a 1200 V/800 A SiC‐MOSFET module for the converter unit. We developed a prototype of the converter unit and the control panel by applying for the SiC‐MOSFET module for an ultra‐high‐speed elevator. As a result, the setting area of the control panel (main part) becomes less than 43% of the conventional panel. We tried to demonstrate the working of a 68‐kW elevator by applying the prototype control panel. Because of the characteristic of the switching loss of SiC‐MOSFET, the power loss of the converter unit has almost no dependence on temperature. An energy‐saving effect of approximately 17% was achieved in the total elevator system in one round trip under high‐temperature condition.     

Semi‐analytical non‐charge‐sheet and non‐depletion MOS model,for inversion charge calculation

A new computationally implemented semi‐analytic mathematical model is presented to obtain a more accurate estimation of the inversion charge in a MOS structure than standard models. The values of the error of the inversion charge obtained are compared with the assumed ‘exact’ numerical calculated values. These errors are appreciably smaller than the estimation coming from the classical charge‐sheet and depletion approximations. Also the calculation time to obtain the inversion charge is shown to be significantly lower than the numerical one. Because of its accuracy and its relatively low computational speed, the proposed model is a good alternative methodology for the calculation of the inversion charge of MOSFET transistors as a function of their physical features and gate bias voltage. In this sense it should be very useful to be implemented by computer‐aided design integrated circuit simulation software. Copyright © 2013 John Wiley & Sons, Ltd.     

An analytic drain current model for long‐channel undoped gate stack surrounding‐gate MOSFETs including interface fixed charges

On the basis of the exact solution of Poisson's equation and Pao–Sah double integral for long‐channel bulk MOSFETs, a continuous and analytic drain current model for the undoped gate stack (GS) surrounding‐gate (SRG) metal–oxide–semiconductor field‐effect transistor (MOSFET) including positive or negative interface fixed charges near the drain junction is presented. Considering the effect of the interface fixed charges on the flat‐band voltage and the electron mobility, the model, which is expressed with the surface and body center potentials evaluated at the source and drain ends, describes the drain current from linear region to saturation region through a single continuous expression. It is found that the surface and body center potentials are increased/decreased in the case of positive/negative interface fixed charges, respectively, and the positive/negative interface fixed charges can decrease/increase the drain current. The model agrees well with the 3D numerical simulations and can be efficiently used to explore the effects of interface fixed charges on the drain current of the gate stack surrounding‐gate MOSFETs of the charge‐trapped memory device. Copyright © 2013 John Wiley & Sons, Ltd.     

A 2‐D surface‐potential‐based threshold voltage model for short channel asymmetric heavily doped DG MOSFETs

In recent times, transistors with heavily doped body have generated much interest because of junctionless channel. In addition, proper threshold voltage regulation requires adjustment of the channel doping, as a result of which most of the compact models become invalid as they consider an intrinsic body. In this paper, a compact surface‐potential‐based threshold voltage model is developed for short channel asymmetric double‐gate metal–oxide–semiconductor field‐effect transistors with heavily/lightly doped channel. The 2‐D surface potential is computed and compared with Technology Computer Aided Design, and a relative error of 2–4 % was obtained. The threshold voltage is solved from 2‐D Poisson's equation using ‘virtual cathode’ method, and a good agreement is observed with the numerical simulations. Also, the model is compared with a reference model and a better result is obtained for heavily doped channel. Copyright © 2014 John Wiley & Sons, Ltd.     

Uncoupled mode space approach for analysis of nanoscale strained junctionless double-gate MOSFET

In this paper, we have analyzed the electrical characteristics of Strained Junctionless Double-Gate MOSFET (Strained JL DG MOSFET). A quantum mechanical transport approach based on non-equilibrium Green’s function (NEGF) method with the use of uncoupled mode space approach has been employed for this analysis. We have investigated the effects of high-\(\kappa \) materials as gate and spacer dielectrics on the device performance. Low OFF-state current, low DIBL, and low subthreshold slope have been obtained with increase in the gate and spacer dielectric constants. The electrical characteristics of strained JL DG MOSFET have also been compared with conventional JL DG MOSFET and Inversion Mode (IM) DG MOSFET. The results indicated that the Strained JL DG MOSFET outperforms the conventional JL and IM DG MOSFETs, yielding higher values of drain current.     

Selectivity and sensitivity enhancement methods for high‐data‐rate super‐regenerative receiver

This paper describes selectivity and sensitivity performance evaluations and improvement methods for an on–off keying super‐regenerative (SR) receiver. A slope‐controlled quasi‐exponential quench waveform, generated by a low‐complexity PVT‐tolerant quench generator circuit, is proposed to increase data rate and reduce the receiver 3‐dB bandwidth, thereby preventing oscillation caused by out‐of‐band injected signals and improving the receiver selectivity. The SR receiver sensitivity is also enhanced by a noise‐canceling front‐end topology with single‐ended to differential (S2D) signal converter. To exemplify these techniques, we designed an SR receiver with the proposed front‐end and quench waveform generator in a 0.18‐μm CMOS technology. Theoretical analyses and circuit simulations show 30% and 65% reduction in 3‐dB bandwidth of the SR receiver at 25 Mbps data rate by employing the proposed quench signal compared with piecewise‐linear and trapezoidal quench waveforms, respectively. Performance of the proposed front‐end is evaluated by a fast bit‐error‐rate estimation procedure, based on circuit noise simulations and statistical analyses, without the need for time‐consuming transient‐noise simulations. Accuracy of the procedure has been verified by comparing its results with transient‐noise simulations. According to the estimated bit‐error‐rate curves, the noise‐canceling topology with S2D converter enhances the SR receiver sensitivity by 9 dB. Copyright © 2017 John Wiley & Sons, Ltd.     

Device‐partition method using equivalent circuit model in two‐dimensional device simulation

In order to accomplish two‐dimensional device simulation with a large number of nodes, in this paper we propose the device‐partition method (DPM) to resolve the problem that the memory size of the simulation environment is insufficient. The idea of DPM is that the device can be divided into several parts and a matrix solver only solves one part at a time. DPM uses the iteration method to simulate the device. By continuous iteration, an accurate solution can be obtained. Hence, we use DPM to demonstrate the simulations of the MOSFET and the CMOS inverter. The simulation results of DPM and the coupled method (CM) are nearly approximate and correspond with the theory. Hence, DPM is a suitable method to develop a powerful simulation environment. Copyright © 2005 John Wiley & Sons, Ltd.     

Device circuit co‐design to reduce gate leakage current in VLSI logic circuits in nano regime

In this paper, nanoscale metal–oxide–semiconductor field‐effect transistor (MOSFET) device circuit co‐design is presented with an aim to reduce the gate leakage curren t in VLSI logic circuits. Firstly, gate leakage current is modeled through high‐k spacer underlap MOSFET (HSU MOSFET). In this HSU MOSFET, inversion layer is induced in underlap region by the gate fringing field through high‐k dielectric (high‐k) spacer, and this inversion layer in the underlap region acts as extended source/drain region. The analytical model results are compared with the two‐dimensional Sentaurus device simulation. Good agreement is obtained between the model and Sentaurus simulation. It is observed that modified HSU MOSFET had improved off current, subthreshold slope, and drain‐induced barrier lowering characteristics. Further, modified HSU MOSFET is also analyzed for gate leakage in generic logic circuits. Copyright © 2015 John Wiley & Sons, Ltd.     

Design of current‐mode MOSFET‐C filters using OTRAs

In this paper, third‐order current‐mode MOSFET‐C filters that use operational transresistance amplifiers (OTRAs) with little parasitic capacitance effects are presented. On the basis of the proposed systematic method and design procedure, we can efficiently synthesize third‐order active filters with OTRAs along with simplified MOSFET resistor circuits, and all virtually grounded capacitors. Third‐order current‐mode Chebychev low‐pass and high‐pass filters are realized to verify the validity of the theoretical analysis. Experimental results employing commercially available current feedback amplifiers are also given. Copyright © 2008 John Wiley & Sons, Ltd.     

An analytical model of triple‐material double‐gate metal–oxide–semiconductor field‐effect transistor to suppress short‐channel effects

This paper presents an analytical subthreshold model for surface potential and threshold voltage of a triple‐material double‐gate (DG) metal–oxide–semiconductor field‐effect transistor. The model is developed by using a rectangular Gaussian box in the channel depletion region with the required boundary conditions at the source and drain end. The model is used to study the effect of triple‐material gate structure on the electrical performance of the device in terms of changes in potential and electric field. The device immunity against short‐channel effects is evaluated by comparing the relative performance parameters such as drain‐induced barrier lowering, threshold voltage roll‐off, and subthreshold swing with its counterparts in the single‐material DG and double‐material DG metal–oxide–semiconductor field‐effect transistors. The developed surface potential model not only provides device physics insight but is also computationally efficient because of its simple compact form that can be utilized to study and characterize the gate‐engineered devices. Furthermore, the effects of quantum confinement are analyzed with the development of a quantum‐mechanical correction term for threshold voltage. The results obtained from the model are in close agreement with the data extracted from numerical Technology Computer Aided Design device simulation. Copyright © 2015 John Wiley & Sons, Ltd.