105 nm Gate length pMOSFETs with high-K and metal gate fabricated in a Si process line on 200 mm GeOI wafers

We report on the fabrication and electrical characterization of deep sub-micron (gate length down to 105 nm) GeOI pMOSFETs. The Ge layer obtained by hetero-epitaxy on Si wafers has been transferred using the Smart Cut^TM process to fabricate 200 mm GeOI wafers with Ge thickness down to 60–80 nm. A full Si MOS compatible pMOSFET process was implemented with HfO₂/TiN gate stack. The electrical characterization of the fabricated devices and the systematic analysis of the measured performances (I_ON, I_OFF, transconductance, low field mobility, S, DIBL) demonstrate the potential of pMOSFET on GeOI for advanced technological nodes. The dependence of these parameters have been analyzed with respect to the gate length, showing very good transport properties (μ_h ～ 250 cm²/V/s, I_ON = 436 μA/μm for L_G = 105 nm), and OFF current densities comparable or better than those reported in the literature.     

Impact of gate material engineering(GME) on analog/RF performance of nanowire Schottky-barrier gate all around (GAA) MOSFET for low power wireless applications: 3D T-CAD simulation

In this paper Gate Material Engineered (GME) Gate-Stack (GS) silicon nanowire Schottky-Barrier (SB) Gate All Around (GAA) MOSFET and Single Material Gate Stack Schottky-Barrier Source/Drain Gate All Around (SM-GS-SB-S/D GAA) structures are proposed for low- power wireless applications. The Analog/RF performance for wireless applications of these devices are demonstrated. The effect of Schottky-Barrier (Metal) S/D is studied for Single Metal (SM)–SB-GAA, (Dual Metal) DM-SB-GAA, SM-GS-SB-GAA and GME-GS-SB-GAA MOSFETs, and it is found that GME-GS-SB-GAA MOSFET with metal drain source shows much improved performance in terms of transconductance (g_m), output conductance (g_d), Early Voltage (V_EA), Maximum Transducer Power Gain, cut-off frequency (f_T), and I_on/I_off ratio. Further, harmonic distortion for wireless applications is also studied using ATLAS-3D device simulator. Due to low parasitic S/D resistance the metal Source/Drain DM-GS-SB-S/D-GAA MOSFET demonstrates remarkable I_on of~31.8 μA/μm and saturation transconductance g_m of~68.2 μS with improved third order derivative of transconductance g_m3.     

Impact of high-k gate dielectric on analog and RF performance of nanoscale DG-MOSFET

Now a days, high-k dielectrics have been investigated as an alternative to Silicon dioxide (SiO₂) based gate dielectric for nanoscale semiconductor devices. This paper is an attempt to characterize the analog and RF performance of the high-k metal gate (HKMG) double gate (DG) metal oxide semiconductor field effect transistor (MOSFET) in nanoscale through 2-D device simulation. The results demonstrates the impact of high-k oxide layer as single and gate stack (GS). The key idea behind this investigation is to provide a physical explanation for the improved analog and RF performance exhibited by the device. The major figures of merit (FOMs) studied in this paper are transconductance (g_m), output conductance (g_d), transconductance generation factor (g_m/I_D), early voltage (V_EA), intrinsic gain (A_V), cut off frequency (f_T), transconductance frequency product (TFP), gain frequency product (GFP) and gain transconductance frequency product (GTFP). The effects of downscaling of channel length (L) on analog performance of the proposed devices have also been presented. It has been observed that the performance enhancement of GS configurations (k=7.5 i.e device D5 in the study) is encouraging as far as the nanoscale DG-MOSFET is concerned. Also it significantly reduces the short channel effects (SCEs). Parameters like DC gain of (91.257 dB, 43.436 dB), nearly ideal values (39.765 V⁻¹, 39.589 V⁻¹) of TGF, an early voltage of (2.73 V, 16.897 V), cutoff frequency (294 GHz, 515.5 GHz) and GTFP of (5.14×10⁵ GHz/V, 1.72×10⁵ GHz/V) for two different values of V_DS=0.1 V and 0.5 V respectively are found to be close to ideal values. Analysis shows an opportunity for realizing high performance analog and RF circuits with the device proposed in this paper i.e. device D5.     

Impact of the lateral straggle on the Analog and RF performance of TFET

In this work, the effect of the variation in lateral straggle on TFETs performance is demonstrated. The ion implantation technique during fabrication process causes the extension of dopants from source/drain region towards the channel. Even though the use of non-zero tilt angle at the time of ion implantation is necessary to avoid the channeling effect, however, series resistance, threshold voltage roll offs, switching speed and effective channel length of the device get affected by the non abrupt doping profile at the source/drain-body junction. It is established earlier that TFET is very convenient for Analog/RF application owing to its below 60 mV/decade subthreshold swing and reduced short channel effects. In order to show the effect of lateral straggle on TFET’s performance, various Analog figure of merits (FOMs) such as drain current (I_d), transconductance (g_m), transconductance generation factor (g_m/I_d), output resistance (R_o), intrinsic gain (g_mR_o) and RF figure of merits (FOMs) like unity gain cutoff frequency (f_T), transit frequency of maximum available power gain (f_MAX) are investigated for the variation in straggle parameter from 0 nm to 5 nm in order to optimize the device performance. The circuit performance of the device for different lateral straggle is carried out using common source amplifier.     

Impact of source-to-drain tunnelling on the scalability of arbitrary oriented alternative channel material nMOSFETs

In this work, the scalability of alternative channel material double gate nano nMOSFETs has been investigated by the mean of semi-analytical models of I_on/I_off currents, accounting for quantum capacitance degradation, short channel effects, band-to-band and source-to-drain tunnelling in arbitrary substrate and channel direction.Contrary to most of the previous study neglecting source-to-drain tunnelling, it has been found that for devices with physical gate length below 13 nm (as required in the 22 and 16 nm nodes), this mechanism significantly penalises the I_on/I_off trade off of small effective masses channel materials like Ge or GaAs, much more than in the case of Si and biaxially strained Si (s-Si). In addition, only strained Si-MOSFETs has been found to meet the performance expectation of the International Technology Roadmap of Semiconductor for the 22 nm and 16 nm technological nodes.     

Performance assessment of (1 1 0) p-FET high-κ/MG: is it mobility or series resistance limited?

In this article the impact of Si-substrate orientation on mobility performance is studied for p-MOSFET’s with both HfSiON and SiON based dielectrics. Consistent with previous studies, the I_on at fixed I_off is 100% larger for Si(1 1 0) larger than for standard Si(1 0 0). A thorough analysis of the factors influencing I_on (EOT, mobility and R_series) for short channel devices (until L_met = 80 nm) indicates that a 200% increase of the mobility at high V_g is the source of this performance enhancement. The lower I_on increase (only 100%) compared to what is expected from the mobility is only explained by a larger impact of the R_series (70% of the total resistance) for short channel devices. As a result additional room for I_on improvement can be reached by device and R_series optimization.     

The influence of junction depth on short channel effects in vertical sidewall MOSFETs

This work addresses a fundamental problem of vertical MOSFETs, that is, inherently deep junctions that exacerbate short channel effects (SCEs). Due to the unconventional asymmetric junction depths in vertical MOSFETs, it is necessary to look separately at the electrostatic influence of each junction. In order to suppress short channel effects better, we explore the formation of a shallow drain junction. This is realized by a self-aligned oxide region, or junction stop (JS) which is formed at the pillar top and acts as a diffusion barrier for shallow junction formation. The benefits of using a JS structure in vertical MOSFETs are demonstrated by simulations which show clearly the effect of asymmetric junctions on SCEs and bulk punch-through. A critical point is identified, where control of SCEs by junction depth is lost and this leads to appropriate junction design in JS vertical sidewall MOSFETs. For a 70 nm channel length the JS structure improves charge sharing by 54 mV and DIBL by 46 mV. For body dopings of 5.0 × 10¹⁷ cm^?3 and 6.0 × 10¹⁷ cm^?3 the JS gives improvements in I_off of 58.7% and 37.8%, respectively, for a given I_on. The inclusion of a retrograde channel gives a further increase in I_on of 586 μA/μm for a body doping of 4.0 × 10¹⁸ cm^?3.     

Investigation and comparison of analog figures-of-merit for TFET and FinFET considering work-function variation

This paper investigates and compares the impacts of metal-gate work-function variation on important analog figures-of-merit (FOMs) for TFET and FinFET devices using 3-D atomistic TCAD simulations. Our study indicates that, at 0.6 V supply voltage and 0.2 V gate-voltage overdrive, TFET exhibits superior variation immunity regarding transconductance to drain–current ratio (g_m/I_DS), output resistance (R_out) and intrinsic gain, and comparable variability in g_m and cutoff frequency (f_T) as compared with the FinFET counterparts. In addition, how the correlations between pertinent parameters (e.g., g_m and R_out) impact the variation immunity of important analog FOMs are analyzed. Our study may provide insights for low-voltage analog design using TFET/FinFET technologies.     

A new method to simulate random dopant induced threshold voltage fluctuations in sub-50 nm MOSFET’s with non-uniform channel doping

In this paper, based on a precise and efficient analytical function of relatively realistic dopant fluctuations, a new method is proposed to simulate the threshold voltage variation of MOSFET’s with non-uniform channel doping due to random dopant fluctuations. Both the number and position fluctuations of dopants are taken into account. Using this method, 2500 microscopically different devices under certain process conditions that cover the range of channel length L from 35 nm to 90 nm, oxide thickness T_ox from 1 nm to 4 nm and channel surface doping concentration N_A from 1 × 10¹⁸ to 5 × 10¹⁸ cm⁻³ are simulated to show how our method works.     

Analysis of nanometer-scale InGaAs/InAs/InGaAs composite channel MOSFETs using high-K dielectrics for high speed applications

The outstanding electron transport properties of InGaAs and InAs semiconductor materials, makes them attractive candidates for future nano-scale CMOS. In this paper, the ON state and OFF state performance of 30 nm gate length InGaAs/InAs/InGaAs buried composite channel MOSFETs using various high-K dielectric materials is analyzed using Synopsys TCAD tool. The device features a composite channel to enhance the mobility, an InP spacer layer to minimize the defect density and a heavily doped multilayer cap. The simulation results show that MOSFETs with Al₂O₃/ZrO₂ bilayer gate oxide exhibits higher gm/I_D ratio and lower sub threshold swing than with the other dielectric materials. The measured values of threshold voltage (V_T), on resistance (R_ON) and DIBL for Lg = 30 nm In_0.53Ga_0.47As/InAs/In_0.53Ga_0.47As composite channel MOSFET having Al₂O₃/ZrO₂ (EOT = 1.2 nm) bilayer dielectric as gate oxide are 0.17 V, 290 Ω-µm, and 65 mV/V respectively. The device displays a transconductance of 2 mS/µm.     

Improved device variability in scaled MOSFETs with deeply retrograde channel profile

Continued scaling of transistor has resulted in severe short channel effects and transport degradation. In addition, variability in deeply scaled transistor such as threshold voltage (V_TH) variability has emerged as a major challenge for circuit and device design. Although various techniques have been suggested to alleviate these problems, such as CMOS on FDSOI or 3D transistors, they are expensive and complicated to manufacture. Recently, MOSFETs with deeply retrograde channel profile have been suggested as a mean to obtain good device characteristics on bulk substrate. In this work, V_TH variability impact of RDF on 65 nm-node deeply retrograde MOSFETs and conventional planar bulk MOSFETs were studied by using TCAD simulation. The simulated results showed that the deeply retrograde MOSFETs have 5 mV lower σ-V_TH (ΔA_VT between two devices is 1.06  mV·μm) than conventional planar bulk MOSFETs at the same I_off level (0.2 nA/μm). The ideal BOX profile structure simulated results showed that the thinner the low doping surface layer for deeply retrograde MOSFETs, the higher the V_TH variability. Our finding suggest that deeply retrograde MOSFETs are inherently less sensitive to V_TH variability due to RDF and channel length than conventional planar bulk MOSFETs and can be feasible for post-CMOS technology.     

DC and microwave characteristics of Lg 50 nm T-gate InAlN/AlN/GaN HEMT for future high power RF applications

The DC and microwave characteristics of L_g = 50 nm T-gate InAlN/AlN/GaN High Electron Mobility Transistor (HEMT) on SiC substrate with heavily doped n+ GaN source and drain regions have demonstrated using Synopsys TCAD tool. The proposed device features an AlN spacer layer, AlGaN back-barrier and SiN surface passivation. The proposed HEMT exhibits a maximum drain current density of 1.8 A/mm, peak transconductance (g_m) of 650 mS/mm and ft/fmax of 118/210 GHz. At room temperature, the measured carrier mobility, sheet charge carrier density (n_s) and breakdown voltage are 1195 cm²/Vs, 1.6 × 10¹³ cm⁻² and 18 V respectively. The superlatives of the proposed HEMTs are bewitching competitor for future monolithic microwave integrated circuits (MMIC) applications particularly in W-band (75–110 GHz) high power RF applications.     

Drivability improvement in Schottky barrier source/drain MOSFETs with strained-Si channel by Schottky barrier height reduction

Due to an extra barrier between source and channel, the drivability of Schottky barrier source/drain MOSFETs (SBMOSFETs) is smaller than that of conventional transistors. To reach the drivability comparable to the conventional MOSFET, the Schottky barrier height (SBH) should be lower than a critical value. It is expected that SBH can be effectively reduced by a bi-axially strain on Si. In this letter, p-channel MOSFETs with PtSi Schottky barrier source/drain, HfAlO gate dielectric, HfN/TaN metal gate and strained-Si channel are demonstrated for the first time using a simplified low temperature process. Devices with the channel length of 4 μm have the drain current of 9.5 μA/μm and the transconductance of 14 μS/μm at V_gs − V_th = V_ds = −1 V. Compared to the cubic Si counterpart, the drain current and the transconductance are improved up to 2.7 and 3.1 times respectively. The improvement is believed to arising from the reduced barrier height of the PtSi/strained-Si contact and the enhanced hole mobility in the strained-Si channel.     

Effect of gate length in InAs/AlSb HEMTs biased for low power or high gain

The effect of gate-length variation on DC and RF performance of InAs/AlSb HEMTs, biased for low DC power consumption or high gain, is reported. Simultaneously fabricated devices, with gate lengths between 225 nm and 335 nm, have been compared. DC measurements revealed higher output conductance g_ds and slightly increased impact ionization with reduced gate length. When reducing the gate length from 335 nm to 225 nm, the DC power consumption was reduced by approximately 80% at an f_T of 120 GHz. Furthermore, a 225 nm gate-length HEMT biased for high gain exhibited an extrinsic f_T of 165 GHz and an extrinsic f_max of 115 GHz, at a DC power consumption of 100 mW/mm. When biased for low DC power consumption of 20 mW/mm the same HEMT exhibited an extrinsic f_T and f_max of 120 GHz and 110 GHz, respectively.     

A 2D compact model for lightly doped DG MOSFETs (P-DGFETs) including negative bias temperature instability (NBTI) and short channel effects (SCEs)

In this paper, a 2D compact model for potential and threshold voltage for lightly doped symmetrical double gate (DG) p-channel MOSFETs (PMOS) including negative bias temperature instability (NBTI) and short channel effects (SCEs) is presented. The model is dedicated to nano scale MOSFETs below 30 nm. In this model, both effects of interface state generation and hole-trapping are considered. Moreover, the effects of scaling down the oxide thickness and the channel thickness on NBTI are discussed. Our model is matched very well with numerical simulations obtained from COMSOL multi-physics at different drain voltages (V_d). A 4% shift in threshold voltage roll-off and 47% shift in drain induced barrier lowering (DIBL) is achieved at a gate length of 10 nm after 10 years of operation at a frequency of 1 GHz.     

Degradation of pMOSFETs due to hot electron induced punchthrough

This paper proposes a method which can separate the parasitic effect from the drain current I_d vs. gate voltage V_g curves of MOSFETs, then uses this method to analyze degradation of experimental pMOSFETs due to hot-electron-induced punchthrough (HEIP). An I_d vs. V_g curve of the parasitic MOSFET formed by a shallow trench isolation (STI) is obtained by extrapolating the line of I_d vs. channel width W at each V_g to W = 0 μm. The I_d vs. V_g curves of the parasitic MOSFET indicate that HEIP caused electron trapping at the interface between SiN and the sidewall oxide of STI, but the curves of the main MOSFET indicate that HEIP caused negative oxide charges and positive interface traps in the channel region. These charges and traps decreased the threshold voltage V_th of the parasitic MOSFET but increased V_th of the main MOSFET. These two opposite behaviors of V_th resulted in little HEIP-induced shift of V_th at W = 2.5 μm. | V_d | to secure ten-year HEIP lifetime of 10% shift of V_th was ≤ 2.2 V at W = 0.3 μm, ≤ 3.5 V at W = 1.0 μm, and ≤ 3.6 V at W = 10 μm; these changes indicate that degradation of parasitic MOSFET influences the HEIP lifetime of narrow pMOSFET significantly.     

Underlap channel metal source/drain SOI MOSFET for thermally efficient low-power mixed-signal circuits

In this paper it has been shown that employing an underlap channel created by varying the lateral doping straggle in dopant-segregated Schottky barrier SOI MOSFET not only improves the scalability but also suppresses the self-heating effect of this device. Although in strong inversion region the reduced effective gate voltage due to voltage drop across the underlap lengths reduces the drive current, in weak/moderate inversion region defined at I_D=5 μA/μm and V_DS=0.5 V the analog figures of merit such as transconductance, transconductance generation factor and intrinsic gain of the proposed underlap device are improved by 15%, 35% and 20%, respectively over the conventional overlap channel structure. In addition to this, at V_DD=0.5 V the gain-bandwidth product in a common-source amplifier based on proposed underlap device is improved by ～20% over an amplifier based on the conventional overlap channel device. The mixed-mode device/circuit simulation results of CMOS inverter, NAND and the NOR gates based on these devices also show that at V_DD=0.5 V the switching energy, static power dissipation and the propagation delay in the case of proposed underlap device are reduced by ～10%, ～35% and ～25%, respectively, over the conventional overlap device. Thus, significant improvement in analog figures of merit and the reduction in digital design metrics at lower supply voltage show the suitability of the proposed underlap device for low-power mixed-signal circuits.     

Sensitivity of trigate MOSFETs to random dopant induced threshold voltage fluctuations

In this paper, we investigate random doping fluctuation effects in trigate SOI MOSFETs by solving the three-dimensional (3D) Poisson, drift-diffusion and continuity equations numerically. A single doping impurity atom is introduced in the undoped channel region of the device and the resulting shift of threshold voltage is measured from the simulated I–V characteristics. This enables the derivation of the threshold voltage shift (ΔV_TH) for any arbitrary location of the doping atom in the transistor. Based on an analysis of a sub-20 nm trigate MOSFET device, we find that the typical variation of V_TH per doping atom is a few tens of mV. Inversion-mode (IM) trigate devices are more sensitive to the doping fluctuation effects than accumulation-mode (AM) devices. The threshold voltage shift arising from doping fluctuations is maximum when the doping atom is near the center of the channel region, which means the original SOI film doping, the random contamination effects or any other impurity doping in the channel region is more important than atoms introduced in the channel by the S/D implantation process for sub-20 nm transistors.     

Microwave performance of field-plate 0.13-μm MOS transistors with varying field-plate extension

Si-based field-plate 0.13 μm gate length metal-oxide-semiconductor field effect transistor (Si MOSFET) with field-plate (FP) lengths of 0.1 μm, 0.2 μm, and 0.3 μm have been fabricated and investigated. The field-plate metals were connected to gate electrode in this study to improve device gate resistance (R_g) resulting in the better microwave performance. By increasing the length of field-plate metal extension (L_FPE), the off-state drain-to-source surface leakage current can be suppressed. Besides, low surface traps in FP NMOS also leads to a higher drain-to-source current (I_ds) especially at high current regime compared to standard device. The power added efficiency (PAE) was 56.3% for L_FPE of 0.3 μm device, and these values where 54.7% and 53.8% for L_FPE of 0.2 μm and 0.1 μm devices, respectively. Wider field-plate metal extension exhibits highly potential for low noise amplifier and high efficiency power amplifier applications.     

Comprehensive effects of strained Ge1−xSnx and device layout arrangement on a nano-scale Ge-based PMOSFET with a short channel

Layout patterns, including salient gate width and dummy active diffusion region (dummy OD), significantly influence the carrier mobility gain of nano scale devices. Germanium (Ge)-based devices with Ge–tin (GeSn) alloy embedded in the source/drain (S/D) regions have been regarded a promising candidate for higher channel mobility. Second-order piezoresistance coefficients were used to estimate the carrier mobility gain within the desired Ge-based device channel. A 20 nm Ge-based p-type metal oxide semiconductor field effect transistor with 100 nm gate width and 100 nm dummy OD width was selected to explore the layout effect of the short channel device. The device consisted of S/D region Ge_1−xSn_x alloy, compressive-stressed contact etch stop layer, and deposited shallow trench isolation with different process-induced stress magnitudes. Maximum carrier mobility gain of 93.65% was obtained when a 10 nm narrow distance between OD and dummy OD was achieved.