Electrical overstress and electrostatic discharge

Semiconductor devices have a limited ability to sustain electrical overstress (EOS). The device susceptibility to EOS increases as the device is scaled down to submicron feature size. At present, EOS is a major cause for IC failures. Published reports indicate that nearly 40% of IC failures can be attributed to EOS events. Hence, EOS threats must be considered early in the design process. For semiconductor devices, EOS embodies a broad range of electrical threats due to electromagnetic pulses, electrostatic discharge (ESD), system transients, and lightning. EOS-related failures in semiconductor devices can be classified according to their primary failure mechanisms into: thermally-induced failures, electromigration, electric-field-related failures. In general, thermally-induced failures are related to the doping level, junction depth, and device characteristic-dimensions whereas electric-field induced failures are primarily related to the breakdown of thin oxides in MOS devices     

NMOS器件ESD特性模拟

NMOS管I-V曲线在ESD(electrostatic discharges)脉冲电流作用下呈现出反转特性,其维持电压VH、维持电流IH、触发电压VB、触发电流IB以及二次击穿电流等参数将会影响NMOS管器件的抗ESD能力。文章通过采用SILVACO软件,对1.0μm工艺不同沟长和工艺条件的NMOS管静电放电时的峰值电场、晶格温度以及VH进行了模拟和分析。模拟发现,在ESD触发时,增加ESD注入工艺将使结峰值场强增强,VH减小、VB减小,晶格温度降低;器件沟长和触发电压VB具有明显正相关特性,但对VH基本无影响。最后分析认为NMOS管ESD失效主要表现为高电流引起的热失效,而电场击穿引起的介质失效是次要的。     

A surge-free intelligent power device specific to automotive highside switches

A novel type of intelligent power device (IPD), which is suitable for automotive monolithic high side switch with high current capability, is presented. An integration of a vertical-power DMOSFET and planar MOS IC devices is performed by the newly developed junction-isolation technique using only one epitaxial growth. The isolation voltage of 80 V has been obtained, which is large enough for automotive IPDs if they are protected against high voltage transients on the battery line. A rugged vertical DMOSFET (VDMOS) has also been developed for this IPD. It has a cellular Zener diode between its source and drain, which prevents the secondary breakdown of parasitic bipolar transistor, and the resulting avalanche capability enhancement is more than an order of magnitude. This VDMOS is used for both output power device and protection device for low-voltage MOS circuitry, which makes the IPD free from any transients in the automobile without the need for external protection     

Analysis and modeling of a digital CMOS circuit operation and reliability after gate oxide breakdown: a case study

A CMOS ring oscillator circuit is observed to operate even after a number of its FET's have undergone a hard gate oxide breakdown. The first breakdown is identified with emission microscopy and statistical tools to most likely occur in the circuit's nFET's. A physical model and an equivalent electrical circuit for an nFET after hard gate oxide breakdown are constructed and used to confirm the understanding of the impact of FET gate oxide breakdown on the ring oscillator. The observations are generalized to conclude that, provided stable soft breakdowns are the only gate oxide failures occurring at operating conditions, large parts of digital CMOS circuits will be unaffected by these failures.     

Field failure analysis on transmission data equipment due to lightning discharges

The telecommunication equipments suffer more damages, dues to lightning and power lines induction, than other type of appliances. The cause is that they have direct connections with wires or cables that are exposed to transients, and usually the affected components have direct connections with external lines, but sometimes the mechanism is more subtle and can affect circuits without contact with exposed connections.This paper treats about failures on data interfaces circuits induced by voltage transients on the earth protection wire. It is based on a study of modems failures connected to remotes data terminals through RS-232 interfaces. Other data interface could also be damaged by this mechanism of failure (RS-422, Ethernet, Token Ring, etc.).On this type of failure the failed circuits (drivers and receivers RS-232) are not located nearly the transient entry gate (telephone line and VAC inputs). They are in an interface between two equipments, and usually the only failed components are the drivers and receivers.     

Impact of active thermal management on power electronics design

Power electronic system design is typically constrained by the thermal limitation so by the overall losses and the peak current. To stay within the maximum current, reached only during transients, the system is typically overrated. Active thermal management is used to control the maximum temperature and the temperature swing to reduce failures that are mostly caused by them. In this paper it is proposed to use the active thermal management to reduce the switching losses or to move them to less stressed devices, during transients, such as a module can reach an higher current, without violating thermal constraints, and the need of overdesign can be reduced. Hence an optimal and cost effective design of power electronics system is achieved.     

Gate protection of MIS devices

Gate shorts caused by electrical breakdown of the gate dielectric are a major yield and reliability problem for MOS transistors and integrated circuits. Diodes or diffused resistors with breakdown voltages of about 40 V can be used to protect the gate from high voltage transients or static discharges. This paper provides a uniform approach to gate protection. It is shown theoretically that in order to obtain effective gate protection: the protecting device should have a low dynamic resistance in breakdown; the breakdown voltage of the protecting device should be above, but close to, the maximum gate operating voltage; and protection by a diffused resistor in series with the gate is much more effective than by a diode in parallel with the gate. It is shown experimentally that, compared to the widely used fieldplate-induced breakdown, breakdown due to reach-through to a highly doped substrate provides: a dynamic resistance that is almost two orders of magnitude lower; reasonable control of the breakdown voltage; much better protection against simulated static discharges. Since under pilot line conditions no adverse effects on performance or yield have been observed, reach-through breakdown devices seem to improve gate protection decisively without any coincident disadvantages.     

Effect of System Processes on Error Repetition: A Probabilistic and Measurement Approach

This paper presents an approach to system reliability modeling where failures and errors are not statistically independent. The repetition of failures and errors until their causes are removed is affected by the system processes and degrades system reliability. Four types of failures are introduced: hardware transients, software and hardware design errors, and program faults. Probability of failure, mean time to failure, and system reliability depend on the type of failure. Actual measurements show that the most critical factor for system reliability is the time after occurrence of a failure when this failure can be repeated in every process that accesses a failed component. An example involving measurements collected in an IBM 4331 installation validates the model and shows its applications. The degradation of system reliability can be appreciable even for very short periods of time. This is why the conditional probability of repetition of failures is introduced. The reliability model allows prediction of system reliability based on the calculation of the mean time to failure. The comparison with the measurement results shows that the model with process dependent repetition of failures approximates system reliability with better accuracy than the model with the assumption of independent failures.     

Lifetime of thin oxide and oxide-nitride-oxide dielectrics withintrench capacitors for DRAMs

An investigation of the field acceleration of the time-dependent dielectric breakdown behavior of a thermal oxide and an oxide-nitride-oxide (ONO) dielectric on planar- and trench-cell MIS capacitors under a constant field stress of 5-9 MV/cm at 150°C is discussed. Defect-related and intrinsic failures are distinguished by a statistical analysis of the breakdown distributions. Planar- and trench-cell capacitors with an ONO dielectric exhibit reduced early failures and a more favorable field-acceleration behavior than capacitors with a thermal-oxide layer. A method which determines the number of intrinsic failures by extrapolation of the accelerated constant field stress data to the device area and down to the operational electric field strength is proposed. The extrapolation predicts, for trench-capacitor arrays with a 5-mm² active device area and a 13.5-nm oxide dielectric operating at 3 MV/cm and 150°C, a mean intrinsic failure rate slightly below 100 Fit in the first year, whereas trench structures with an ONO-dielectric reach the same number of cumulative failures after 1 million years     

Investigations on the thermal behavior of interconnects under ESD transients using a simplified thermal RC network

This work focuses on the interconnect heating during fast ESD transients. A simplified thermal RC network is used to study the behavior of interconnects and to predict their failures, which can be an open circuit or a latent failure due to the decrease of the electromigration lifetime. The RC model is validated by both experiments and finite difference simulations. We observe that the melting of the interconnect system can be considered as instantaneous. Simulations in both solid and liquid phase of the metal are in good agreement with experiments. HBM and MM transients are investigated and a relationship to correlate these ESD stresses with the TLP measurements is studied in depth. We show that a square pulse of 80 ns may be used to predict an HBM stress and a 45 ns pulse is proposed for MM.     

Compact failure modeling for devices subject to electrostatic discharge stresses – A review pertinent to CMOS reliability simulation

This paper reviews the physical mechanisms and compact modeling approaches of two physical damages in MOS devices induced by electrostatic discharge (ESD) stresses; namely gate oxide breakdown and thermal failures. Theories underlying the failure mechanism are discussed and compact models that can be used to monitor ESD induced gate oxide breakdown and thermal failure are developed. Related work reported in the literature is discussed, and benchmarking of measurement data versus simulation results are included in support of the modeling work.     

Simulation of system backend dielectric reliability

Backend dielectric breakdown degrades the reliability of circuits. A methodology to estimate chip lifetime due to backend dielectric breakdown is presented. It incorporates failures due to parallel tracks, the width effect, field enhancement due to line ends, and variation in activity and temperature. Different workloads are considered as well, in order to evaluate aging effects in microprocessors running real-world applications with realistic use conditions.     

变电站调试对二次回路隐性故障的影响分析

随着电力能源需求量的不断增加以及电力系统规模的扩大,对其安全运行也提出了更高要求。二次回路在保证电力系统可靠运行和供电质量上起着重要作用。但二次回路中始终存在着隐性故障,严重影响了电力系统的正常运行。文中在介绍二次回路隐性故障的基础上,对变电站调试对二次回路隐性故障的影响进行了分析,并提出了二次回路隐性故障预防措施和排查处理方法。     

Photovoltaic Array Reliability Optimization

Several statistical reliability studies have been conducted in areas of photovoltaic component design covering cell failure, interconnect fatigue, glass breakage and electrical insulation breakdown. This paper integrates the results from these studies and draws general conclusions relative to optimal reliability features for modules. The analysis is based on designing for specified low levels of component failures and then controlling the degrading effects of the failures through the use of fault tolerant circuitry and module replacement. Means of selecting the cost-optimal level of component failures, circuit redundancy, and module replacement are described.     

Preliminary characterization of a metal-gas-semiconductor field-effect transistor (MGSFET) proposed

A solid-gate-insulator-less field-effect transistor, named metal-gas-semiconductor FET, MGSFET is proposed. This is aimed to avoid possible failures such as dielectric breakdown of the gate due to the gate insulator. A fundamental process sequence and preliminary characterization for MGSFET are described in this article.Regarding the device performance, it is observed that drain current drivability of MGSFET is about four times worse than that of conventional MOSFET. It is speculated that the inferiority is caused by the permittivity difference between SiO₂ and air. While, the gate leakage current of MOSFET obviously becomes worse after the catastrophic breakdown, but that of MGSFET becomes much better than before in forced breakdown of gate insulation. In this first trial of MGSFET implementation, the forced breakdown simultaneously degrades normal transistor performance. Further investigation should be made to analyze what is going on MGSFET structure.     

The Correlation of Surface Defects and Reverse Breakdown of 4H-SiC Schottky Barrier Diodes

Surface defect characterization and the influence of selected surface defects on the reverse characteristics of 4H-SiC Schottky barrier diodes (SBDs) are investigated, with particular emphasis on comet and carrot defects. Premature breakdown caused by comets occurs at voltages below 250 V for an SBD with ideal parallel plane breakdown of 1,600 V. The location of comets relative to the Schottky contact ultimately determines the reverse characteristics of the device. The reverse breakdown voltage of SBDs with carrot defects can be more than 1,000 V, but the reverse leakage current is about two orders higher than that of a defect-free SBD. The SBDs of diodes with and without carrots are 1.01 eV and 1.44 eV, respectively. The SBDs, which catastrophically fail during reverse bias measurement, are investigated as well. The average breakdown voltage of SBDs, which failed catastrophically, is about 745 V. According to the experimental observations, catastrophic failures are not associated with obvious surface defects, crystallographic directions, or postimplant annealing time.     

Mitigation for single event coupling delay

With advances in CMOS technology, circuits are increasingly more sensitive to transient pulses caused by single event particles. It has been predicted that the majority of the observed radiation induced soft failures in technologies below 65 nm will be because of transients that will occur in combinational logic (CL) circuits. Researchers mostly consider single event transients as the main source for CL related radiation-induced soft errors. However, for high reliability applications such as avionics additional sources need to be included in reliability analysis. In this work, we report a new error mechanism named ‘single event crosstalk delay’, investigate the vulnerability of recent technologies to these delay effects and then propose hardening techniques for single event crosstalk delay. Results are demonstrated using HSpice simulations with interconnect and device parameters derived in 130, 90 and 65 nm technology.     

Transient operation of transistor with inductive load

A transistor operating with an inductive load may develop a collector-emitter short circuit when the transistor is suddenly turned off. The secondary breakdown of the collector characteristics determines the susceptibility to this type of failure. The secondary breakdown is greatly influenced by the reverse base current. The reverse base bias voltage and impedance affect the reverse base current in a predictable manner. The failure mechanism can be explained in terms of the characteristics of a four-layer device. Transistor requirements and design considerations are examined. For safe operation, the secondary breakdown current should be greater than the maximum operating current. When the reverse base current is minimized, the transistor is also protected. Several circuits which prevent the flow of reverse base current are presented.     

Influence of gate oxides with high thermal conductivity on the failure distribution of InGaAs-based MOS stacks

In this work, the breakdown transients of metal-oxide-semiconductors (MOS) stacks with InGaAs channels and different oxide layers (Al₂O₃, HfO₂ and Si₃N₄) have been studied in terms of the time-to-breakdown and the duration of the progressive breakdown regime. It is observed that dielectric layers with higher thermal conductivity show larger transient time during the progressive breakdown regime, and this provides a significant lifetime extension across the entire failure distribution. This is attributed to a lower temperature of the percolation path which reduces local electro-migration. Moreover, the overall results show that the progressive breakdown regime is uncorrelated with the initial degradation rate, and that the bending of failure distribution at low percentiles is exclusively attributed to the progressive increase of the gate current during the breakdown event.     

砷化镓微波单片集成电路的失效分析

通过封装内部气氛、芯片显微、能谱等分析手段对国内某研究所研制砷化镓微波单片集成电路高温加速寿命试验后的样品进行了失效分析,对其失效机理进行探讨,得出:封装气密性不好、工艺造成的缺陷是引起失效的主要原因,也是造成国内产品质量与可靠性不如国外同类产品的重要原因。