A 14-bit 250 kS/s two-step inverter-based incremental $$\varSigma \varDelta$$ ADC for CMOS image sensor in $$0.18\,\upmu \hbox {m}$$0.18μm technology

This paper presents an ultra-low-power, bulk-driven, source-degenerated fully differential transconductor (FD-OTA), operating in subthreshold region. The source-degeneration (SD) and bulk-drive ensure linearity and rail-to-rail input swing. The flipped voltage follower and SD resistor perform V–I conversion in input core with power efficient class AB mode of operation. The reduction in open loop gain and gain bandwidth (GBW) of bulk-drive is compensated by applying partial positive feedback at diode connected MOSFET pair. The current gain from input core to output load side is set (1:1) in OTA₁ and (1:4) in OTA₂. The OTA₂ offers increased transconductance and GBW whereas self-cascode load increases the output impedance and overall gain of the FD-OTAs. Both the input core and common source self-cascode load operate in class AB mode so these FD-OTAs provide enhanced slew rates. These OTAs have been employed to implement Biquadratic low-frequency G_m-C filter suitable for bio-signal applications. The proposed OTA₂ has used dual supply voltage of ± 0.3 V and dissipates around 70 nW power and provides 62 dB FD-open loop gain with GBW of 7.73 kHz while driving the FD-load of 2 × 15 pF. The Cadence VIRTUOSO environment using UMC 0.18 µm CMOS process technology has been used to simulate the proposed circuit. The Simulation results verified fully differential total harmonic distortion of ? 72 dB, for 1.2 V_p–p signal at 200 Hz frequency in unity gain configuration with resistive degeneration of 1 MΩ for OTA₁.     

An ultra-low power CMOS DC–DC buck converter with double-chain digital PWM technique

In present-day integrated digital circuits are become attractive choice for the DC–DC buck converters. This paper proposes a novel approach of CMOS DC–DC buck converter with double-chain digital pulse width modulation (PWM) for ultra-low power applications. The proposed digital PWM architecture consists of double delay lines which is to reduce power consumption and improves ripple voltage with the resolution. An algorithm is proposed that describes the operation of digital PWM. The double chain digital PWM is implemented and analyzed in cadence platform using commercial 180 nm TSMC design kit. The promising results reveals that the power consumption is reduces up to 1.16 µW with occupies less area under the operating frequency of 100 kHz. The DC–DC buck converter with proposed PWM achieves peak efficiency of 92.6% including a load current range of 4–10 mA. This proposed digital PWM method demonstrates its ability to minimize the ripple voltage by 49% and enables to DC–DC converter for compose in a compact chip area as compared to conventional converters. Measured and Simulated power efficiency are made good agreement with each other.     

A voltage mode buck DC–DC converter with automatic PWM/PSM mode switching by detecting the transient inductor current

This paper presents a voltage mode buck DC–DC converter that integrates pulse-width modulation (PWM) and pulse-skipping modulation (PSM) to achieve high efficiency under heavy and light load conditions, respectively. Automatic mode-switching is implemented simply by detecting the voltage drop of high-side power switch when it is on, which indicates the transient current flowing through the inductor. Unlike other methods based on average current sensing, the proposed auto-mode switching scheme is implemented based on voltage comparison and simple control logic circuit. In order to avoid unstable mode switching near the load condition boundary, the mode switching threshold voltage is set differently in PWM and PSM mode. Besides, a 16-cycle counter is also used to ensure correct detection of the change in the load condition and fast response of the converter. In addition, a dual-path error amplifier with clamp circuit is also adopted to realize loop compensation and ensure 100 % duty cycle operation. Fabricated in a 0.18-μm standard CMOS technology, the DC–DC converter is able to operate under supply voltage from 2.8 to 5.5 V with 3-MHz clock frequency. Measurement results show that the converter achieves a peak efficiency of 93 %, and an output voltage ripple of less than 40 mV, while the chip area is 1.02 mm².     

Design of efficient power amplifier for low power transmitters

This paper presents a fully integrated, low transmit-power and high-efficiency 2.4 GHz class-E power amplifier (PA) in TSMC 0.18 μm CMOS process for low-power transmitters such as wireless sensor networks (WSN). In this paper, a new output load has been proposed. Also, analytical design equations have been included to design an efficient low power circuit. This PA, employs the pad capacitance and bond-wire inductance of the output node, for satisfying class-E zero-voltage switching (ZVS) condition and matching the antenna’s 50 Ω resistance. By using bond-wire inductance instead of inductor in the output filter, smaller chip size and higher efficiency has been achieved compared to other works for low transmit-power applications. Also, the effectiveness of bulk-drive technique on faster switching and increasing efficiency have been evaluated. It has been proved that this technique leads to increase the efficiency of switching PAs. This PA delivers a range of output power from 2.7 to 7.2 dBm with a supply voltage range from 500 to 850 mV while achieving overall power efficiency range of 57.3–60.7%.     

Switchless compact dual-band matching networks for class-E power amplifiers

Two compact switchless dual-band load networks for class-E power amplifier (PA) operating at 800 and 1900 MHz are proposed, featuring small area and low loss which will be suitable for non-concurrent dual-band PA module in handset. Theoretical analysis and design equations are provided along with a loss model, including loss in the transistor and in the load network. Loss model is extracted for each structure to find the design parameters for optimized and balanced efficiency in both bands. Both designs are fabricated on Rogers RO4003 substrate with lumped components. Full PA simulations of both bands are carried out with co-simulation using a Triquint TGF2023-2-10 GaN transistor model, lumped components and EM models of load network layouts for both structures. The PA with transformer-based load network achieves a power added efficiency of 68.6 % at low band and 62.6 % at high band at an output power of 37.8 and 36.7 dBm respectively. The overall area consumed by the load network is 13.5 × 9.6 mm². The LC-based PA has a similar PAE of 68.3 and 60 % at low band and high band, respectively. The output power is 38.1 dBm in the low band and 37 dBm in the high-band. The overall area consumed by the load network is 9 × 10 mm²     

Design of a CW 1 THz Gyrotron (Gyrotron Fu Cw III) Using a 20 T Superconducting Magnet

Design of a CW 1 THz gyrotron at second harmonic operation using a 20 T superconducting magnet has been described. The mode competition analysis is employed to investigate operation conditions of second harmonic mode, which is being excited at the frequency ranging from 920 GHz to 1014 GHz. The output power up to 250 watt corresponding to the efficiency of 4.16 percent could be achieved by using an electron beam with accelerating voltage 30 kV and current 200 mA. The important advantage of this gyrotron is that the single mode excitation at second harmonic, and extremely high frequency of the radiation, could be maintained even at high currents. It opens possibility to realize a high power radiation source at 1 THz. Such gyrotron is under construction at FIR Center, University of Fukui.     

A 200-mA, 93% peak power efficiency, single-inductor, dual-output DC–DC buck converter

A single-inductor dual-output (SIDO) DC–DC buck converter is presented. The circuit uses only one (external) inductor to provide two independent output voltages ranging from 1.2 V to the power supply (2.6–5 V) with a maximum total output current of 200 mA. The proposed converter has been fabricated in a 0.35-μm p-substrate CMOS technology. Measurement results demonstrate that a peak power efficiency as high as 93.3% can be achieved. An automatic substrate bias switch technique, that cancels the body effect of the p-channel output power transistors, improves the converter power efficiency performance.     

Impact and control of network QoS on smart grid controlled electrical vehicle charging

Novel, networked information-rich control systems are emerging to provide a stable and cost-efficient operation of future electricity distribution grids. However, the dependence on fault-prone, low-cost, and heterogeneous network technologies and architectures challenges the grid control quality. In this work, we study the impact of varying network QoS for M2M connectivity on the low voltage grid operation in an electrical vehicle charging scenario. The analyzed charging control system relies on: (a) grid power sensing using smart meters via high latency power line communication and, (b) charging point actuation commands disseminated via unreliable wireless links (IEEE 802.11). Based on emulation results, we quantify the maximum acceptable meter reading delay from network transmission that sufficiently minimizes load prediction error. Further, based on the introduction of a timed reliable communication protocol, it is shown how changing the trade-off in QoS parameters of delay, loss and information inconsistency can be applied to overcome degradation of controller performance.     

A 0.1–4 GHz SDR receiver with reconfigurable 10–100 MHz signal bandwidth in 65 nm CMOS

A 0.1–4 GHz software-defined radio (SDR) receiver with reconfigurable 10–100 MHz signal bandwidth is presented. The complete system design methodology, taking blocker effects into account, is provided. Fully differential Op-Amp with Miller feedback and feed-forward compensations is proposed to support wideband analog circuits with low power consumption. The stability and isolation of inverter-based trans-conductance amplifier are analyzed in details. The design approach of high linearity Tow-Thomas trans-impedance amplifier is presented to reject out-of-band blockers. To compensate for PVT variations, IIP2, frequency tuning, DC offset and IQ calibration are also integrated on-chip. The SDR receiver has been implemented in 65 nm CMOS, with 1.2/2.5 V power supply and a core chip area of 2.4 mm². The receiver achieves S11 input matching below ?10 dB and a NF of 3–8 dB across the 0.1–4 GHz range, and a maximum gain of 82–92 dB with a 70 dB dynamic range. Dissipated power spans from 30 to 90 mW across this entire frequency range. For LTE application with 20 MHz signal bandwidth and a LO frequency of 2.3 GHz, the receiver consumes 21 mA current.     

Design and electrochemical measurement of a current-mode analog-to-time converter with short-pulse output capability using local intra-cell activation for high-speed time-domain biosensor array

Functional electrical stimulation has been widely used for the restoration of bladder functions after spinal cord injury or other neurological disorders. However, most of the neuroprostheses for bladder control are still imperfect due to lack of the feedback information about the state of the controlled bladder. The purpose of this study is to develop an implantable system which allows us to stimulate the nerves and record the nerve signals related to the condition of the bladder. The proposed stimulator consists of three parts: a digital-to-analog converter (DAC), a current driver, and a switch network. Using the same current source with a switch network eliminates the need for separate current sources for anodic and cathodic sections and reduce the need for interconnect lines of control signals which is an area-saved and power-efficient configuration. A symmetrical regulated cascode current driver is used to implement a high voltage compliance and a high output impedance which improves its ability with load. The amplitude, frequency and the pulse width of the stimulating current are adjusted by encoding the DAC and switch sequences, respectively. In addition, we also present two-stage fully differential capacitively-coupled amplifiers for neural recording. The neural amplifier’s parameters are carefully chosen according to the characteristics of neural signal; meanwhile, we analyzed theoretically the main noise sources, especially the pseudo-resistor in the feedback path which gives little attention by previous studies. The integrated neural stimulating and recording frontend for bladder control prosthesis has been designed and simulated, using a TSMC’s 0.18-μm CMOS process. The proposed stimulator can provide a symmetrical cathodic-first biphasic current pulse with interphasic gap, a low headroom voltage of 0.168 V corresponding to 2.48 mA full-scale current, an adjustable pulse width of 100–500 μs and frequency of 1–40 Hz. The recording amplifier with a low input-referred noise of 3.62 μV, an NEF of 3.88 and a low power dissipation of 7.2 μW has a gain of 61.6 dB and a frequency bandwidth from 300 Hz to 5.3 kHz. Both circuit analysis and simulations are presented to examine the performance of the proposed designs.     

On the design of highly linear CMOS digitally programmable operational transconductance amplifiers for low and high-frequency applications

This paper proposes a novel highly linear digitally programmable fully differential operational transconductance amplifier (DPOTA) circuit. Two versions of the proposed DPOTA structure are designed. The first version is optimized for high-frequency operation with current division networks designated to 3-bit control code words. On the other hand, the second version is optimized for low-frequency operation with 4-bit control code words. The third-order harmonic distortion (HD3) of the first DPOTA version remains below ? 66 dB up to 0.4 V differential input voltage at 10 MHz frequency. The second DPOTA version achieved HD3 of ? 70 dB with an amplitude of 20 mV_p–p and at 100 Hz frequency. The proposed circuits are designed and simulated in 90 nm CMOS model, BSIM4 (level 54) under a balanced 1.2 V supply voltage.     

A high efficiency transmitter and receiver for magnetic resonant wireless battery charging system in 0.35 μm BCD

This paper presents a transmitter and receiver for magnetic resonant wireless battery charging system. In the receiver, a wide-input range CMOS multi-mode active rectifier is proposed for a magnetic resonant wireless battery charging system. The configuration is automatically changed with respect to the magnitude of the input AC voltage. The output voltage of the multi-mode rectifier is sensed by a comparator. Furthermore, the configuration of the multi-mode rectifier is automatically selected by switches as original rectifier mode, 1-stage voltage multiplier or 2-stage voltage multiplier mode. As a result, a rectified DC voltage is output from 7.5 to 19 V for an input AC voltage of 5–20 V. In the transmitter, a class-E power amplifier (PA) with an automatic power control loop and load compensation circuit is proposed to improve the power efficiency. The transmitted power is controlled by adjusting the signal applied to the gate of the power control transistor. In addition, a parallel capacitor is also controlled to enhance the efficiency and compensate for the load variation. This chip is implemented using 0.35 μm BCD technology with an active area of around 5,000 × 2,500 μm. When the magnitude of the input AC voltage is 10 V, the power conversion efficiency of the multi-mode active rectifier is about 94 %.The maximum power efficiency of the receiver is about 70 %. The transmitter provides an output power control range of 10–30.2 dBm. The maximum power efficiency of the PA is 71.5 %.     

Automatic Modulation Recognition Based on Morphological Operations

Automatic modulation recognition under negative signal-to-noise ratio (SNR) environment is a challenging topic. In this paper, we propose the method consisting of two main steps: constructing a template library and recognition. The former extracts the morphological envelope of each signal power spectrum by using the morphological close–open operation to construct the template library. The latter can further be divided into two sub steps. The first sub-step is to calculate the similarities between the morphological envelope of received signal power spectrum and each template in the template library. The second one is to determine the modulation type of received signal based on the maximum of the similarities which are more than the threshold. Simulation results demonstrate that the correct recognition rate (CRR) can increase by 0.84 % and 9.38 % with hierarchical method and ZAM-GTFR method at SNR=?4 dB, respectively. The proposed method can reduce the computational complexity by about 97 % compared with the ZAM-GTFR method when N≤4096. The results prove the method has the advantage of high CRR and the less computation.     

A microwatt switched-capacitor voltage doubler-based voltage regulator for ultra-low power energy harvesting systems

This paper presents an SC voltage doubler-based voltage regulator for ultra-low power energy harvesting applications. It produces a stable 1.2-V power supply, using inputs from 0.63 to 1.8 V. External compensation and an on-chip output capacitor ensure good performance even with zero load current and any load capacitance. The regulator tolerates arbitrary input ramp-ups, and is immune to blackout and brownout. A stability analysis for the regulator control loop is presented. The regulator ASIC is implemented in a 180 nm CMOS process. The measured regulator peak power and current efficiency are 63 and 49 %, respectively. The performance has been characterized with load currents from zero to \(100\,\upmu\)A.     

Frequency tunable low ripple and fast response on-chip DC–DC converter for DVFS

Dynamic voltage and frequency scaling (DVFS) is an efficient method to reduce the power consumption in system on-chip. To support DVFS, multiple supply voltages are generated based on different work load frequencies and currents using on-chip DC–DC voltage converter. In this paper a frequency tunable multiple output voltage switched capacitor based dc–dc converter is presented. An analog to digital converter and phase controller is used in the feedback to change the switching frequency and duty cycle of the converter. An input voltage of 1.8 V is converted to 0.6 and 0.8 V for low and high signal frequency respectively. The proposed 2-phase switched capacitor architecture with gain setting of 1:2 is designed with the 90 nm technology. An output ripple of 45 mV is observed and the maximum transient response time of the converter is 17.3 ns (= 58 MHz).     

Dual-output switched-capacitor DC–DC converter with pseudo-three-phase swap-and-cross control and amplitude modulation mechanism

This paper presents an inductorless dual-output switched-capacitor DC–DC converter employing pseudo-three-phase swap-and-cross control (PTPSCC) and an amplitude modulation mechanism (AMM). The AMM circuit scales the amplitudes of the driving signals for the switches according to the loading conditions in order to minimize switching losses. To reduce output ripples, average charge distribution, and improve regulation, the PTPSCC circuit continuously switches power transistors to deliver enough charge to the outputs by keeping at least one flying capacitor connected to each output. The switched capacitor DC–DC converter was implemented in a standard 0.18-μm 3.3-V CMOS process. Measurements were used to verify that the proposed converter provides dual independently regulated output voltages without cross regulation. The two outputs were regulated at 2.5 and 0.8 V with input ranges of 1.7–2 V. The maximum output loading was 100 mA for both outputs. A power efficiency of 90.5% was achieved at a maximum total output power of 330 mW with a switching frequency of 500 kHz, and a maximum power efficiency of 92.1% was achieved for a total output power of 210 mW. The maximal peak-to-peak output ripple voltages for the two outputs at 100 mA load currents were suppressed to below 26 and 20 mV, respectively.     

A WiSN node SoC with real-time image compressor and IEEE 802.15.4 MAC accelerator

This article presents a wireless image sensor node SoC (system-on-a-chip) for low-power wireless image sensor network (WiSN), in which camera chip interface, high-quality image compression and IEEE 802.15.4 compliant acceleration modules are integrated on chip. The proposed SoC contains a hardware-implemented real-time lossless JPEG (JPEG-LS) compression engine for Bayer Color Filter Arrays (Bayer CFA), reaching a 3.5 bits/pixel with peak signal to noise ratio (PSNR) greater than 46.3 dB and achieving a maximum 5 frames/s @16 MHz for VGA (640 × 480) colour images. The proposed hardware accelerator for IEEE 802.15.4 media access control (MAC) layer covers crucial protocol defined functions and algorithms, and reduces 45% software code in the host processor. This SoC has been fabricated in UMC 0.18 µm 1P6M CMOS process. The average power of the prototype chip is 18.2 mW at 3.0 V power supply and 16 MHz clock rate.     

140 GHz, 1 MW CW Gyrotron Development for Fusion Applications��Progress and Recent Results

A 10 MW, 140 GHz ECH system is currently under construction for the stellarator W7-X. The RF power will be provided by 10 gyrotrons. A European collaboration has been established to develop and build 9 (out of 10) tubes each with an output power of 1 MW for continuous wave (CW) operation. This contribution reports on recent results with the series gyrotrons.     

Design and analysis of all-optical up- and down-wavelength converter based on FWM of SOA-MZI for 60 Gbps RZ data signal

In this paper, the design and analysis of the all-optical up- and down-wavelength converter based on four-wave mixing (FWM) effect of semiconductor optical amplifier Mach–Zehnder interferometer (SOA-MZI) have been presented. The return-to-zero (RZ) modulated data signal at a bit rate of 60 Gbps has been evaluated for error-free operation to show the feasibility of proposed system at different pump wavelength. The converted signal power and quality factor are investigated as the function of variable signal power and pump power. The optimized operating input signal power of ?5 dBm with Q-factor of \(\sim \)28 dB for RZ modulated signal by using SOA-MZI structure with enhanced FWM effect. The important contribution of these investigations that it is possible to expand the optical network with limited available channel bandwidth by utilizing the wavelength converter and gives an approach to implement wavelength converter for future hybrid optical access networks.     

High static gain single-phase PFC based on a hybrid boost converter

In this paper, a single-phase unity power factor rectifier, based on a hybrid boost converter, resulting from the integration of a conventional dc–dc boost converter and a switched-capacitor voltage doubler is proposed, analysed, designed and tested. The high-power rectifier is controlled by two feedback loops with the same control strategy employed in the conventional boost-based rectifier. The main feature of the proposed rectifier is its ability to output a dc voltage larger than the double of the peak value of the input line voltage, while subjecting the power switches to half of the dc-link voltage, which contributes to reducing the cost and increasing the efficiency. Experimental data were obtained from a laboratory prototype with an input voltage of 220 Vrms, line frequency of 60 Hz, output voltage of 800 Vdc, load power of 1000 W and switching frequency of 50 kHz. The efficiency of the prototype, measured in the laboratory, was 96.5% for full load and 97% for half load.