Scan Division Algorithm for Shift and Capture Power Reduction for At-Speed Test Using Skewed-Load Test Application Strategy

This paper discusses an automated method to divide scan chains into multiple scan segments that are suitable for power-constrained at-speed testing using the skewed-load test application strategy. By dividing a circuit into multiple partitions, which can be tested independently, both power during shift and power during capture can be controlled. Despite activating one partition at a time, we show how through conscious construction of scan segments, high transition fault coverage can be achieved, while reducing test time of the circuit and employing third party test generation tools.

Fast PWM-Based Test for High Resolution ΣΔ ADCs

This work describes a novel test strategy that uses digital stimuli for cheap, fast, though accurate, testing of high resolution ΣΔ ADCs. Simulations and measurements showed a discrimination threshold on specification parameters up to −90 dBc. The proposed method helps to reduce the cost of ADC production test, to extend test coverage and to enable built-in self-test and test-based self-calibration.

Isolation of Failing Scan Cells through Convolutional Test Response Compaction

This paper describes a non-recursive fault diagnosis technique for scan-based designs with convolutional test response compaction. The proposed approach allows a time-efficient and accurate identification of failing scan cells using Gauss–Jordan elimination method.

Test Compression for IP Core Testing with Reconfigurable Network and Fixing-Flipping Coding

This paper proposes a class of test compression for IP (intellectual property) core testing. The proposed compression requires only test cubes for the IP cores and it dose not require the structural information about the IP cores. It uses both a reconfigurable network and classes of coding, namely fixing-flipping coding and fixing-shifting-flipping coding. The proposed compression is evaluated from the viewpoint of compression rates and hardware overhead. For three out of four large ISCAS89 benchmark circuits, the compression rates of the proposed compression are better than those of the four existing test compressions.

RF Testing on a Mixed Signal Tester

In this paper, testing of radio frequency (RF) devices with mixed-signal testers is discussed. General purpose automatic test equipment (ATE) will be used. In this paper, a more universal test structure utilizing RF building blocks is proposed. A global positioning system (GPS) device is used as an example to illustrate how to develop the RF test plan with this usage. The test plan developed includes fast, cost-effective and dedicated circuitry.

Reverse Breakdown Voltage Measurement for Power P<Superscript>+</Superscript>NN<Superscript>+</Superscript> Rectifier

The measurement of the reverse breakdown voltage for power rectifier is an important test. Two test methods for the reverse breakdown voltage measurement are employed in the industry, namely the forced voltage test (FVT) and the forced current test (FCT). In this work, we perform a systematic study to explain the different breakdown voltages obtained from the two test methods and the possible damage mechanisms to the device under test during FVT and FCT. The study shows that FVT has a much shorter test time while FCT is less destructive to the device under test.

A Low-Cost Test Methodology for Dynamic Specification Testing of High-Speed Data Converters

Testing high-speed A/D converters for dynamic specifications needs test equipment running at high frequency. In this paper, a methodology to test high-speed A/D converters using low-frequency resources is described. It is based on the alternate testing approach. In the proposed methodology, models are built to map the signatures of an initial set of devices, obtained on the proposed low-cost test set-up, to the dynamic specifications of the same devices, obtained using high-precision test equipment. During production testing, the devices are tested on the low-cost test set-up. The dynamic specifications of the devices are estimated by capturing their signatures on the low cost test set-up and processing them with the pre-developed models. As opposed to the conventional method of dynamic specification testing of data converters, the proposed approach does not require the tester resources running at a frequency higher than the device-under-test (DUT). The test methodology was verified in simulations as well as in hardware with specification estimation error of less than 5%.

Controllability of Static CMOS Circuits for Timing Characterization

Timing violations, also known as delay faults, are a major source of defective silicon in modern Integrated Circuits (ICs), designed in Deep Sub-micron (DSM) technologies, making it imperative to perform delay fault testing in these ICs. However, DSM ICs, also suffer from limited controllability and observability, which impedes easy and efficient testing for such ICs. In this paper, we present a novel Design for Testability (DFT) scheme to enhance controllability for delay fault testing. Existing DFT techniques for delay fault testing either have very high overhead, or increase the complexity of test generation significantly. The DFT technique presented in this paper, exploits the characteristics of CMOS circuit family and reduces the problem of delay fault testing of scan based sequential static CMOS circuits to delay fault testing of combinational circuits with complete access to all inputs. The scheme has low overhead, and also provides significant reduction in power dissipation during scan operation.

Reducing Test Time Using an Enhanced RF Loopback

This work presents a method to improve the loopback test used in RF transceivers. The approach is targeted to the System-On-Chip environment, being able to reuse system resources in order to minimize the test overhead. An RF sampler is used during loopback operation, allowing observation of spectral characteristics of the RF signal. While able to improve the overall observability of the RF signal path, faster diagnosis than conventional loopback tests is achieved thanks to a large reduction in the number of transmitted symbols. Theoretical analysis and practical results for a prototype transceiver operating at 846 MHz are presented. It is shown that a significant test time reduction is achievable considering bit error rate tests for common digital modulation schemes.

Oscillation Test Scheme of SC Biquad Filters Based on Internal Reconfiguration

In this paper, we explore general conditions for the oscillation based test of switched-capacitor biquad filter stages. Expressions describing the characteristics of a filter stage put into oscillation are derived and conditions for achieving oscillation by internal transformation of the filter stage are explored. Reconfiguration scheme based on the transformation of the biquad filter stage to a quadratic oscillator is studied. Theoretically the circuit can be put into oscillation by de-activating a single capacitor. Simulations, however, show that in practice a carefully designed low feed-back loop is required to achieve acceptable oscillation test mode.

Online Testing of MEMS Based on Encoded Stimulus Superposition

This article presents a technique that enables online testing of sensors through the superposition of the test stimulus onto the measurand. Perturbations due to the surrounding environment can very often introduce fluctuations in the test output creating a major concern for this type of sensor testing. In this paper, a signal processing technique is proposed where the test stimulus is encoded by a pseudo-random sequence in order to reduce the test output fluctuations. The trade-off between the level of rejection of a perturbation and the overall test time is studied. In the case of the MEMS accelerometer considered in this paper, it is theoretically demonstrated that the rejection is more than 20 dB for a test time of 2.55 s. Furthermore, excessively strong perturbations can be monitored so that the test status is updated only if the accuracy of the test signal permits so. The technique has been implemented on a demonstration board and validated on a vibration platform.

Arbitrary Two-Pattern Delay Testing Using a Low-Overhead Supply Gating Technique

With increasing defect density and process variations in nanometer technologies, testing for delay faults is becoming essential in manufacturing test to complement stuck-at-fault testing. This paper presents a novel test technique based on supply gating, which can be used as an alternative to the enhanced scan based delay fault testing, with significantly less design overhead. Experimental results on a set of ISCAS89 benchmarks show an average reduction of 34% in area overhead with an average improvement of 65% in delay overhead and 90% in power overhead during normal mode of operation, compared to the enhanced scan implementation.

Reduced stability testing set for a diamond-type family of quasipolynomials

A diamond-type family of quasipolynomials, for which vertex stability results hold, is presented. Both delay independent and delay-dependent stability conditions are given. In the first case, it suffices to check for the stability of a finite testing set of multivariate polynomials. While in the other one, it is also needed to check the stability of several edge sub-families of quasipolynomials.

Noise-Insensitive Digital BIST for any PLL or DLL

PLLs are the heart of most SoCs, so their performance affects many tests. Practical, published PLL BIST approaches cannot measure <10 ps RMS jitter or >1 GHz. This paper describes how a SerDes undersampling DFT technique was adapted to test multiple PLLs and DLLs for jitter, phase error, output frequency, duty cycle, lock time, and lock range. Two techniques for cancelling random and systematic noise are also described. The multi-GHz range, sub-picosecond jitter noise floor, and minimal silicon area are better than for any previous silicon-proven DFT or BIST that needs no calibration or analog circuitry. FPGA implementation results are provided.

Scan Shift Power Reduction by Freezing Power Sensitive Scan Cells

In this paper, we show that not every scan cell contributes equally to the power consumption during scan-based test. The transitions at some scan cells cause more toggles at the internal signal lines of a circuit than the transitions at other scan cells. Hence the transitions at these scan cells have a larger impact on the power consumption during test application. We call these scan cells power sensitive scan cells. A signal probability based approach is proposed to identify a set of power sensitive scan cells. Additional hardware is added to freeze the outputs of power sensitive scan cells during scan shifting in order to reduce the shift power consumption. Experimental results on industrial circuits show that on average more than 45% of the scan shift power can be eliminated when freezing only 5% of power sensitive scan cells.

Methods of Testing Discrete Semiconductors in the 1149.4 Environment

This paper describes measurement methods for testing discrete semiconductors in the environment defined by the IEEE 1149.4 standard for a mixed-signal bus. First, the paper introduces and illustrates measurement procedures for obtaining such essential electrical parameters of diodes and transistors as can be used for testing and identification. Then, the procedures are carried out and the achieved measurement results presented. To demonstrate the usability of the measurement procedures, the paper then presents test methods and measurement results for discrete component blocks. The results indicate that testing and measuring some of the electrical parameters of discrete semiconductors is possible in the 1149.4 environment. These parameters allow the determination of whether the component under test is working properly or not. Our tests only covered the semiconductors’ DC features, disregarding their AC features. Also discussed are limitations of the 1149.4 environment in discrete semiconductor testing.

Hardware Implementation of Skeletonization Algorithm for Parallel Asynchronous Image Processing

This paper presents an FPGA realisation of an application-specific cellular processor array designed for asynchronous skeletonization of binary images. The skeletonization algorithm is based on iterative thinning utilizing a ‘grassfire’ transformation approach. The purpose of this work was to test the performance of a fully parallel asynchronous processor array and to evaluate the inhomogeneity of wave propagation velocity. A proof-of-concept design has been implemented and evaluated, the results are presented and discussed.

Detecting Multiple Faults in One-Dimensional Arrays of Reversible QCA Gates

Reversible logic design is a well-known paradigm in digital computation. In this paper, quantum-dot cellular automata (QCA) is investigated for testable implementations of reversible logic in array systems. Testability of 1D arrays consisting of reversible QCA gates is investigated for multiple faulty modules. It has been shown that fault masking is possible in the presence of multiple faults without additional lines for controllability and observability. A technique for achieving C-testability of a 1D array is introduced by adding lines for observability. By adding lines for controllability, as well as observability, the array may be fully tested with a smaller number of test patterns. Different cases of arrays made of QCA reversible gates are presented to illustrate the applicability of the proposed testing method.

A Robust 130 nm-CMOS Built-In Current Sensor Dedicated to RF Applications

In this paper we present a design methodology that allows a dramatic reduction of the dependency on process variation, yielding to a new version of this BICS. Taking advantage of a 130 nm VLSI CMOS technology, the proposed BICS has a peak-to-peak dispersion lower than 10% of its output full-scale range. It makes it more suitable to implement the test functionality while maintaining the initial BICS intrinsic performances. The built-in self-test methodology is illustrated by monitoring the supply current of Low-Noise Amplifiers (LNAs). Measurements confirm the BICS’s transparency relative to the circuit-under-test (CUT) and its accuracy.

Symbol Timing Synchronization Using Interpolation-Based Matched-Filters

This paper presents a symbol timing synchronization method by interpolating the discrete impulse response of matched-filter, in which the group delay of matched-filter is adjusted by different interpolation step to achieve symbol timing synchronization. The proposed method is of much less complexity than the conventional polyphase filterbank method that could be viewed as a special case of interpolated matched-filters. The interpolated matched-filters are used in a loop, and the loop is simulated at 2 samples/symbol, the simulation results show that the proposed method can provide precise symbol timing synchronization with less complexity.