High performance 3.3- and 5-V 0.5-μm CMOS technology for ASIC's

Process integration of two manufacturable high performance 0.5-μm CMOS technologies, one optimized for 5.0 V operation and the second optimized for 3.3-V operation, will be presented. The paper will emphasize poly-buffered LOGOS (PBL) isolation, MOS transistor design using conventional and statistical modeling to reduce circuit performance sensitivity to process fluctuations, gate oxide and gate length control, and hot carrier reliability of the transistors. Manufacturing and simulation data for both 3.3- and 5.0-V technologies will be shown. The nominal ring oscillator delay is measured for both 3.3- and 5.0-V technologies as 80 ps. Therefore, 5.0-V technology equivalent speed is achieved in the 3.3-V technology with a reduction in power consumption by a factor of 2.4     

A reliable and manufacturable method to induce a stress of >1 GPa on a P-channel MOSFET in high volume manufacturing

This letter discusses a reliable and manufacturable integration technique to induce greater than 1 GPa of stress into a p-channel MOSFET, which will be required to increase the drive current beyond 1 mA//spl mu/m at the sub-90-nm process generation. Uniaxial compressive stress is introduced into the p-channel by both a selective deposition of SiGe in the source/drain and an engineered 2.5-GPa compressively stressed nitride. The highest to date compressively stressed SiN film is obtained by heavy ion bombardment during the deposition of the film.     

Silicon-on-insulator approach for power IC's integrating verticalDMOS and polycrystalline silicon CMOS thin-film transistors

A novel approach for the monolithic integration of low-voltage logic and analog control circuits with vertical-current flow power transistors is described. This is achieved by fabricating a CMOS device family, using polycrystalline-silicon thin-film transistors (TFTs), on the field oxide of a single-crystal power device. Parasitic interactions between the control and power devices are eliminated in a simple, inexpensive, and easily manufacturable process. The technology is capable of supporting both MOS and bipolar power devices and the presence of the TFT circuits places no restriction on the maximum voltage or current of the power device. The TFTs exhibit good electrical characteristics and the power devices are not compromised by the addition of the TFT control circuits. This concept is demonstrated by the fabrication of a vertical DMOS power transistor with >100-V, >45-A capability, monolithically integrated with current-limiting and temperature-limiting functions     

Design of 25-nm SALVO PMOS devices

The concept and preliminary designs of novel self-aligned local-channel V-gate by optical lithography (SALVO) devices are presented. SALVO uses optimized local-channel doping to sharpen the lateral junctions, in order to minimize short channel effects for gate lengths down to 25 nm. In addition, it utilizes the replacement-gate design with inner spacers to facilitate integration of alternative gate stack materials and to extend the application of optical lithography. SALVO PMOS designs with both metal gate and poly-metal gate electrodes were studied, the latter proving capable of delivering high performance 25 nm PMOS with currently manufacturable processes     

Robust Electromigration reliability through engineering optimization

With complex process integration approach and severe fabrication limitations caused by introduction of new materials and diminishing process margins, there are mounting concerns with the increased failure rate at the early life cycle (e.g.<1 year operation) of product application known as infant mortality failures. A paradigm change in reliability qualification methodology aim at understanding the impact of variation on reliability is required to ensure reliability robustness. Using Electromigration (EM) as an example, this paper described a methodology where the impact of process variation on reliability is studied. A model that predicts the impact of process variation on EM sigma is also proposed which enables variation and its impact on reliability to be quantified. Using this methodology, the critical process parameters impacting reliability could be identified and controlled to ensure reliability robustness.     

Planar AlGaAs/GaAs HBT fabricated by MOCVD overgrowth with a grownbase

A planar heterojunction bipolar transistor (HBT) with an AlGaAs emitter layer epitaxially grown onto a selectively defined grown base layer, where the base is grown with the collector as part of the original epi, is discussed. The transistors fabricated with this process exhibit good gain and output characteristics. Transistors with 7×7 μm² emitters have exhibited a DC current gain of 10 to 1000 for base doping from 1×10¹⁹ to 8×10¹⁷ cm³, respectively, and Early voltages ⩾100 V. The propagation delay of 19-stage ring oscillators was 87 ps/gate. The transistor-fabrication process was designed to be manufacturable, and the planar nature of the transistor surface should permit large-scale integration with good yields     

High-performance TFTs fabricated on plastic substrates

Poly-Si thin-film transistors (TFTs) have recently been introduced to commercial glass flat-panel displays. This letter presents a manufacturable process for fabricating poly-Si TFTs directly on plastic substrates that exceed TFT parameter requirements for active-matrix displays. Plastic sheets are laminated onto carrier wafers, to allow use of automated tools for manufacturing. In order to maintain adhesion through the whole process, the wafer temperature is kept below 105/spl deg/C. Laser crystallization is used to grow poly-Si, and a quarter-wavelength stack layer is deposited to protect plastic from the laser processing. In order to achieve state-of-the-art poly-Si TFTs on plastic, the gate oxide is optimized. Using a higher temperature anneal after delamination minimizes leakage currents.     

Flip Chip Assembly of Thinned Silicon Die on Flex Substrates

Driven by a growing range of applications in the automotive, industrial, military, aerospace, computer, telecommunication, consumer electronics, and medical electronics industries, miniaturization and the use of flex circuits continue to be of prime interest to electronics manufacturers. The assembly of thinned silicon die (25-100 mum) onto flex substrates provides options for ultrathin, flexible electronics for applications ranging from smart cards to space-based radars. For high-density applications, 3-D modules can be fabricated by stacking and laminating preassembled and tested flex layers and then processing vertical interconnections. This paper describes a low cost, highly manufacturable process developed for flip chip assembly of thinned die to poly-imide flex substrates that eliminates the need for special handling tools and techniques. In this paper, solder bumped thinned die are reflow soldered to the patterned flex using a method that maintains the flex substrate flat during die placement and reflow. Reflow is followed by underfill dispense and cure. The underfill dispense process is critical to avoid underfill flowing onto the top of the thin silicon die and will be discussed. Parts assembled using these processes have undergone reliability testing, a high degree of reliability has been found, and those results are presented.     

Hybrid punch through approach to address electroless related integration issues of hybrid CoWP/SiCN barriers

Integration of CoWP self-aligned barriers in hybrid stack with SiCN liner in a standard 65 nm technology node integration scheme faces several issues. For example, bowing of upper metal level occurs due to the interaction between CoWP and etch plasma during SiCN opening step leading to lower line resistance compared to SiCN reference. Furthermore, wet cleaning after patterning step must be carefully processed in order to remove residues while keeping CoWP integrity. Electrical and reliability performance show that a clean recipe can be efficient to remove residues leading to low via resistance but in the same time, no electromigration improvement compared to SiCN reference is observed due to CoWP degradation and vice versa. To overcome integration issues, a new integration scheme called hybrid punch through (HPT) approach is proposed. In this approach, the patterning step is modified by SiCN open removal and it is followed by an adapted punch through process during metallization to open the via. HPT approach allows avoiding contact between CoWP and etch plasma or cleaning chemistry and leads to better electrical performance in terms of via and line resistances compared to standard scheme without degrading CoWP.     

Synthesis of a new manufacturable high-quality graded gate oxidefor sub-0.2 μm technologies

Graded gate oxide process involves a two-step synthesis of growing an oxide at a temperature above the viscoelastic temperature (T_VE ) onto a pregrown low temperature thermally grown SiO₂ layer to form a composite graded SiO₂ structure. The cooling rate is carefully modulated near T_VE~925°C to enhance growth induced stress relaxation. The pregrown SiO₂ layer provides grading and is a sink for stress accommodation for the final high temperature SiO₂ forming the interface. Both grading and modulated cooling generate a strain-free and planar Si/SiO₂ interface. Such an interface delivers significant enhancement in all aspects of device reliability and performance. These oxides are of very high-quality, robust, and manufacturable with a process capability index, C_pk>1.5. Graded gate oxide is already in the primary path of our 0.16 μm and 0.12 μm technologies     

Characterization and comparison of single and stacked MIMC in copper interconnect Process for mixed-mode and RF applications

This letter presents the dc and RF study and comparison on four manufacturable single- (one and dual additional masks) and stacked- (intraand multiple inter-) metal-insulator-metal capacitors (MIMCs) in a Cu dual-damascene backend of line process. The capacitors were found to exhibit low leakage and high breakdown field strength, absence of dispersive behavior, and good voltage and temperature linearity. Their quality factor (Q) values are different due to the different electrode series resistance as a result of different architectures. The stacked MIMC offers reduced chip area for the same capacitance value and is a viable manufacturable alternative for current and future precision mixed-mode capacitor incorporating SiN or high-/spl kappa/ dielectric materials.     

Electromigration challenges for advanced on-chip Cu interconnects

As technology scales down, the gap between what circuit design needs and what technology allows is rapidly widening for maximum allowed current density in interconnects. This is the so-called EM crisis. This paper reviews the precautions and measures taken by the interconnect process development, circuit design and chip integration to overcome this challenge. While innovative process integration schemes, especially direct and indirect Cu/cap interface engineering, have proven effective to suppress Cu diffusion and enhance the EM performance, the strategies for circuit/chip designs to take advantage of specific layout and EM failure characteristics are equally important to ensure overall EM reliability and optimized performance. To enable future technology scaling, a co-optimization approach is essential including interconnect process development, circuit design and chip integration.     

Low noise fibre optic receiver operating from 2 to 20 GHz

A wideband optical receiver has been designed and fabricated. The gain with respect to 50 Ω is 12 dB from 2 to 20 GHz, and the noise spectral density is a maximum of 10 pA/√Hz between 6 and 18 GHz. The noise, gain and flatness performances of this GaAs MMIC-based receiver match the equivalent achieved experimentally using highly optimised discrete components, but using a manufacturable process     

Reliability study of 3D IC packaging based on through-silicon interposer (TSI) and silicon-less interconnection technology (SLIT) using finite element analysis

Three-dimensional (3D) integration using the through-silicon via (TSV) approach becomes one promising technology in 3D packaging. 2.5D through-silicon interposer (TSI) is one of the applications of TSV technology, which provides a platform for realizing heterogeneous integration on the TSI interposer. However, TSV manufacturing faces several challenges including high cost. Si-less interconnection technology (SLIT) could overcome such challenges and provide the similar function and benefits as TSI interposer. In SLIT technology, TSVs and silicon substrate are eliminated and the back-end-of-line (BEOL) structures are the same as that in the TSI interposer. Thermo-mechanical reliability is still one important concern under process condition and thermal cycling (TC) test condition for both packaging technologies. In this study, solder joint reliability has been investigated and compared for both packaging technologies through finite element analysis (FEA). Reflow process induced low-k stress and package warpage have also been simulated and compared between packages with TSI and SLIT technologies. The simulation results show that SLIT-based package has comparable micro bump TC reliability as TSI-based package, but SLIT-based package has better C4 joint TC reliability than TSI-based package. SLIT-based package also has lower reflow-induced package warpage and low-k stress than TSI-based package. FEA simulation results verify that SLIT-based packaging is one of promising packaging technologies with good thermo-mechanical performance and cost efficiency.     

Intra-field effects on device and circuit manufacturability: astatistical simulation approach

In spite of the numerous improvements in deep ultraviolet (DUV) lithography, minimizing lens aberrations remains critical to obtaining manufacturable logic technologies. In this paper, we investigate the effects of lens imperfections on the distributions of process, device, and circuit parameters. Lens imperfections, as manifested by intrafield gate critical dimension (CD) variations, can affect device and circuit parameters strongly. The latter is central to designing fast high-yielding logic products, especially microprocessors. Our approach employs process, device, and statistical simulations, coupled with extensive calibration, to predict manufacturing distributions for a new technology well before it is ramped to full-scale production. We study nominal channel length n- and p-channel devices, inverter ring oscillators, and four-input NAND standard cells, We compare different stepper conditions both for conventional and annular illumination. We consider the case of more than one die in a reticle field and investigate how lens imperfections affects different dice therein. We apply our approach to an experimental DUV stepper and demonstrate coma effects that potentially lower yields. Our results also include a paradox: the best annular illumination case, which betters the CD distributions of conventional illumination, ultimately yields worse circuit performance     

0.18μm Low—k SiOF Integration and Reliability

The requirement of reduced RC delay and cross-talk for multilevel interconnect ULSI applications has enthusiastically driven process development for seeking suitable low dielectric constant materials with sufficient k value.The replacement of HDP FSG(k-3.5-3.6)with conventional SiO2 as a manufacturable intermetal dielectric layer(IMD) has achieved 0.18μm ULSI interconnect technology.The electrical test result,via resislance as well as multilevel CMOS transistor characteristics (such as plasma damage,device degradation,hot carrier,etc.)are basically compatible to those conventional oxide as IMD.Assessment of metal line-to-line capacitance reduction using comb capacitors yields values of reduction range 10%-14% comparing FSG to convention oxide.The effectiveness of low-k FSG in circuit performance is also demonstrated.Comparisons of ring-oscillator speed performance for metal runners with various width and space show speed improvement approximately 10% for the FSG.Impact of FSG on reliability is evaluated and results show manufacturing compatibility to conventional SiO2.     

X-band varactor tuned monolithic GaAs FET oscillators†

The design, fabrication and performance of X-band varactor-tuned monolithic GaAs FET oscillators is described. The design is based on small and large signal device characteristics. A manufacturable process is used in order to realize the oscillators. The experimental performance agrees with the theoretical expectations within 0·2% for the oscillation frequency and 4% for the tuning bandwidth. Best tuning bandwidth and output power values exceeded 2 GHz and 28 mW. Wafer dispersion depends on oscillator characteristics and varies between ±1% and ±7·7% for oscillators with a varactor in the FET source. The rf wafer yield is 65%. Finally, noise and temperature characteristics are given.     

VLSI scaling methods and low power CMOS buffer circuit

Device scaling is an important part of the very large scale integration(VLSI) design to boost up the success path of VLSI industry, which results in denser and faster integration of the devices. As technology node moves towards the very deep submicron region, leakage current and circuit reliability become the key issues. Both are increasing with the new technology generation and affecting the performance of the overall logic circuit. The VLSI designers must keep the balance in power dissipation and the circuit’s performance with scaling of the devices. In this paper, different scaling methods are studied first. These scaling methods are used to identify the effects of those scaling methods on the power dissipation and propagation delay of the CMOS buffer circuit. For mitigating the power dissipation in scaled devices, we have proposed a reliable leakage reduction low power transmission gate(LPTG) approach and tested it on complementary metal oxide semiconductor(CMOS) buffer circuit. All simulation results are taken on HSPICE tool with Berkeley predictive technology model(BPTM) BSIM4 bulk CMOS files. The LPTG CMOS buffer reduces 95.16% power dissipation with 84.20% improvement in figure of merit at 32 nm technology node. Various process, voltage and temperature variations are analyzed for proving the robustness of the proposed approach. Leakage current uncertainty decreases from 0.91 to 0.43 in the CMOS buffer circuit that causes large circuit reliability.     

Efficient object-oriented integration and regression testing

This paper presents a model, a strategy and a methodology for planning integration and regression testing from an object-oriented model. It shows how to produce a model of structural system test dependencies which evolves with the refinement process of the object-oriented design. The model (test dependency graph) serves as a basis for ordering classes and methods to be tested for regression and integration purposes (minimization of test stubs). The mapping from unified modeling language to the defined model is detailed as well as the test methodology. While the complexity of optimal stub minimization is exponential with the size of the model, an algorithm is given that: computes a strategy for integration testing with a quadratic complexity in the worst case; and provides an efficient testing order for minimizing the number of stubs. Various integration strategies are compared with the optimized algorithm (a real-world case study illustrates this comparison). The results of the experiment seem to give nearly optimal stubs with a low cost despite the exponential complexity of getting optimal stubs. As being a part of a design-for-testability approach, the presented methodology also leads to the early repartition of testing resources during system integration for reducing integration duration