Closed-Form Expressions of 3-D Via Resistance, Inductance, and Capacitance

Closed-form expressions of the resistance, capacitance, and inductance for interplane 3-D vias are presented in this paper. The closed-form expressions account for the 3-D via length, diameter, dielectric thickness, and spacing to ground. A 3-D numerical simulation is used to extract electromagnetic solutions of the resistance, capacitance, and inductance for comparison with the closed-form expressions, revealing good agreement between simulation and the physical models. The maximum error for the resistance, capacitance, and inductance is less than 8%.      

Optimization of via formation in photosensitive dielectric layersusing neural networks and genetic algorithms

Via formation using photosensitive polymer technology can reduce process cost by reducing process complexity and is hence of great interest in electronics packaging substrate fabrication. However, to overcome technical difficulties and to facilitate low-cost manufacturing, process modeling, optimization and control are required. In this paper, a process optimization approach for via formation in dielectric layers composed of photosensitive benzocyclobutene (BCB) for high density interconnect (HDI) in MCM-L/D substrates is presented. A series of designed experiments are used to characterize the via formation workcell (which consists of the spin coat, soft bake, expose, develop, cure, and plasma de-scum unit process steps). Neural network process models are then constructed to characterize via yield and geometry, as well as film thickness, retention, and uniformity. These models are used for process optimization using genetic algorithms (GA's) and hybrid combinations of GA's with the Powell algorithm and with the simplex algorithm. The optimized process recipes are verified experimentally. Comparison of the three approaches reveals that the hybrid GA/simplex method yields superior recipes     

Redistribution of pads on a singulated IC die using laser direct-write ablation

The use of laser direct-write technology is demonstrated for rapid turnaround redistribution of pads on known good integrated circuit dice. The technology, which is suitable for rapid prototyping of advanced electronic packages, employs an automated laser ablation system with wavelength at 355nm to pattern thin copper films to form the interconnect and vias in the polyimide interlevel insulator. The ablation tool is designed to directly accept the CAD data and write the metallization and via level patterns with excellent (/spl plusmn/3/spl mu/m) layer-to-layer registration. This process is maskless and, except for cleaning steps, does not require patterning by wet chemical etching. The implementation of a change in the design can be done rapidly and involves modifying the CAD data, downloading it to the laser ablation tool, and fabricating a part according to the new design. This paper illustrates the use of laser direct-write ablation for fabrication of via chain test structures and redistribution of pads on functional integrated circuits on singulated dice. Comparable electrical test results were obtained between structures fabricated using laser ablation technology and those fabricated on full 150-mm diameter wafers using conventional photolithography and etch processes.     

Comparison of laser-wavelength operation for drilling of via holes in AlGaN/GaN HEMTs on SiC substrates

By using a frequency-tripled Nd:YVO₄ laser source (355 nm) for drilling through-wafer via holes in SiC substrates, we can reduce the surface contamination and achieve better smoothness inside the via holes compared to use of the more common 1064-nm Nd:YVO₄ laser. The sheet and contact resistance of AlGaN/GaN HEMT layers grown on SiC substrates were similar after formation of vias by 355-nm laser drilling to those of the undrilled reference sample. By sharp contrast, 1064-nm laser drilling produces significant redeposition of ablated material around the via and degrades the electrical properties of the HEMT layers.     

激光熔覆成形薄壁金属制件精度的预测模型

为了控制激光熔覆成形薄壁金属制件的精度，分析了激光熔覆成形金属薄壁的工艺理论和影响因素。采用BP神经网络建立了激光功率、光斑直径、扫描速度和送粉率与金属零件壁厚的非线形关系模型和激光熔覆成形薄壁制件的精度控制系统。通过优化神经网络的权值和阈值，并引入动量因子和学习速率的自适应调整，克服了BP算法容易陷入局部最小值的问题。用实验参数作为训练样本对模型进行训练，并进行了误差分析。实验和仿真结果表明，训练样本和检验样本的最大相对误差分别为1.93％和1.19％，预测精度高。该网络模型可用于优化激光熔覆成形工艺参数和成形金属制件精度的在线实时控制。     

Microwave Characterization and Modeling of High Aspect Ratio Through-Wafer Interconnect Vias in Silicon Substrates

In this paper, we present the detailed fabrication process, high-frequency characterization, and modeling of through-wafer copper-filled vias ranging from 50- to 70-$mu$m-in diameter on 400-$mu$m-thick silicon substrates. The high aspect ratio via-holes were fabricated by carefully optimizing the inductively coupled plasma deep reactive ion etching process. The high aspect ratio via-holes are completely filled with copper using a bottom-up electroplating approach. The fabricated vias were characterized using different resonating structures based on which the inductance and resistance of the filled via-holes are extracted. For a single 70-$mu$m via, the inductance and resistance are measured to be 254 pH and 0.1$Omega$, respectively. In addition, the effect of the physical arrangement and distribution in multiple-via configurations on the resulting inductance is also evaluated with double straightly aligned quadruple and diagonally aligned quadruple vias. Physical mechanisms of the dependence was depicted by electromagnetic simulation. An equivalent-circuit model is proposed and model parameters are extracted to provide good agreement.     

激光微孔加工技术在刚挠性基材中的研究

刚挠结合印制板向高密度互联方向发展,要求线路更细,导通孔直径更小。适合刚挠结合印制板的微导通孔加工工艺在刚挠结合印制板制造工艺中起着关键作用,微孔加工工艺中普遍采用激光技术。文章分析了激光微孔加工中的各影响因素,用正交试验法作对比试验,优化各因素参数,讨论了各因素与基板材料的关系,并拟合出方程定量描述此种关系。根据优化方程选取激光微孔参数,在挠性与刚性基板材料上取得理想效果。     

Application of selective CVD tungsten for low contact resistance via filling to aluminum multilayer interconnection

Process parameters for selective chemical vapor deposition of tungsten to fill vias between aluminum or aluminum alloy multilevel metallization have been identified and demonstrated. By controlling two competing parallel reactions: Aluminum and hydrogen reductions of tungsten hexafluoride in one reduction step process, the specific contact resistivity was found to be in the range of 2.5 to 8.0 x 10⁻⁹ ohm-cm² for 1.8 micron diameter vias. This is at least one order of magnitude lower than the values reported by the previous workers. It was also observed that alloying the aluminum did not appear to affect the contact resistance significantly. In this experiment one cold wall experimental reactor, two cold wall production systems of two different models and one hot wall tube furnace were used to deposit selective CVD tungsten on aluminum or aluminum with 1% silicon first level metal. As a consequence of these findings, problems associated with filling straight wall vias of high aspect ratio in VLSI multilevel interconnection (i.e., high contact resistance, poor step coverage, electromigration, etc.) can now be alleviated or resolved. Therefore, the use of selective CVD tungsten in the existing aluminum IC metallization becomes very attractive and feasible.     

Robust porous SiOCH/Cu interconnects with ultrathin sidewall protection liners

Robust porous low-k/Cu interconnects have been developed for 65-nm-node ultralarge-scale integrations (ULSIs) with 180-nm/200-nm pitched lines and 100-nm diameter vias in a single damascene architecture. A porous plasma-enhanced chemical vapor deposition (PECVD)-SiOCH film (k=2.6) with subnanometer pores is introduced into the intermetal dielectrics on the interlayer dielectrics of a rigid PECVD-SiOCH film (k=2.9). This porous-on-rigid hybrid SiOCH structure achieves a 35% reduction in interline capacitance per grid in the 65-nm-node interconnect compared to that in a 90-nm-node interconnect with a fully rigid SiOCH. A via resistance of 9.7 /spl Omega/ was obtained in 100-nm diameter vias. Interconnect reliability, such as electromigration, and stress-induced voiding were retained with interface modification technologies. One of the key breakthroughs was a special liner technique to maintain dielectric reliability between the narrow-pitched lines. The porous surface on the trench-etched sidewall was covered with an ultrathin plasma-polymerized benzocyclobuten liner (k=2.7), thus enhancing interline time-dependent dielectric breakdown reliability. The introduction of a porous material and the control of the sidewall are essential for 65-nm-node and beyond scaled-down ULSIs to ensure high levels of reliability.     

Investigation of laser ablation on boron emitters for n‐type rear‐junction PERT type silicon wafer solar cells

n‐type silicon wafer solar cells are receiving increasing attention for industrial application in recent years, such as the n‐type rear‐junction Passivated Emitter Rear Totally‐diffused (PERT) solar cells. One of the main challenges in fabricating the n‐PERT solar cells is the opening of the rear dielectric for localized contacts. In this work laser ablation is applied to locally ablate the rear dielectric. We investigate the laser damage to the emitter at the laser‐ablated regions using the emitter saturation current density, J_0e,laser, extracted by two approaches. J_0e,laser is observed to be injection dependent due to high J₀₂ recombination caused by laser damage to the space charge region. By using the optimized laser ablation parameters, n‐PERT solar cells with an efficiency of up to 21.0% are realized. Copyright © 2015 John Wiley & Sons, Ltd.     

Plating of small blind vias [multilayer PCBs]

Metallization of laminates with blind vias on the dielectric side was performed by electroless copper plating with subsequent copper electroplating. The vertical cross section of blind vias with diameters between 125 and 75 μm were analyzed by reflective microscopy. Results indicate that ultrasonic vibration during the pretreatment processes of metallization enables complete electroless copper deposition of the inside wall of the small blind vias without any voids. Furthermore, the introduction of periodic pulse reversal current for the subsequent copper electroplating process resulted in high throwing power deposition. By employing these two protocols, it has been demonstrated that high throwing power deposition can be readily achieved for blind vias as small as 75 μm in diameter with an aspect ratio of 3:1     

管材激光弯曲规律的试验研究

通过实验研究管状件激光弯曲成形的机理以及成型规律。金属管状零件的激光弯曲成形是一种利用激光加热来实现构件的柔性成形技术,其基本原理是利用高能激光束扫描金属管表面,加热区域材料的热膨胀引起材料产生堆积,冷却后,该区域材料沿轴向上的缩短,导致了金属管朝向激光束的弯曲从而最终实现无模具成形。影响金属管状零件激光弯曲成形的工艺参数主要有激光功率、扫描角度、扫描次数、光斑直径和扫描速度。通过实验研究了工艺参数对弯曲角度的影响。在一定取值范围内,增大激光功率,增大扫描角度,增加扫描次数,降低扫描速度均可以使弯曲角度变大;增大光斑直径,弯曲角度会变小。     

Selectively deposited nickel film for via filling

A selective deposition process is used to fill vias in VLSI multilevel interconnection. Ni film is chosen as the via-filling material because of its compatibility with the underlying Al film. The vias are filled with a thin Pd film first and a thick Ni film. The deposited Ni film is uniform and smooth in the via regions. This film is not attacked by the plasma etch used in subsequent Al patterning; therefore, the design rule of overlapping the second metal on vias can be relaxed. The specific via resistance of this process is 4×10 ^-9Ω-cm². The via resistance increases about 30% after an exposure to 450°C for 8 h     

Modeling Thermal Stresses in 3-D IC Interwafer Interconnects

We present a finite-element-based analysis to determine if there are potential reliability concerns due to thermally induced stresses in interwafer copper via structures in three-dimensional (3-D) ICs when benzocyclobutene (BCB) is used as the dielectric adhesive to bond wafers. We first partially validate our approach by comparing computed results against two types of experimental data from planar ICs: 1) volume-averaged thermal stresses measured by X-ray diffraction in an array of parallel Cu lines passivated with TEOS and 2) studies of failures induced by thermal cycling via chain structures embedded in SiLK or SiCOH. In the volume-averaged thermal stress study, predicted stress slopes (dsigma/dT) agree well with other modeling results. Our computed stress slopes agree reasonably well with experimental data along the Cu line direction and normal to the Cu lines surface, but we underestimate the stress slope across the Cu line. In the case of via chains, computed von Mises stresses agree with the results of thermal cycle experiments; we predict failure when SiLK is used as a dielectric and predict no failure when SiCOH is used as the dielectric. The approach is then employed to study thermal stresses in interwafer Cu vias in 3-D IC structures bonded with BCB. Simulations show that the von Mises stresses in interwafer Cu vias decrease with decreasing pitch at constant via size, increase with decreasing via size at constant pitch, and decrease with decreasing BCB thickness. We conclude that there is a concern regarding the stability of interwafer Cu vias. Guidelines for design parameter values are estimated, e.g., interwafer via size, pitch, and BCB thickness. For 2.6-mum-thick BCB, computations indicate that via size should be larger than 3 mum at a pitch of 10 mum to avoid plastic yield of Cu vias     

Laser Drilling of Copper Foils for Electronics Applications

Single pulse drilling of copper foils and copper-coated dielectric circuit board materials, relevant to applications in micro-electronics packaging, has been investigated here using an enhanced peak power CO ₂-laser. The plasma generated during copper laser ablation, under these conditions, has been found to be self-extinguishing once the copper has been punched through, and does not materially impact the process. The analysis of the undercut formation in the copper coated laminates illustrated a direct link with the energy delivered to the dielectric after the copper has been laser ablated. Holes with zero undercut were obtained by the use of an acousto-optic modulator, used as a pulse shutter, to control the energy delivered to the dielectric. For unmodulated laser pulses, holes with zero undercut were obtained when drilling copper foils 35-mum thick. In general, when drilling copper-coated dielectrics with unmodulated pulses, holes with low undercut were obtained for peak powers <1.2 kW. However, the stochastic nature of copper drilling dominates the process in this regime. At higher peak powers (up to 1.8kW), a yield of 100% holes in copper is obtained, but this also results in significant undercut     

Optimization of via distribution and stacked via in multi-layered P/G networks

The usage of via stack was not carefully studied in previous multi-layered P/G (Power/Ground) network designs. However, with feature size scaling down, the resistance of via is increasing quickly and their influence on voltage drop of P/G networks has become obvious. In this paper, two optimization techniques for via placement are proposed, which are proved to be helpful in reducing on die voltage drop. Firstly, an efficient heuristic algorithm based on sensitivity analysis is presented to optimize via distribution in early design stage. Compared with even distribution design strategies, averagely the heuristic algorithm can reduce the worst voltage drop by 8.43% without adding more vias. Secondly, experiments demonstrated that using stacked vias in nonadjacent layers is powerful in eliminating “hot” areas which suffer from large voltage drop. Based on this observation, a heuristic algorithm is developed to further reduce the worst voltage drop. Experiments show that voltage drop distribution can be well optimized by combining these two strategies together.     

Electrical Characteristics of the Three-Dimensional Interconnection Structure for the Chip Stack Package with Cu through Vias

A chip stack specimen of a three-dimensional (3-D) interconnection structure with Cu vias of 75-μm diameter, 90-μm height, and 150-μm pitch was successfully fabricated using via hole formation with deep reactive ion etching (RIE), Cu via filling with pulse-reverse pulse electroplating, Si thinning, Cu/Sn bump formation, and flip-chip bonding. The contact resistance of a Cu/Sn bump joint and Cu via resistance could be determined from the slope of the daisy chain resistance versus the number of bump joints of the flip-chip specimen containing Cu vias. When the flip chip was bonded at 270°C for 2 min, the contact resistance of a Cu/Sn bump joint of 100-μm diameter was 6.74 mΩ, and the resistance of a Cu via of 75-μm diameter and 90-μm height was 2.31 mΩ. As the power transmission characteristics of the Cu through via, the S₂₁ parameter was measured up to 20 GHz.     

304不锈钢板料激光热应力成形试验研究

通过改变激光功率、扫描速度、光斑直径、扫描次数及板料宽度对2 mm厚度的AISI304不锈钢板料进行激光热应力弯曲试验, 分析了各工艺参数对弯曲角度的影响规律, 对工件表面烧蚀情况进行评价, 并对板料金相组织进行观察分析。试验结果表明: 在试验参数范围内激光扫描次数、光斑直径、扫描速度和板料宽度对弯曲角度呈近似线性规律, 而激光功率对弯曲角度的影响不呈线性规律; 较大的面能量密度产生较大的弯曲角度。可通过工艺参数的合理组合在保证板料表面质量的前提下采用较大的面能量密度进行扫描以提高弯曲变形的效率。以上研究为精确控制板料激光弯曲成形奠定基础。     

Laser-assisted via hole metallization in PCB materials

A novel via hole metallization method is presented, where the vias are drilled in polyimide/copper (PI/Cu) flexible printed circuit boards (PCBs) using KrF excimer pulses, and then pre-metallized using a scanned Ar⁺ laser. In the premetallization step, a thin (20–50 nm) and narrow (2–10 μm) palladium layer is deposited on the polyimide-covered side of the PCB and on the wall of the vias using the laser-induced chemical liquid-phase deposition method. After the pretreatment, the Pd covered holes are immersed into a Cu electroless plating bath. Plated copper vertical and horizontal interconnects are analyzed by optical microscopy, focused ion beam, profilometry and resistivity measurements. The results show that the copper deposits formed on the pre-metallized surface of PCBs have high chemical purity, excellent adhesion and almost bulk conductivity, but, so far, due to unclear reasons, high through hole resistance.     

高速多层PCB板中过孔的建模、仿真及分析

利用Hyperlynx软件对高速PCB板中所应用到的过孔进行建模与仿真,分析了过孔对流经其上信号的影响,并给出了改进、优化过孔的方法。仿真结果表明,在要求线上信号完整性高的情况下,使用过孔方式连接的电路得到了改善和优化。