Time-domain approach for synthesising SPICE-compatible models of power delivery networks of printed circuit board

Resonance noise, or power/ground bounce noise, between the power and ground planes of high-speed circuit packages is one of the main concerns of signal integrity or power integrity issues. A novel time-domain approach is proposed to extract the equivalent circuit models of power/ground planes by time-domain reflection and time-domain transmission waveforms. The extracted model can accurately predict the resonance behaviour of power/ground planes over a wide frequency range. These models can be efficiently incorporated into the HSPICE simulator for the consideration of power/ground bouncing noise in high-speed circuits.     

A Novel Time-Domain Approach for Extracting Broadband Models of Power Delivery NetworksWith Resonance Effect

Resonance noise, or power/ground bounce noise, on the power and ground planes of high-speed circuit packages is one of the main concerns of signal integrity or power integrity issues. A novel time-domain approach is proposed to synthesize the broadband models of the power/ground planes with resonance effect. Using waveforms either from measurements by time-domain reflectrometry or simulations by the finite-difference time-domain method, the time-domain step response of the planes is characterized with a pole-residue representation obtained through the matrix pencil method. Lumped circuit equivalent circuit models are then synthesized through the pole-residue representations. The synthesized model can accurately predict the resonance behavior of power/ground planes over a wide frequency range. These models can be efficiently incorporated into the currently available circuit simulator such as HSPICE for the consideration of power/ground bouncing noise in high-speed circuits. Three cases are tested to demonstrate the validity and broadband accuracy of the proposed approach.      

Modeling of multilayered power distribution planes using transmission matrix method

This paper presents a method for analyzing multilayered rectangular and irregular shaped power distribution planes in the frequency and time domain. The analysis includes the effect of vias on the power distribution network. The planes are modeled using a two dimensional array of distributed RLCG circuit elements. Planes are connected in parallel using vias, which are modeled as self and mutual inductors. For the computation of the power distribution impedances at specific points in the network, a multiinput and multioutput transmission matrix method has been used. This is much faster than Spice and requires smaller memory. Using the transmission matrix method, via effects and the effects of multiple rectangular power/ground plane pairs without and with decoupling capacitors have been analyzed for realistic structures.     

Physics-Based Via and Trace Models for Efficient Link Simulation on Multilayer Structures Up to 40 GHz

Analytical models for vias and traces are presented for simulation of multilayer interconnects at the package and printed circuit board levels. Vias are modeled using an analytical formulation for the parallel-plate impedance and capacitive elements, whereas the trace-via transitions are described by modal decomposition. It is shown that the models can be applied to efficiently simulate a wide range of structures. Different scenarios are analyzed including thru-hole and buried vias, power vias, and coupled traces routed into different layers. By virtue of the modal decomposition, the proposed method is general enough to handle structures with mixed reference planes. For the first time, these models have been validated against full-wave methods and measurements up to 40 GHz. An improvement on the computation speed of at least two orders of magnitude has been observed with respect to full-wave simulations.      

A compact multilayer IC package model for efficient simulation, analysis, and design of high-performance VLSI circuits

A multilayered integrated circuit (IC) package structure is composed of many signal layers, power layers, and ground layers. Particularly, the whole planes are assigned for the power and ground of the system. Accordingly, the generic circuit representation of such a complicated multilayer IC package becomes too complicated to efficiently evaluate its electrical performance. In this work, a novel compact package circuit model for the efficient simulation and analysis of such complicated IC packages is presented. Unlike the conventional models, current distributions within the package are modeled by introducing a compact partial plane circuit model. Thus, the proposed package model is much simpler than the conventional generic circuit models, while its accuracy is preserved. Thereby, today's complicated IC packages can be efficiently evaluated and analyzed. Its accuracy and efficiency are verified by benchmarking it with a conventional generic package circuit model; this conventional model may not be practical to use for package evaluation and analysis. It is then shown that the proposed model can be efficiently applied for the signal integrity verification of complicated IC packages and high-performance VLSI circuits.     

多层PCB 电源地平面返回路径阻抗的边界元分析

研究了多层印制电路板(PCB)中含有一个信号过孔的电源/地平面返回路径阻抗的频域特性,并分析采用添加短路过孔的方法减小多层PCB的输入阻抗.电源/地平面形成了径向传输线结构,反焊盘处的输入阻抗即为信号电流在电源/地平面间的返回路径阻抗.在电源/地平面外部边界施加PMC(完全导磁体)边界条件,在反焊盘处施加电流激励源,短路过孔轴向电场为零,采用高效的二维边界元法求解.计算了10GHz内电源/地平面返回路径的输入阻抗.结果表明:在两特性相同的平面之间添加短路孔可以降低输入阻抗,同时,电源、地平面的输入阻抗随频率变化交替呈现容性或感性,在反谐振频率处输入阻抗值可达几百欧姆,此外,在频率较低时输入阻抗可用静态电容或静态电感表示.采用基于全波分析的有限元软件验证了计算结果和计算方法的正确性.     

Efficient Simulation of Power Distribution Network by Using Integral-Equation and Modal-Decoupling Technology

A novel integral-equation equivalent-circuit method is proposed for the efficient electrical simulation of the power distribution network in the electronic package and printed circuit board. The total electromagnetic field inside the power distribution network is decoupled into two modes: the parallel-plate mode sandwiched between the power and ground planes and the transmission line mode propagating along the signal traces. An integral-equation method is then proposed to solve the parallel-plate mode. By discretizing the integral equation, the power-ground planes pair is equivalent to a ground network. Finally, this ground network is recombined with the transmission line mode to simulate the entire power distribution network. Meanwhile, the discontinuity due to the thru-hole via is also considered by an analytic formula. The proposed method decomposes the complex 3-D problem into two simple 2-D problems, and then extracts the equivalent circuits. Therefore, it greatly reduces the computing time and memory requirement. Through several examples, its accuracy and efficiency are validated.     

Analysis of power delivery network constructed by irregular-shaped power/ground plane including densely populated via-hole

The high speed and low power trend has imposed more and more importance on the design of the power distribution network (PDN) using multilayer printed circuit boards (PCBs) for modern microelectronic packages. This paper presents a fast and efficient analysis methodology in frequency domain for the design of a PDN with a power/ground plane pair, which considers the effect of irregular shape of the power/ground plane and densely populated via-holes. The presented method uses parallel-plate transmission line theory with equivalent circuit model of unit-cell grid considering three-dimensional geometric boundary conditions. Characteristics of PDNs implemented by perforated planes including a densely populated via-hole structure is quantitatively determined based on full-wave analysis using the finite-difference time-domain (FDTD) periodic structure modeling method and full-wave electromagnetic field solver. Using a circuit simulator such as popularly used SPICE and equivalent circuit models for via-hole structure and perforations, the authors have analyzed input-impedance of the power/ground plane pair. Since the presented method gives an accurate and fast solution, it is very useful for an early design of multilayer PCBs.     

Simulating package behavior under power dissipation using uniformthermal loading

The thermomechanical behavior of electronic packages under power dissipation is simulated using uniform thermal loading. Two packages are studied, a large periphery leaded plastic quad flat pack (PQFP) package and a more compact plastic ball grid array (PBCA) package, both mounted on a printed circuit board (PCB). Experimentally verified linear elastic finite element models are used to find the displacements at the predicted failure location during power dissipation, and then during uniform thermal loading. The results for the two cases are then analyzed to find correlations between power dissipation levels and equivalent heating temperatures. One use of the results could be to replace power cycling fatigue tests with thermal cycling tests, For the packages studied, the results revealed that very little uniform heating is required to simulate the thermomechanical effects at the failure location resulting from power dissipation. Due to the prestrained state of the packages at room temperature, power dissipation decreases the expansion mismatch while increasing the thermal mismatch between package and PCB     

Hybrid analytical modeling method for split power bus in multilayered package

As multiple chips are being integrated into a single package with increased operating frequency, switching noise coupling on power buses has become an important design issue. To reduce the noise coupling, a split power bus structure has been generally used in package substrates having multilayered power and ground planes. Consequently, there is an increasing need for an efficient method to analyze a split power bus in a multilayered package. This paper introduces a hybrid analytical modeling method for characterizing a split power bus in a multilayered package. The proposed method uses a resonant cavity model combined with a segmentation method. Furthermore, a port assignment technique and an associated calculation method for the equivalent circuit model parameter of the split gap are proposed. The proposed port assignment technique and the analytical equation make it possible to analyze a split power bus, especially in a multilayered package. To verify the proposed method, multilayered test packages are fabricated and tested by means of frequency-domain measurements. In addition, an optimal power bus design method was successfully demonstrated for suppressing noise coupling between chips on a single package. Finally, the proposed method and optimal power bus design method was verified using a series of frequency-domain and time-domain measurements.     

过孔转换信号完整性分析的区域分解有限元法

提出了一种基于区域分解的二维有限元法分析多层印制电路板电源/地平面中过孔转换结构的信号完整性.过孔电流产生的电磁场呈三维结构,其中,一部分电磁波沿过孔轴向传输,另一部分电磁波在电源/地平面间沿径向传播.采用一虚拟柱面将求解区域分割为过孔区和电源/地平面区.将过孔区建模为以周向磁场为主分量的二维轴对称问题,而将电源/地平面区建为以垂直电场为主分量的二维模型.首先求解电源/地平面区的二维边值问题获得分割边界上节点的波阻抗,然后将该波阻抗代入过孔区模型中分割边界节点的边界条件,从而计算出过孔信号传输的S参数.所提方法通过模型缩减可实现对微细过孔结构信号完整性的精确快速计算,且采用全波电磁场分析软件对算法的有效性和准确性进行了验证.     

Lumped-circuit model extraction for vias in multilayer substrates

Via interconnects in multilayer substrates, such as chip scale packaging, ball grid arrays, multichip modules, and printed circuit boards (PCB) can critically impact system performance. Lumped-circuit models for vias are usually established from their geometries to better understand the physics. This paper presents a procedure to extract these element values from a partial element equivalent circuit type method, denoted by CEMPIE. With a known physics-based circuit prototype, this approach calculates the element values from an extensive circuit net extracted by the CEMPIE method. Via inductances in a PCB power bus, including mutual inductances if multiple vias are present, are extracted in a systematic manner using this approach. A closed-form expression for via self inductance is further derived as a function of power plane dimensions, via diameter, power/ground layer separation, and via location. The expression can be used in practical designs for evaluating via inductance without the necessity of full-wave modeling, and, predicting power-bus impedance as well as effective frequency range of decoupling capacitors.     

EMI mitigation with multilayer power-bus stacks and via stitchingof reference planes

General methods for reducing printed circuit board (PCB) emissions over a broad band of high frequencies are necessary to meet EMI requirements, as processors become faster and more powerful. One mechanism by which EMI can be coupled off a PCB or multichip module (MCM) structure is from high-frequency fringing electric fields on the DC power and reference planes at the substrate periphery. An approach for EMI mitigation by stitching multiple ground planes together along the periphery of multilayer PCB power-bus stacks with closely spaced vias is reported and quantified in this paper. Power-bus noise induced EMI and coupling from the board edges is the major concern herein. The EMI at 3 m for different via stitch spacing and layer thickness is modeled with the finite-difference time domain (FDTD) method. Design curves and an empirical equation are extracted from a parametric study to summarize the variation of the radiated EMI as a function of layer thickness and stitch spacing     

Simplified modeling of parallel plate resonances on multilayerprinted circuit boards

Multilayer printed circuit boards (PCBs) are currently used in various areas of electronics such as telecommunications. However, high crosstalk between signal vias can cause degradation of performance for these kinds of structures. Resonances of parallel ground or power planes can increase this crosstalk. In this study, a simplified approach to the modeling of these resonances is described. It is assumed that the fields inside the board have characteristically only two-dimensional (2-D) variation. When this hypothesis is valid, it is shown that resonances can be measured on two-layer prototyping boards and simulated using a 2-D finite-difference model. It is additionally noted that a previously suggested method of using coaxial ground vias to suppress coupling between vias is not necessarily effective if there are resonant parallel plates on the board. Agreement between measured and modeled results is good enough for practical design purposes. The main advantages of the method used in this study compared to the more robust three-dimensional (3-D) simulation models are savings in time and costs. Additionally, prototyping is much easier on two than multilayer boards     

Modeling and analysis of power distribution networks for Gigabit applications

As the operating frequency of digital systems increases and voltage swing decreases, it becomes very important to characterize and analyze power distribution networks (PDNs) accurately. This paper presents the modeling, simulation, and characterization of the PDN in a high-speed printed circuit board (PCB) designed for chip-to-chip communication at a data rate of 3.2 Gbps. The test board consists of transmitter and receiver chips wirebonded onto plastic ball grid array (PGBA) packages on a PCB. In this paper, a hybrid method has been applied for analysis, which consists of the transmission matrix method (TMM) in the frequency domain and macromodeling method in the time domain. As an initial step, power/ground planes have been modeled using TMM. Then, the macromodel of the power/ground planes has been generated at the desired ports using macromodeling. Finally, the macromodel of the planes, transmission lines, and nonlinear drivers have been simulated in standard SPICE-based circuit simulators for computing power supply noise. In addition to noise computation, the self and transfer impedances of power/ground planes have been computed and the effect of decoupling capacitors on power supply noise has been analyzed. The methods discussed have been validated using hardware measurements.     

Composite effects of reflections and ground bounce for signal line through a split power plane

The signal propagating along a microstrip line over a slot on the power plane will suffer from composite effects of reflected noise by a discontinuity in signal return path and ground bounce between power and ground planes. A new equivalent circuit model is proposed and simulations are performed for multilayer structures to characterize these composite effects. An experimental setup is devised to demonstrate significant coupling between signal lines due to the slot-induced ground bounce. Favorable comparison between the simulation and measured results validates the proposed equivalent circuit model and analysis approach.     

Modeling and transient simulation of planes in electronic packages

This paper presents a modeling and simulation approach for ground/power planes in high speed packages. A plane pair structure is first characterized in terms of its impedance (Z) matrix at arbitrary port locations in the frequency domain. This solution is then extended for multiple plane pairs under the assumption that skin effect is prominent at higher frequencies causing isolation between the layers. Since the solutions are in analytical form, the frequency and transient response can be computed efficiently requiring small computational time. To develop spice models, equivalent circuits are constructed using resonator models with passive elements using model order reduction methods. This paper also discusses a method for incorporating decoupling capacitors into the plane models. The simulation results show good correlation with measured data     

IC封装中键合线传输结构的仿真分析

随着高频高速集成电路制造工艺的不断进步,电子封装技术的发展也登上了一个新高度。作为微电子器件制造过程中的重要步骤之一,封装中的传输线、过孔、键合线等互连结构都可能对电路的性能产生影响,因此先进的集成电路封装设计必须要进行信号完整性分析。介绍了一种键合线互连传输结构,采用全波分析软件对模型进行仿真,着重分析与总结了键合线材料、跨距、拱高以及微带线长度、宽度五种关键设计参数对封装系统中信号完整性的影响,仿真结果对封装设计具有实际的指导作用。     

Cost-effective chip-on-heat sink leadframe package for 800-Mb/s/lead applications

Chip-on-heat sink leadframe (COHS-LF) packages offer a simple, low-cost chip encapsulation structure with advanced electrical and thermal performance for high-speed integrated circuit applications. The COHS-LF package is a novel solution to the problems of increased power consumption and signal bandwidth demands that result from high-speed data transmission rates. Not only does it offer high thermal and electrical performance, but also provides a low-cost short time-to-market package solution for high-speed applications. In general, there are two main memory packages employed by the most popular high-speed applications, double data rate (DDR) SDRAM. One is the cheaper, higher parasitic leadframe packages, such as the thin small outline packages (TSOPs), and the other is the more expensive, lower parasitic substrate-based packages, such as the ball grid array (BGA). Due to the requirement for higher ambient temperature and operating frequency for high-speed devices, DDR2 SDRAM packages were switched from conventional TSOPs to more expensive chip-scale packages (i.e., BGA) with lower parasitic effects. And yet, by using an exposed heat sink pasted on the surface of the chip and packed in a conventional leadframe package, the COHS-LF is a simpler, lower cost design. Results of a three-dimensional full-wave electromagnetic field solver and SPICE simulator tests show that the COHS-LF package achieves less signal loss, propagation delay, edge rate degradation, and crosstalk than the BGA package. Furthermore, transient analysis using the wideband T-3/spl pi/ models optimized up to 5.6 GHz for signal speeds as high as 800 Mb/s/lead demonstrates the accuracy of the equivalent circuit model and reconfirms the superior electrical characteristics of COHS-LF package.     

Coupling of vias in electronic packaging and printed circuit board structures with finite ground plane

A full wave method is presented for modeling and analyzing multiple interactions among vertical vias in densely packaged integrated circuits and printed circuit board with ground plane of finite extent. In such structures, the TEM mode in the planar structure is excited and can propagate and cause interaction of waves among vias. Reflections will also occur at the edges of the finite ground plane. The electromagnetic analysis methodology is an extension of the previous methodology in analyzing multiple scattering among vias for infinite ground plane . The analysis is based upon the cylindrical wave mode expansion of the magnetic field Green's function, the Foldy-Lax multiple scattering formalism and utilizing the resonator modes of a circular cavity. The circular resonator modes are transformed into cylindrical waves onto the cylindrical via structures. Numerical results illustrate the physics of the underlying resonance scattering problems. We consider the cases of a) two coupled active vias of differential mode and b) two coupled vias of common mode. Results are also illustrated for ground plane resonance and the effects of shorting vias on such resonance. The effects of off-centering and the presence of idle vias are also illustrated.