Mobility-field behavior of fully depleted SOI MOSFET's

This work reports measured effective mobility vs. effective vertical electric field and the accompanying experimental method of extraction for the fully depleted (FD) SOI MOSFET. The effective channel mobility vs. effective vertical electric field behavior was investigated as a function of the SOI film doping concentration, the SOI back-gate bias, and the SOI film thickness. The validity of using the approximation, Q_i=C_ox(V_GS-V_TH), for the inversion charge density in FD SOI is examined and experimentally confirmed     

Switch-off behavior of floating-body PD SOI MOSFET's

In this work, we report a detailed study of the switch-off transients of the drain current in floating-body partially depleted (PD) SOI MOSFETs. When operated in the kink region and at frequency in the MHz range, floating body effects improve the current capability of these devices. However, we point out a serious drawback, that has been previously overlooked: the same effects lead to orders of magnitude increase of the off-state leakage current calling for a trade-off between speed and power dissipation     

Electron mobility in short-channel MOSFET's with series resistances

Electron mobilities have been measured in transistors with channel lengths from 5.0 to 0.5 µm. The originally high low-field mobility µ0≈ 700 cm²/V . s seems to be greatly decreased by parasitic series resitances, to a minor degree also by surface scattering.     

Scaled silicon MOSFET's: universal mobility behavior

We use a fully quantum-mechanical model to study the inversion layer mobility in a silicon MOS structure. The importance of depletion charge and surface-roughness scattering on the effective electron mobility is examined. The magnitude of the mobility is found to be considerably reduced by both depletion charge and interface-roughness scattering. The appropriate weighting coefficients a and b for the inversion and depletion charge densities in the definition of the effective electric field, which eliminate the doping dependence of the effective electron mobility, are also calculated. These are found to differ from the commonly used values of 0.5 and 1. In addition, the weighting coefficient for the depletion charge density is found to be significantly influenced by the actual shape of the doping profile and can be either >1 or <1     

Substrate current measurements in thin SOI MOSFET's at 300 and 77 K

Measurements of impact-ionized hole current in fully depleted SOI (silicon-on-insulator) MOSFETs at room temperature and liquid nitrogen temperature are reported. The measured current exhibits properties similar to those of the substrate current in bulk transistors, except for higher drain biases when the parasitic bipolar in the device is significant. Since the body contact is effective in collecting only a small fraction of the total generated hole current, the body contact cannot be used to eliminate the bipolar action in thin SOI, at least for channel widths on the order of 10 μm     

Inversion-layer capacitance and mobility of very thin gate-Oxide MOSFET's

Inversion-layer capacitance has been experimentally characterized and identified to be the main cause of the second-order thickness-dependence of MOSFET characteristics. Field-dependent channel mobilities of both electrons and holes were independent of gate-oxide thicknesses from 50 to 450 Å, e.g., there is no evidence of the alleged mobility degradation in very thin gate-oxide MOSFET's. Subthreshold slope, insignificantly affected by the inversion-layer capacitance, follows the simple theory down to ∼ 35 Å of oxide thickness. The empirical equations for inversion-layer Capacitance and mobilities versus electric field are proposed.     

Monte Carlo simulation of electron transport properties inextremely thin SOI MOSFET's

Electron mobility in extremely thin-film silicon-on-insulator (SOI) MOSFET's has been simulated. A quantum mechanical calculation is implemented to evaluate the spatial and energy distribution of the electrons. Once the electron distribution is known, the effect of a drift electric field parallel to the Si-SiO₂ interfaces is considered. The Boltzmann transport equation is solved by the Monte Carlo method. The contribution of phonon, surface-roughness at both interfaces, and Coulomb scattering has been considered. The mobility decrease that appears experimentally in devices with a silicon film thickness under 20 nm is satisfactorily explained by an increase in phonon scattering as a consequence of the greater confinement of the electrons in the silicon film     

Comparison of hole mobility in LOCOS-isolated thin-film SOIp-channel MOSFET's fabricated on various SOI substrates

The hole mobility of LOCOS-isolated thin-film silicon-on-insulator (SOI) p-channel MOSFET's fabricated on SOI substrates with different buried oxide thickness has been investigated. Two types of SOI wafers are used as a substrate: (1) SIMOX wafer with 100-nm buried oxide and (2) bonded SOI wafer with 100-nm buried oxide. Thin-film SOI p-MOSFET's fabricated on SIMOX wafer have hole mobility that is about 10% higher than that on bonded SOI wafer. This is caused by the difference in the stress under which the silicon film is after gate oxidation process. This increased hole mobility leads to the improved propagation delay time by about 10%     

Time-dependent snapback in thin-film SOI MOSFET's

During pulsed stressing of SOI MOSFETs for ESD characterization, the turn-on voltage of the parasitic bipolar transistor was observed to be a function of the stress pulse-width. This observation can be understood in terms of a capacitive charging model. The theory behind this time-dependent snapback is presented in this letter along with the experimental results. Comparisons with bulk-Si devices indicate that this phenomenon is specific to SOI and is a manifestation of the floating body effect     

Electron and hole mobility enhancement in strained SOI by waferbonding

N- and p-MOSFETs have been fabricated in strained Si-on-SiGe-on-insulator (SSOI) with high (15-25%) Ge content. Wafer bonding and H-induced layer transfer techniques enabled the fabrication of the high Ge content SiGe-on-insulator (SGOI) substrates. Mobility enhancement of 50% for electrons (with 15% Ge) and 15-20% for holes (with 20-25% Ge) has been demonstrated in SSOI MOSFETs. These mobility enhancements are commensurate with those reported for FETs fabricated on strained silicon on bulk SiGe substrates     

Transient pass-transistor leakage current in SOI MOSFET's

This paper reports an accurate method of measuring the anomalous leakage current in pass-gate MOSFET's unique to SOI devices. A high-speed measurement setup is used to provide experimental results, and to quantify the magnitude of leakage. Particularly, great care is taken to measure only the device leakage current and not the currents due to parasitic capacitances. Systematic influences of different factors such as temperature, bias, device history, and device structure on this leakage current are experimentally established,     

Subthreshold kinks in fully depleted SOI MOSFET's

Measured current-voltage characteristics of scaled, floating-body, fully depleted (FD) SOI MOSFET's that show subthreshold kinks controlled by the back-gate (substrate) bias are presented. The underlying physical mechanism is described, and is distinguished from the well known kink effect in partially depleted devices. The physical insight attained qualifies the meaning of FD/SOI and implies new design issues for low-voltage FD/SOI CMOS     

Subthreshold slope of thin-film SOI MOSFET's

Silicon-on-insulator (SOI) n-channel transistors have been made in thin (90 nm) silicon films. Both modeling and experimental results show that excellent subthreshold slopes can be obtained (62 mV/ decade) when the silicon film thickness is smaller than the maximum depletion depth in the transistor channel. For comparison, the subthreshold slope of transistors made in thicker films is also reported.     

Scaling theory for double-gate SOI MOSFET's

A scaling theory for double-gate SOI MOSFETs, which gives guidance for device design (silicon thickness t_si; gate oxide thickness t_ox) that maintains a subthreshold factor for a given gate length is discussed. According to the theory, a device can be designed with a gate length of less than 0.1 μm while maintaining the ideal subthreshold factor. This is verified numerically with a two-dimensional device simulator     

Electron mobility in the inversion layers of fully depleted SOI films

The dependences of the electron mobility μ_eff in the inversion layers of fully depleted double–gate silicon-on-insulator (SOI) metal–oxide–semiconductor (MOS) transistors on the density N _e of induced charge carriers and temperature T are investigated at different states of the SOI film (inversion–accumulation) from the side of one of the gates. It is shown that at a high density of induced charge carriers of N _e > 6 × 10¹² cm^–2 the μeff(T) dependences allow the components of mobility μ_eff that are related to scattering at surface phonons and from the film/insulator surface roughness to be distinguished. The μ_eff(N _e ) dependences can be approximated by the power functions μ_eff(N _e) ∝ N _e ^?n . The exponents n in the dependences and the dominant mechanisms of scattering of electrons induced near the interface between the SOI film and buried oxide are determined for different N _e ranges and film states from the surface side.     

Reduction of threshold voltage sensitivity in SOI MOSFET's

The threshold voltage sensitivity, of fully depleted SOI MOSFET's to variations in SOI silicon film thickness was examined through both simulation and device experiments. The concept of designing the channel V_th implant to achieve a constant dose within the film, rather than a constant doping concentration, was studied for a given range of film thicknesses. Minimizing the variation in retained dose reduced the threshold voltage sensitivity to film thickness for the range of t_si examined. One-dimensional process simulations were performed to determine the optimal channel implant condition that would reduce the variation in retained dose using realistic process parameters for both NMOS and PMOS device processes. SOI NMOS transistors were fabricated. The experimental results confirmed the simulation findings and achieved a reduced threshold voltage sensitivity     

Degradation in thin-film SOI MOSFET's caused by single-transistorlatch

The measurement of anomalous hot-carrier damage in thin-film n-channel SOI MOSFETs is reported. Due to the presence of a parasitic bipolar transistor between the source and drain, the minimum drain voltage for breakdown in these devices occurs when the device is biased in subthreshold. Using charge-pumping measurements, it is shown that if the device is biased in this regime, where single-transistor latch occurs, hot holes are injected into the gate oxide near the drain. Consequently, the maximum allowable drain voltage for these devices is governed by the parasitic bipolar properties of the SOI MOSFET     

Surface potential at threshold in thin-film SOI MOSFET's

The usual condition for threshold in bulk MOSFETs, of equal rates of change with gate voltage of the inversion and bulk charges, is suitably modified to describe threshold in fully depleted SOI MOSFETs. Using this modified condition the value of the surface potential at threshold in fully depleted transistors is obtained analytically in terms of device dimensions, film doping level, and applied voltages. The results are in excellent agreement with one-dimensional numerical simulations, and it is shown that the surface potential at threshold may differ significantly from 2φ_F, the value conventionally assumed     

Numerical analysis of switching characteristics in SOI MOSFET's

The paper presents an analysis of switching characteristics in SOI MOSFET's. By using a two-carrier and two-dimensional transient SOI simulator, calculated waveforms having good agreement with experimental results are obtained. Further analysis revealed the mechanism of switching characteristics. The motion of majority carriers features the switching characteristics for SOI devices in both turn-on and turn-off stages, although the current overshooting time and the substrate potential recovery time are strongly affected by bias conditions. The magnitude of drain current overshoot in the turn-on stage also proved to be a function of substrate impurity concentration.     

Moderate inversion in SOI MOSFET's with grain boundaries

Our previous model for the effects of grain boundaries on the strong-inversion (linear region) conductance of silicon-on-insulator (SOI) MOSFET's is extended to account for moderate inversion. The extension, which is supported by measurements of laser-recrystallized devices, predicts a nearly exponential dependence for the conductance on the (front) gate voltage that is controlled by the grain boundaries.