高性能L5-Dispatcher的性能评测

为支持基于请求内容调度的策略，提出并实现了一个集中调度、分布路由的可扩展路由机制。与通常的单前端机不同，提出的可扩展路由结构由多个前端机组成，一个前端机执行集中调度任务（即调度器），其余的前端机执行分布路由任务（即转发器）。测试数据表明，一台运行调度器程度的PⅢ933主机的吞吐量为450000conns/s，可满足80台转发器同时请求调度服务。换言之，有80台转发器可同时转发请求数据或响应数据，即分布式前端总共可提供16Gbps的吞吐量。     

微控器在试验中实现的前端设备远程复位控制

介绍了用微控制器实现的兰州重离子加速器冷却储存环工程（HIRFL-CSR）束流注入线电源控制系统中前端网关的远程复位控制,其中包括用AT89C51单片机实现的前端智能电路模块、AT89C51单片机的运行程序、中心控制室通讯应用程序。该系统成功实现了科研中束流调节人员可以在不用到现场的情况下远程复位前端发生死机的网关。该系统工作稳定，抗干扰强，没有发生误操作，实现了科研当中对前端设备的远程控制，大大提高了科研工作人员的工作效率。     

前途无量[Intel 3GHz Pentium 4]

当3.06GHz的Pentium 4对于大多数人来说还是镜花水月的时候，新一代的3GHz Pentium4又闪亮登场了。虽然从工作频率上看，这款3GHz Pentium 4比以往的3.06GHz还低了60MHz，但是其前端总线却达到了800MHz，而以往Pentium 4产品的最高前端总线为533MHz。前端总线频率的提高意味着处理器与内存控制器之间拥有了更高速的数据传送通道。以往的533MHz前端总线可以提供4.2GBps的带宽，而800MHz则具备了6.4GBps的峰值带宽。从数据上看，这会带来50％的带宽提升，不过这只是理论数据，并不意味着采用800MHz前端总线的处理器的性能要比533M…     

ClojureScript：前端世界的Lisp

又一门前端语言 曾经看到有程序员这样抱怨：“前端技术发展到现在，感觉上已~Java还重量级了。”各种框架、构建工具、新语言在为前端开发提供了更多的选择的同时，也增加了它的复杂度。     

某型导弹测试仪插件远程诊断系统前端的设计

本文介绍了一种基于Internet在PC上实现的一个远程故障诊断系统的前端。前端由前端计算机和以AT89C52单片机为核心设计的智能数据采集卡组成。使用了由AT命令集控制的MODEM调制解调技术，通过公用电话网．实现实时远程数据采集、处理及管理功能。     

GPS接收机前端设计的要求及实现

从ＧＰＳ信号特点出发，对接收机前端设计要求进行了分析，并提出了实现方案，实验结果与设计性能完全一致，从而解决了ＧＰＳ接收机设计中射频（ＲＦ）前端的难点。     

应用于图象融合的高集成度视频信号采集系统

为配合多波段图象实时融合系统的研制，设计和开发了高速、高集成度，并具有广泛通用性的前端视频信号采集系统。该系统的设计和开发采用了专用视频解码芯片和大规模可编程逻辑器件（EPLD）以及VHDL语言。系统具有集成度高、可靠性好、性能优良、体积小、接口简单、采样参数在线可编程修改等特点。其应用于多波段图象采集和融合系统中，作为前端图象采集部分取得了良好的效果。同时，该设计也可作为前端图象采集部分用于其他图象处理系统中。     

迎接前端性能的挑战

2009年12月，业界盛会第四届D2前端技术论坛在杭州成功举办，来自口碑网的秦歌为大家分享了关于前端性能优化的经验，而个人秀环节，hax与army关于语法着色器的性能PK更是成为整个会议的亮点，这也预示着在新的一年里前端性能将成为前端工程师关注的重点。     

工业控制设备前端信息集成管理的研究与实现

本文讨论了在连续过程生产中ＣＩＭＳ的应用之一，工业控制设备前端信息集成管理的基本思想，提出了统一格式的操作平台为目的设备前端服务器的框架结构，并在此基础上设计和实现了一个应用于八·五攻关项目应用工厂的设备前端服务器（ＭａｃｈｉｎｅＦｒｏｎｔＥｎｄＳｅｒｖｅｒ简称ＭＦＥ），阐述了该系统的基本结构及开发策略。     

基于现场总线的风粉智能测量前端的开发与实现

根据火电厂在线监测一次风速与煤粉浓度的要求，研究开发了一种基于现场总线的风粉智能测量前智，介绍了该前端所采用的一些软，硬件技术，现场使用表明，该前端测量精确，易于操作，通讯可靠，工作稳定。     

Lex和yacc在Delphi中的应用

本文介绍如何在Delphi中利用专用工具lex和yacc创建简单编译器的过程。并给出一个简单的自定义可视化编译器的制作实例。     

A*: a language for implementing language processors

A* is an experimental language designed to facilitate the creation of language-processing tools. It is analogous either to an interpreted yacc with Awk as its statement language, or to a version of Awk which processes programs rather than records. A* offers two principal advantages over the combination of lex, yacc, and C: a high-level interpreted base language and built-in parse tree construction. A* programmers are thus able to accomplish many useful tasks with little code. This paper describes the motivation for A*, its design, and its evolution. Experience with A* is described, and then the paper concludes with an analysis of that experience     

Design, construction, and application of a generic visual languagegeneration environment

The implementation of visual programming languages (VPLs) and their supporting environments is time-consuming and tedious. To ease the task, researchers have developed some high-level tools to reduce the development effort. None of these tools, however, can be easily used to create a complete visual language in a seamless way as the lex/yacc tools do for textual language constructions. This paper presents the design, construction and application of a generic visual language generation environment, called VisPro. The VisPro design model improves the conventional model-view-controller framework in that its functional modules are decoupled to allow independent development and integration. The VisPro environment consists of a set of visual programming tools. Using VisPro, the process of VPL construction can be divided into two steps: lexicon definition and grammar specification. The former step defines visual objects and a visual editor, and the latter step provides language grammars with graph rewriting rules. The compiler for the VPL is automatically created according to the grammar specification. A target VPL is generated as a programming environment which contains the compiler and the visual editor. The paper demonstrates how VisPro is used by building a simple visual language and a more complex visual modeling language for distributed programming     

Ytracc: A parse browser for yacc grammars

We describe a program for the display and exploration of complex, domain-specific information: ytracc, an interactive grammar debugging tool for compiler writers. The ytracc system provides the designer of a yacc grammar a method of tracing a parser as it uses the grammar, ytracc captures the states of the parse as it is carried out. The captured parse can then be replayed forwards or backwards, step-by-step, or subtree-by-subtree, as defined by the non-terminals of the grammar. The tool has been successfully used by students as an assistant in an advanced undergraduate compiler construction class, and we use the tool in our everyday work.     

Very fast YACC-compatible parsers (for very little effort)

We have developed a yacc-compatible parser generator that creates parsers that are 2.0 to 6.0 times faster than those generated by yacc or bison. Our tool, mule, creates directly-executable, hard-coded parsers in ANSI; yacc produces interpreted, table-driven parsers. Two attributes distinguish mule from other parser generators that create hard-coded LR parsers; mule is compatible wtih yacc (including yacc's peculiar error recovery mechanisms), and mule does absolutely none of the complex automata analysis of previous hard-coded-parser generators. Mule creates simple, fast parsers after very little analysis. © 1998 John Wiley & Sons, Ltd.     

Automatic detection and diagnosis of faults in generated code for procedure calls

In this paper, we present a compiler testing technique that closes the gap between existing compiler implementations and correct compilers. Using formal specifications of procedure-calling conventions, we have built a target-sensitive test suite generator that builds test cases for a specific aspect of compiler code generators: the procedure-calling sequence generator. By exercising compilers with these specification-derived target-specific test suites, our automated testing tool has exposed bugs in every compiler tested on the MIPS and one compiler on the SPARC. These compilers include some that have been in heavy use for many years. Once a fault has been detected, the system can often suggest the nature of the problem. The testing system is an invaluable tool for detecting, isolating, and correcting faults in today's compilers.     

ForCES体系结构下基于Click的FE模型实现研究

本文主要对ForCES体系结构下的转发单元FE建模,并基于Click软件路由器对其实现进行了实验性研究。文章首先对FE模型作了深入分析,使用ASN．1语言对FE的能力和状态、拓扑连接以及元数据等信息做出形式化描述,提出了基于Click的FE模型实现方案,并利用lex/yacc工具将模型转换为For/CES协议层可执行代码。最后,通过模拟试验对FE模型的正确性作了验证。     

Structured dataflow analysis for arrays and its use in an optimizing compiler

We extend the well-known interval analysis method so that it can be used to gather global flow information for individual array elements. Data dependences between all array accesses in different basic blocks, different iterations of the same loop, and across different loops are computed and represented as labelled arcs in a program flow graph. This approach results in a uniform treatment of scalars and arrays in the compiler and builds a systematic basis from which the compiler can perform numerous global optimizations. This global dataflow analysis is performed as a separate phase in the compiler. This phase only gathers the global relationships between different accesses to a variable, yet the use of this information is left to the code generator. This organization substantially simplifies the engineering of an optimizing compiler and separates the back end of the compiler (e.g. code generator and register allocator) from the flow analysis part. The global dataflow analysis algorithm described in this paper has been implemented and used in an optimizing compiler for a processor with deep pipelines. This paper describes the algorithm and its compact implementation and evaluates it, both with respect to the accuracy of the information and to the compile-time cost of obtaining and using it.     

减少多种子内建自测试方法硬件开销的有效途径

提出一个基于重复播种的新颖的BIST方案，该方案使用侦测随机向量难测故障的测试向量作为种子，并利用种子产生过程中剩余的随意位进行存储压缩；通过最小化种子的测试序列以减少测试施加时间．实验表明，该方案需要外加硬件少，测试施加时间较短，故障覆盖率高，近似等于所依赖的ATPG工具的故障覆盖率．在扼要回顾常见的确定性BIST方案的基础上，着重介绍了文中的压缩存储硬件的方法、合成方法和实验结果．