Gate length scalability of n-MOSFETs down to 30 nm: Comparisonbetween LDD and non-LDD structures

Gate length scalability of LDD and non-LDD n-MOSFETs are investigated in terms of resistance to short-channel effects. Extremely small gate electrodes are delineated using electron beam direct writing and highly selective dry-etching techniques. An LDD MOSFET with As-implanted 15-nm-deep junctions shows a superior scalability down to 30 nm. In contrast, in the case of a non-LDD MOSFET having Sb-δ-doped 18-nm-deep junctions, the drain induced barrier lowering (DIBL) mechanism limits the minimum gate length to around 80 nm, at which favorable device operation is achieved. The difference between built in potential of source/drain junctions (around 0.1 eV) of LDD and non-LDD devices is found to remarkably affect short channel characteristics in the sub-0.1-μm region     

Vertical Enhancement-Mode InAs Nanowire Field-Effect Transistor With 50-nm Wrap Gate

We present results on fabrication and dc characterization of vertical InAs nanowire wrap-gate field-effect transistor arrays with a gate length of 50 nm. The wrap gate is defined by evaporation of 50-nm Cr onto a 10-nm-thick HfO₂ gate dielectric, where the gate is also separated from the source contact with a 100-nm SiO_x, spacer layer. For a drain voltage of 0.5 V, we observe a normalized transconductance of 0.5 S/mm, a subthreshold slope around 90 mV/dec, and a threshold voltage just above 0 V. The highest observed normalized on current is 0.2 A/mm, with an off current of 0.2 mA/mm. These devices show a considerable improvement compared to previously reported vertical InAs devices with SiN_x, gate dielectrics.     

Cat-CVD SiN-passivated AlGaN-GaN HFETs with thin and high Al composition barrier Layers

The effect of SiN surface passivation by catalytic chemical vapor deposition (Cat-CVD) on Al/sub 0.4/Ga/sub 0.6/N-GaN heterostructure field-effect transistors (HFETs) was investigated. The channel sheet resistance was reduced by the passivation due to an increase in electron density, and the device characteristics of the thin-barrier HFETs were significantly improved by the reduction of source and drain resistances. The AlGaN(8 nm)-AlN(1.3 nm)-GaN HFET device with a source/drain distance of 3 /spl mu/m and a gate length of 1 /spl mu/m had a maximum drain current density of 0.83 A/mm at a gate bias of +1.5 V and an extrinsic maximum transconductance of 403 mS/mm. These results indicate the substantial potential of Cat-CVD SiN-passivated AlGaN-GaN HFETs with thin and high Al composition barrier layers.     

The impact of uniform strain applied via bonding onto plastic substrate on MOSFET performance

For the first time, this letter presents a novel post-backend strain applying technique and the study of its impact on MOSFET device performance. By bonding the Si wafer after transistor fabrication onto a plastic substrate (a conventional packaging material FR-4), a biaxial-tensile strain (/spl sim/0.026%) was achieved globally and uniformly across the wafer due to the shrinkage of the bonded adhesive. A drain-current improvement (average /spl Delta/I/sub d//I/sub d//spl sim/10%) for n-MOSFETs uniformly across the 8-in wafer is observed, independent of the gate dimensions (L/sub g//spl sim/55 nm -0.530 /spl mu/m/W /spl sim/2-20 /spl mu/m). The p-MOSFETs also exhibited I/sub d/-improvement by /spl sim/7% under the same biaxial-tensile strain. The strain impact on overall device characteristics was also studied, including increased gate-induced drain leakage and short-channel effects.     

Experimental Method to Extract Effective Channel Length of Nanoscale n-MOSFETs

An experimental method of extracting the effective channel length L_eff from measured gate tunneling current (I_g) of nanoscale n-MOSFETs is proposed. The tunneling current from gate to the source and drain (I_gsd) was measured while applying a reverse bias to the substrate, and it was corrected for the depletion effect of the source/drain junctions. The gate tunneling current to the substrate (I_gc) was obtained by subtracting I_gsd from I_g. L_eff was calculated using a linear extrapolation of the I_gc versus gate length plot. The proposed method is a very simple and quite accurate method of extracting L_eff which does not require any additional assumptions and parameter extraction.     

Surface passivation of InGaP/InGaAs/GaAs pseudomorphic HEMTs with ultrathin GaS film

We report on the successful surface passivation of wide recess InGaP/InGaAs/GaAs pseudomorphic HEMTs with MBE-grown ultrathin GaS film (2 nm) employing a single precursor, tertiarybutyl-galliumsulfide-cubane ([(t-Bu)GaS]/sub 4/). At the recess length of 1.1 /spl mu/m, a GaS-passivated device with a 0.5-/spl mu/m gate length has the maximum transconductance (g/sub m max/) of 347 mS/mm, which is about 40% higher than that of 240 mS/mm for a device without GaS passivation. We found that one of the causes of an increased g/sub m max/ is the decrease of sheet resistance on the recessed surface because GaS passivation has reduced the depletion layer. Meanwhile, the two-terminal gate-to-drain reverse breakdown voltage (BV/sub gd/) was reduced after GaS passivation. The BV/sub gd/ is independent of the recess length between gate and drain (L/sub gd/) for GaS-passivated devices, unlike that for devices without GaS passivation. According to our calculation of the BV/sub gd/ involving the effects of impact ionization and the interface state, the BV/sub gd/ becomes almost independent of the L/sub gd/, when the interface state density (N/sub int/) is below 1/spl times/10/sup 12/ cm/sup -2/. Then, the calculated surface potential at the recess region is less than 0 eV. This result suggests that GaS passivation can remarkably reduce the N/sub int/ at the recess region.     

Gate-induced drain leakage current degradation and its time dependence during channel hot-electron stress in n-MOSFETs

The effects of channel hot-electron stress on the gate-induced drain leakage current (GIDL) in n-MOSFETs with thin gate oxides have been studied. It is found that under worst case stress, i.e. a high density of generated interface states Delta D/sub it/, the enhanced GIDL exhibits a significant drain voltage dependence. Whereas Delta D/sub it/ increases significantly the leakage current at low V/sub d/, it has minor effects at high V/sub d/. On the other hand, the electron trapping was found to increase the leakage current rather uniformly over both low and high V/sub d/ regions. In addition, GIDL degradation can be expressed as a power law time dependence (i.e. Delta I/sub leak/=A.t/sup n/), and the time dependence value n varies according to the dominant damage mechanism (i.e. electron trapping against Delta D/sub it/), similar to that reported for on-state device degradation.<>     

High-power AlGaN/GaN HEMTs for Ka-band applications

We report on the fabrication and high-frequency characterization of AlGaN/GaN high-electron mobility transistors (HEMTs) grown by molecular beam epitaxy (MBE) and metal-organic chemical vapor deposition (MOCVD). In devices with a gate length of 160 nm, a record power density of 10.5 W/mm with 34% power added efficiency (PAE) has been measured at 40 GHz in MOCVD-grown HEMTs biased at V/sub DS/=30 V. Under similar bias conditions, more than 8.6 W/mm, with 32% PAE, were obtained on the MBE-grown sample. The dependence of output power, gain, and PAE on gate and drain voltages, and frequency have also been analyzed.     

High-performance enhancement-mode AlGaN/GaN HEMTs using fluoride-based plasma treatment

We report a novel approach in fabricating high-performance enhancement mode (E-mode) AlGaN/GaN HEMTs. The fabrication technique is based on fluoride-based plasma treatment of the gate region in AlGaN/GaN HEMTs and post-gate rapid thermal annealing with an annealing temperature lower than 500/spl deg/C. Starting with a conventional depletion-mode HEMT sample, we found that fluoride-based plasma treatment can effectively shift the threshold voltage from -4.0 to 0.9 V. Most importantly, a zero transconductance (g/sub m/) was obtained at V/sub gs/=0 V, demonstrating for the first time true E-mode operation in an AlGaN/GaN HEMT. At V/sub gs/=0 V, the off-state drain leakage current is 28 /spl mu/A/mm at a drain-source bias of 6 V. The fabricated E-mode AlGaN/GaN HEMTs with 1 /spl mu/m-long gate exhibit a maximum drain current density of 310 mA/mm, a peak g/sub m/ of 148 mS/mm, a current gain cutoff frequency f/sub T/ of 10.1 GHz and a maximum oscillation frequency f/sub max/ of 34.3 GHz.     

A study of the effects of tunneling currents and reliability of sub-2 nm gate oxides on scaled n-MOSFETs

This work examined various components of direct gate tunneling currents and analyzed reliability of ultrathin gate oxides (1.4–2 nm) in scaled n-metal-oxide-semiconductor field effective transistor (MOSFETs). Direct gate tunneling current components were studied both experimentally and theoretically. In addition to gate tunneling currents, oxide reliability was investigated as well. Constant voltage stressing was applied to the gate oxides. The oxide breakdown behaviors were observed and their effects on device performance were studied. The ultrathin oxides in scaled n-MOSFETs used in this study showed distinct breakdown behavior and strong location dependence. No “soft” breakdown was seen for 1.5 nm oxide with small area, implying the importance of using small and more realistic MOS devices for ultrathin oxide reliability study instead of using large area devices. Higher frequency of oxide breakdowns in the source/drain extension to the gate overlap region was then observed in the channel region. Possible explanations to the observed breakdown behaviors were proposed based on the quantum mechanical effects and point-contact model for electron conduction in the oxide during the breakdown. It was concluded that the source/drain extension to the gate overlap regions have strong effects on the device performance in terms of both gate tunneling currents and oxide reliability.     

Is gate line edge roughness a first-order issue in affecting the performance of deep sub-micro bulk MOSFET devices?

An experimental study of the effects of gate line edge roughness (LER) on the electrical characteristics of bulk MOSFET devices was performed. Device simulation had previously predicted that gate LER causes off-state current to increase. In our experiments, gate LER was deliberately introduced in devices with 40 nm or longer physical gate length, and we found about 3X I/sub OFF/ increase (for 40 nm gate length) in the I/sub OFF/-I/sub ON/ plot. In our devices, Source/Drain (S/D) extensions are produced by implants self-aligned to gate edges. Simulation results indicate that what really matters is the roughness induced of the S/D to channel junctions by gate LER. Implantation scattering and dopant diffusion cause the S/D to channel junctions to be smoother than the gate edges. This will partially reduce the differences in the I/sub OFF/-I/sub ON/ curves caused by differing amounts of gate LER. By optimizing our process flows, we obtained a minimized gate LER (EdgeRMS<2 nm). We believe that the consequence of this minimized LER is secondary to the impact of other process variations across wafer for devices with 40 nm or longer gate length.     

1.5 nm direct-tunneling gate oxide Si MOSFET's

In this paper, normal operation of a MOSFET with an ultra-thin direct-tunneling gate oxide is reported for the first time. These high current drive n-MOSFET's were fabricated with a 1.5 nm direct-tunneling gate oxide. They operate well at gate lengths of around 0.1 μm, because the gate leakage current falls in proportional to the gate length, while the drain current increases in inverse proportion. A current drive of more than 1.0 mA/μm and a transconductance of more than 1,000 mS/mm were obtained at a gate length of 0.09 μm at room temperature. These are the highest values ever obtained with Si MOSFET's at room temperature. Further, hot-carrier reliability is shown to improve as the thickness of the gate oxide is reduced, even in the 1.5 nm case. This work clarifies that excellent performance-a transconductance of over 1,000 mS/mm at room temperature-can be obtained with Si MOSFET's if a high-capacitance gate insulator is used     

Improved DC and RF performance in Si/SiGe n-MODFETs with ion-implanted buried p-well doping

The dc and RF characteristics of Si/SiGe n-MODFETs with buried p-well doping incorporated by ion implantation are reported. At a drain-to-source biasV/sub ds/ of +1 V devices with 140-nm gate length had peak transconductance g/sub m/ of 450 mS/mm, and maximum dc voltage gain A/sub v/ of 20. These devices also had "off-state" drain current I/sub off/ of 0.15 mA/mm at V/sub g/=-0.5 V. Control devices without p-well doping had A/sub v/=8.1 and I/sub off/=13 mA/mm under the same bias conditions. MODFETs with p-well doping had f/sub T/ as high as 72 GHz at V/sub ds/=+1.2 V. These devices also achieved f/sub T/ of 30 GHz at a drain current, I/sub d/, of only 9.8 mA/mm, compared to I/sub d/=30 mA/mm for previously published MODFETs with no p-well doping and similar peak f/sub T/.     

DC performance of deep submicrometer Schottky-gated n-channel Si:SiGe HFETs at low temperatures

N-type Schottky-gated Si:SiGe heterostructure field-effect transistors with physical gate lengths between 70 and 450nm are characterized over a wide temperature range (T=10 K...300 K) for low electric fields. The room-temperature maximum low-field transconductance increases 61% to 440 mS/mm at T=10 K for the 70-nm device. The minimum subthreshold slope is 14...19 mV/dec at T=10 K. The off-state currents I/sub OFF/ are limited by parallel conduction at high temperatures and by the gate leakage current at low temperatures. Substrate leakage currents are found to be due to generation of carriers within the drain/substrate depletion layer and only make a minor contribution to I/sub OFF/. Operation of the devices at the lowest temperature is found to result in the occurrence of the floating-body kink effect, as a consequence of substrate freeze-out and subsequent self-biasing by impact ionization currents. Low temperature characteristics exhibit a nonlinear low-field drain current dependence on the drain voltage, due to the presence of parasitic Schottky source/drain contacts. An extraction method for access resistance consistent with this phenomenon is presented.     

DC, RF, and microwave noise performances of AlGaN/GaN HEMTs on sapphire substrates

High-performance AlGaN/GaN high electron-mobility transistors with 0.18-/spl mu/m gate length have been fabricated on a sapphire substrate. The devices exhibited an extrinsic transconductance of 212 mS/mm, a unity current gain cutoff frequency (f/sub T/) of 101 GHz, and a maximum oscillation frequency (f/sub MAX/) of 140 GHz. At V/sub ds/=4 V and I/sub ds/=39.4 mA/mm, the devices exhibited a minimum noise figure (NF/sub min/) of 0.48 dB and an associated gain (Ga) of 11.16 dB at 12 GHz. Also, at a fixed drain bias of 4 V with the drain current swept, the lowest NFmin of 0.48 dB at 12 GHz was obtained at I/sub ds/=40 mA/mm, and a peak G/sub a/ of 11.71 dB at 12 GHz was obtained at I/sub ds/=60 mA/mm. With the drain current held at 40 mA/mm and drain bias swept, the NF/sub min/,, increased almost linearly with the increase of drain bias. Meanwhile, the Ga values decreased linearly with the increase of drain bias. At a fixed bias condition (V/sub ds/=4 V and I/sub ds/=40 mA/mm), the NF/sub min/ values at 12 GHz increased from 0.32 dB at -55/spl deg/C to 2.78 dB at 200/spl deg/C. To our knowledge, these data represent the highest f/sub T/ and f/sub MAX/, and the best microwave noise performance of any GaN-based FETs on sapphire substrates ever reported.     

Nanoscale silicon MOSFETs: A theoretical study

We have carried out extensive numerical modeling of double-gate, nanoscale silicon n-metal oxide semiconductor field effect transistors (MOSFETs) with ultrathin, intrinsic channels connecting bulk, highly doped electrodes. Our model takes into account two most important factors limiting the device performance as the gate length is reduced, namely the gate field screening by source and drain, and quantum mechanical tunneling from source to drain. The results show that the devices with small but plausible values of gate oxide thickness t/sub ox/ and channel thickness t (both of the order of 2 nm) may retain high ON current, good saturation and acceptable subthreshold slope even if the gate length L is as small as /spl sim/5 nm, with voltage gain above unity all the way down to L/spl ap/2 nm (channel length L/sub c/=L+2t/sub ox//spl ap/5 nm). However, as soon as L is decreased below /spl sim/10 nm, specific power (per unit channel width) starts to grow rapidly. Even more importantly, threshold voltage becomes an extremely sensitive function of L,t, and t/sub ox/, creating serious problems for reproducible device fabrication.     

High-energy tail electrons as the mechanism for the worst-case hot-carrier stress degradation of the deep submicrometer N-MOSFET

Experimental evidence, based on sensitively modulating the concentration of the high-energy tail of the electron energy distribution, reveals an important trend in the mid-to-high gate stress voltage (V/sub g/) regime, where device degradation is seen to continuously increase with the applied V/sub g/, for a given drain stress voltage V/sub d/. The shift in the worst-case degradation point from V/sub g//spl ap/V/sub d//2 to V/sub g/=V/sub d/, depicting an uncorrelated behavior with the substrate current, is caused by the injection of the high-energy tail electrons into the gate oxide, when the oxide field near the drain region becomes increasingly favorable as V/sub g/ approaches V/sub d/. This letter offers an improved framework for understanding the worst-case hot-carrier stress degradation of deep submicrometer N-MOSFETs under low bias condition.     

Charge trapping in ultrathin hafnium silicate/metal gate stacks

Charge trapping characteristics of MOCVD HfSi/sub x/O/sub y/ (20% SiO/sub 2/) gate stack of n-MOSFETs during substrate injection have been investigated. Positive constant voltage stress (CVS) and constant current stress (CCS) were applied at the gate of TiN-HfSi/sub x/O/sub y/-SiO/sub 2//p-Si n-MOSFETs having EOT of 2 nm. Significant electron trapping is observed from the positive shift of threshold voltage (/spl Delta/V/sub t/) after stress. Curve fitting of the threshold voltage shift data confirms power law dependence for Hf-silicate gate stacks. Charge pumping measurements for both cases showed significant electron trapping at bulk Hf-silicate while interface trap generation was comparatively insignificant. A turn-around effect is noticed for /spl Delta/V/sub t/ as the stress current and voltage increases under CCS and CVS. Dependence of spatial distribution of charge trapping at shallow traps on stress level in the Hf-silicate film and redistribution of trapped charges during and after removal of stress is possibly responsible for the turn-around effect.     

547-GHz f/sub t/ In/sub 0.7/Ga/sub 0.3/As-In/sub 0.52/Al/sub 0.48/As HEMTs with reduced source and drain resistance

We fabricated 30-nm gate pseudomorphic channel In/sub 0.7/Ga/sub 0.3/As-In/sub 0.52/Al/sub 0.48/As high electron mobility transistors (HEMTs) with reduced source and drain parasitic resistances. A multilayer cap structure consisting of Si highly doped n/sup +/-InGaAs and n/sup +/-InP layers was used to reduce these resistances while enabling reproducible 30-nm gate process. The HEMTs also had a laterally scaled gate-recess that effectively enhanced electron velocity, and an adequately long gate-channel distance of 12nm to suppress gate leakage current. The transconductance (g/sub m/) reached 1.5 S/mm, and the off-state breakdown voltage (BV/sub gd/) defined at a gate current of -1 mA/mm was -3.0 V. An extremely high current gain cutoff frequency (f/sub t/) of 547 GHz and a simultaneous maximum oscillation frequency (f/sub max/) of 400 GHz were achieved: the best performance yet reported for any transistor.     

A normally off GaN n-MOSFET with Schottky-barrier source and drain on a Si-auto-doped p-GaN/Si

We have fabricated an enhancement-mode n-channel Schottky-barrier-MOSFET (SB-MOSFET) for the first time on a high mobility p-type GaN film grown on silicon substrate. The metal contacts were formed by depositing Al for source/drain contact and Au for gate contact, respectively. Fabricated SB-MOSFET exhibited a threshold voltage of 1.65 V, and a maximum transconductance(g/sub m/) of 1.6 mS/mm at V/sub DS/=5V, which belongs to one of the highest value in GaN MOSFET. The maximum drain current was higher than 3 mA/mm and the off-state drain current was as low as 3 nA/mm.