Immunity against temperature variability and bias point invariability in double gate tunnel field effect transistor

The weak dependence of the Tunnel Field Effect Transistor (TFET) device characteristics on temperature provides an edge over the conventional MOSFETs in terms of its reliable operation over a wide temperature range applications. This study focusses on the analog/RF performance comparison of DG-TFET and DG-MOSFET, and the impact of temperature variations on some of the key parameters like VIP₃ and intrinsic device gain (g_m * R_out) and the variation of the optimum bias point. In the study of linearity and analog performance, g_m3 (third order derivative of I_ds ? V_gs), VIP₃ in conjunction with intrinsic gain are considered to select the optimum bias point to achieve high gain and better linearity performance. The impact of temperature variations on the ambipolar behavior of a TFET has also been studied.     

Impact of the lateral straggle on the Analog and RF performance of TFET

In this work, the effect of the variation in lateral straggle on TFETs performance is demonstrated. The ion implantation technique during fabrication process causes the extension of dopants from source/drain region towards the channel. Even though the use of non-zero tilt angle at the time of ion implantation is necessary to avoid the channeling effect, however, series resistance, threshold voltage roll offs, switching speed and effective channel length of the device get affected by the non abrupt doping profile at the source/drain-body junction. It is established earlier that TFET is very convenient for Analog/RF application owing to its below 60 mV/decade subthreshold swing and reduced short channel effects. In order to show the effect of lateral straggle on TFET’s performance, various Analog figure of merits (FOMs) such as drain current (I_d), transconductance (g_m), transconductance generation factor (g_m/I_d), output resistance (R_o), intrinsic gain (g_mR_o) and RF figure of merits (FOMs) like unity gain cutoff frequency (f_T), transit frequency of maximum available power gain (f_MAX) are investigated for the variation in straggle parameter from 0 nm to 5 nm in order to optimize the device performance. The circuit performance of the device for different lateral straggle is carried out using common source amplifier.     

Impact of high-k gate dielectric on analog and RF performance of nanoscale DG-MOSFET

Now a days, high-k dielectrics have been investigated as an alternative to Silicon dioxide (SiO₂) based gate dielectric for nanoscale semiconductor devices. This paper is an attempt to characterize the analog and RF performance of the high-k metal gate (HKMG) double gate (DG) metal oxide semiconductor field effect transistor (MOSFET) in nanoscale through 2-D device simulation. The results demonstrates the impact of high-k oxide layer as single and gate stack (GS). The key idea behind this investigation is to provide a physical explanation for the improved analog and RF performance exhibited by the device. The major figures of merit (FOMs) studied in this paper are transconductance (g_m), output conductance (g_d), transconductance generation factor (g_m/I_D), early voltage (V_EA), intrinsic gain (A_V), cut off frequency (f_T), transconductance frequency product (TFP), gain frequency product (GFP) and gain transconductance frequency product (GTFP). The effects of downscaling of channel length (L) on analog performance of the proposed devices have also been presented. It has been observed that the performance enhancement of GS configurations (k=7.5 i.e device D5 in the study) is encouraging as far as the nanoscale DG-MOSFET is concerned. Also it significantly reduces the short channel effects (SCEs). Parameters like DC gain of (91.257 dB, 43.436 dB), nearly ideal values (39.765 V⁻¹, 39.589 V⁻¹) of TGF, an early voltage of (2.73 V, 16.897 V), cutoff frequency (294 GHz, 515.5 GHz) and GTFP of (5.14×10⁵ GHz/V, 1.72×10⁵ GHz/V) for two different values of V_DS=0.1 V and 0.5 V respectively are found to be close to ideal values. Analysis shows an opportunity for realizing high performance analog and RF circuits with the device proposed in this paper i.e. device D5.     

Simulation study of Insulated Shallow Extension Silicon On Nothing (ISESON) MOSFET for high temperature applications

This paper analyzes the effect of temperature variation on various device architectures i.e. Insulated Shallow Extension Silicon On Nothing (ISESON), ISE and SON MOSFET using ATLAS 3D device simulator for 45 nm gate length. The simulation results obtained with the ATLAS has been validated by comparing it with reported experimental data of SON MOSFET. The simulation results demonstrate that out of three device designs, the ISESON MOSFET is the most suitable device for high speed, low voltage and high temperature applications. The integration of ISE and SON onto the conventional bulk MOSFET leads to the enhancement in analog device performance in terms of device efficiency (g_m/I_ds), device gain (g_m/g_d), output resistance (R_out) and early voltage (V_ea).     

Impact of gate metal work-function engineering for enhancement of subthreshold analog/RF performance of underlap dual material gate DG-FET

This work presents a systematic comparative study of analog/RF performance for underlap dual material gate (U-DMG) DG NMOSFET. In previous works, improved device performances have been achieved by use of high dielectric constant (k) spacer material. Although high-k spacers improve device performance, the intrinsic gain of the device reduces. For the analog circuits applications intrinsic gain is an important parameter. Hence, an optimized spacer material having dielectric constant, k = 7.5 has been used in this study and the gain is improved further by dual-material gate (DMG) technology. In this paper we have also studied the effect of gate material having different work function on the U-DMG DG NMOSFETs. This device exploits a step function type channel potential created by DMG for performance improvement. Different parameters such as the transconductance (g_m), the gain per unit current (g_m/I_ds), the intrinsic gain (g_mR_o), the intrinsic capacitance, the intrinsic resistance, the transport delay and, the inductance of the device have been analyzed for analog and RF performance analysis. Analysis suggested that the average intrinsic gain, g_m/I_d and g_m are increase by 22.988%, 16.10% and 27.871% respectively compared to the underlap single-material gate U-DG NMOSFET.     

Carrier transport mechanisms and photovoltaic properties of Au/p-ZnPc/Al device

The dark current density–voltage characteristic of Au/ZnPc/Al device at room temperature has been investigated. Results showed a rectification behavior. At low forward bias, the current density was found to be ohmic, while at high voltages, space charge limited the current mechanism dominated by exponential trapping levels. Junction parameters such as rectification ratio (RR), series resistance (R_s), and shunt resistance (R_sh) were found to be 9.42, 9.72 MΩ, and 0.88 × 10³ MΩ, respectively. The current density–voltage characteristics under white light illumination (100 W/m²) gives values of 0.55 V, 3 × 10⁻³ A/m², 0.18 and 5.8 × 10⁻⁴% for the open circuit voltage, V_oc, the short circuit current density (J_sc), the fill factor (FF), and conversion efficiency (η), respectively.     

Study of body and oxide thickness variation on analog and RF performance of underlap DG-MOSFETs

The underlap double gate MOSFET (UDG-MOSFET) has been well established as a potential candidate for the RF applications. However, before implementation the various process related variations are required to be addressed for the better dependability. In this paper, the effect of process dependent parameter variations on the RF performance of the UDG-MOSFET is analyzed. The process dependent parameters considered are the oxide and the body thicknesses. The RF performance of UDG-MOSFET is analyzed as a function of RF figure of merits (FOMs), intrinsic capacitance (C_gs, C_gd), intrinsic resistance (R_gs, R_gd), transport delay (τ_m), inductance (L_sd) and analog FOMs transconductance (g_m), transconductance generation factor (g_m/I_d), output resistance (R_o) and intrinsic gain (g_mR_o). The analysis is performed using the non-quasi static (NQS) small signal model of the UDG-MOSFET.     

HCS degradation of 5 nm oxide high-voltage PLDMOS

Hot carrier (HC) injection, inducing drain and gate leakage current increase in 5 nm oxide p-channel LDMOS transistors, is investigated. Devices with two different drain implants are studied. At low gate voltage (V_GS) and high drain voltage (V_DS), reduction of the ON-resistance (R_ON) is observed. At stress times at which R_ON almost reaches its constant level, an increase of the drain leakage in OFF state (V_DS = −60 V, V_GS = 0 V) is observed. Longer stress time leads to increased gate leakage and in some cases oxide breakdown. In contrast to what was reported for devices with 25 nm gate oxide thickness, the threshold voltage of 5 nm gate oxide PLDMOS transistors does not drift. The experimental data can be fully explained by hot carrier injection and the oxide damage can be explained by two different and competing degradation mechanisms. By combining experimental data and TCAD simulations we are further capable to locate the hot spot of maximum oxide damage in the accumulation (Acc) region of the PLDMOS.     

The investigation of Al-doped ZnO as an electron transporting layer for visible-blind ultraviolet photodetector based on n-ZnO nanorods/p-Si heterojunction

An n-ZnO nanorods/p-Si heterojunction photodetector with Al-doped ZnO (AZO) as an electron transporting layer was fabricated. The heterojunction with 20 nm AZO film showed a better characteristic than that of the device without AZO, and it displays a rectification ratio of 8470 at ±3 V and a turn-on voltage of 1.8 V. Also, based on spectral responsivity measurement, the device with AZO coating showed higher responsivity and better visible-blind detectivity than those without AZO, and the peak responsivity of the photodetector with AZO was as high as ~0.49 A/W at 354 nm. Furthermore, the photodetector with AZO layer showed a bigger UV–visible responsivity ratio (R_354 nm / R_546 nm) than that of the photodetector without AZO coating at −2 V. The role of AZO layer was illustrated through energy band theory and the electron transport mechanism.     

Aggregation,crystallization, and resistance properties of poly(3-hexylthiophene-2,5-diyl) solid films gel-cast from CHCl3/p-xylene mixed solvents

In this study we found that the gelation time and crystallinity of P3HT solid films are adjustable when aging and casting from CHCl₃/p-xylene mixed solvents. After aging for 36 h in pure p-xylene, CHCl₃, or various mixtures of the two as cosolvents, we found that the solid P3HT film gel-cast from 20 vol% CHCl₃ had the highest degree of crystallinity of its main chain (ϕ_m = 0.54), highest melting point of its main chain (T_m = 232.7 °C), fastest gelation time (30 min), largest melting enthalpy of its main chain (ΔH_m = 19.81 J g⁻¹), and lowest resistance (R_P = 0.76 MΩ); the latter value was three orders and one order of magnitude lower than those of the films cast from pure CHCl₃ (ca. 110 MΩ) and pure p-xylene (ca. 4.4 MΩ), respectively. In differential scanning calorimetry scans, we attribute the presence of melting peaks near 75 °C to the solid-to-solid phase transition of the side chain crystallites of P3HT, thereby affecting the aggregation of the P3HT main chain and resulting in the changes in resistance, crystallinity, melting enthalpy, and melting point of the gel-cast P3HT solid films.     

Performance analysis of nanoscale GeSn MOSFETs for mixed-mode circuit applications

Using extensive numerical analysis we investigate the impact of Sn ranging 0–6% in compressively strained GeSn on insulator (GeSnOI) MOSFETs for mixed-mode circuit performance at channel lengths (L_g) ranging 100–20 nm with channel thickness values of 10 and 5 nm. Our results reveal that 10 nm thick Ge_0.94Sn_0.06 channel MOSFETs produce improvement of peak transconductance g_m, peak gain Av, peak cut-off frequency f_T and maximum frequency of oscillations f_max by 80.5%, 18.8%, 83.5% and 81.7%, respectively compared with equivalent GeOI device at L_g =20 nm. Furthermore, such devices exhibit 78.8% increase in ON-current I_ON while yield 44.5% reduction in delay as compared to Ge control devices enabling them attractive for logic applications. Thinning of the channel thickness from 10 to 5 nm increases peak Av, peak transconductance efficiency and reduces output conductance and OFF-current I_OFF while degrading other parameters in all GeSnOI and control Ge devices.     

Analysis of recursive convolutional codes and turbo codes as sources with memory

The paper proposes a general method to analyze discrete sources with memory. Besides the classical entropy, we define new information measures for discrete sources with memory, similar to the information quantities specific to discrete channels. On the base of this method, we show for the first time that, as result of convolutional and turbo encoding, sources with memory are obtained. We apply this information analysis method for the general case of a recursive convolutional encoder of rate R_CC = 1/n₀ and memory of order m, and for a turbo encoder of rate R_TC = 1/3, with two systematic recursive convolutional component encoders. Each component encoder has memory of order m, and is built based on the same primitive feedback polynomial. For the convolutional and turbo codes, the information quantities H(Y/S), H(S,Y), H(S/Y), H(Y), H(S) and I(S,Y) have been computed, where S and Y denote the set of states and the set of messages of the encoder, respectively. The analysis considered two cases: n₀ ≤ m + 1 and n₀ > m + 1. When n₀ = m + 1, the mutual information I(S,Y) is maximum and equal to m, as is the entropy of the set of states. For turbo codes, the quantity I(S,Y) also depends on the input bit and on its probability.     

DC and microwave characteristics of Lg 50 nm T-gate InAlN/AlN/GaN HEMT for future high power RF applications

The DC and microwave characteristics of L_g = 50 nm T-gate InAlN/AlN/GaN High Electron Mobility Transistor (HEMT) on SiC substrate with heavily doped n+ GaN source and drain regions have demonstrated using Synopsys TCAD tool. The proposed device features an AlN spacer layer, AlGaN back-barrier and SiN surface passivation. The proposed HEMT exhibits a maximum drain current density of 1.8 A/mm, peak transconductance (g_m) of 650 mS/mm and ft/fmax of 118/210 GHz. At room temperature, the measured carrier mobility, sheet charge carrier density (n_s) and breakdown voltage are 1195 cm²/Vs, 1.6 × 10¹³ cm⁻² and 18 V respectively. The superlatives of the proposed HEMTs are bewitching competitor for future monolithic microwave integrated circuits (MMIC) applications particularly in W-band (75–110 GHz) high power RF applications.     

Study of fin tapering effect in nanoscale symmetric dual-k spacer (SDS) hybrid FinFETs

Symmetric Dual-k Spacer (SDS) Hybrid FinFETs is a novel device, which combines three significant technologies i.e., 2-D ultra-thin-body (UTB), 3-D FinFET, and symmetric spacer engineering on a single silicon on insulator (SOI) platform. For the first time, this article systematically analyzes the impacts of non-rectangular fin shape on various performance metrics of SDS Hybrid FinFETs. Under distinctive inclination fin angles as prescribed by the process technology, the performances of the device at different fin heights are examined. This work evaluates the response of fin tapering as well as fin height on parameters like threshold voltage (V_th), subthreshold slope (SS), on current (I_on), transconductance (g_m), transconductance generation factor (TGF), and total gate capacitance (C_gg) in SDS Hybrid FinFETs. Optimum structural configuration is thus proposed to fabricate the hybrid device in sub-20 nm FinFET architecture.     

Effect of fullerene doping on the electrical properties of P3HT/PCBM layers

Poly (3-hexylthiophene-2, 5-diyl) (P3HT) and its blend with Phenyl-C₆₁-Butyric acid-Methyl-Ester (PCBM) and fullerene (C₆₀) thin films were prepared and their electrical properties for memory applications were studied. Due to doping, a sharp decrease in the resistance for a P3HT:PCBM:C₆₀ device was observed at around 70 °C which makes it useful for thermal switching applications. Addition of C₆₀ to P3HT:PCBM blend gave a high value for R_RESET/R_SET in thermal switching. For bias switching, threshold voltage reduces to 1.4 V from 25 V with the addition of C₆₀ to P3HT layer.     

Self-aligned inversion n-channel In0.2Ga0.8As/GaAs metal–oxide–semiconductor field-effect-transistors with TiN gate and Ga2O3(Gd2O3) dielectric

A self-aligned process for fabricating inversion n-channel metal–oxide–semiconductor field-effect-transistors (MOSFET’s) of strained In_0.2Ga_0.8As on GaAs using TiN as gate metal and Ga₂O₃(Gd₂O₃) as high κ gate dielectric has been developed. A MOSFET with a 4 μm gate length and a 100 μm gate width exhibits a drain current of 1.5 mA/mm at V_g = 4 V and V_d = 2 V, a low gate leakage of <10^?7 A/cm² at 1 MV/cm, an extrinsic transconductance of 1.7 mS/mm at V_g = 3 V, V_d = 2 V, and an on/off ratio of ～10⁵ in drain current. For comparison, a TiN/Ga₂O₃(Gd₂O₃)/In_0.2Ga_0.8As MOS diode after rapid thermal annealing (RTA) to high temperatures of 750 °C exhibits excellent electrical and structural performances: a low leakage current density of 10^?8–10^?9 A/cm², well-behaved capacitance–voltage (C–V) characteristics giving a high dielectric constant of ～16 and a low interfacial density of state of ～(2～6) × 10¹¹ cm^?2 eV^?1, and an atomically sharp smooth Ga₂O₃(Gd₂O₃)/In_0.2Ga_0.8As interface.     

Pyrene functioned diarylfluorenes as efficient solution processable light emitting molecular glass

In this paper, we described a new category of solution processable small molecule organic light emitting materials, the pyrene functioned diarylfluorenes: 2PE-PPF and DPE-PPF. They emit blue light in solution and green light in film, and show high thermal stability with the 5% weight loss temperature (T_d) over 400 °C. The glass transition temperature (T_g) for 2PE-PPF and DPE-PPF is 102 °C and 147 °C, respectively. These molecules are interesting molecular glass and they have good film forming abilities. Smooth and uniform film could be obtained by spin-coating. This character enables them able to be used in solution processed OLEDs by spin-coating or jet-printing. Single layered device using 2PE-PPF as the active material shows a turn-on voltage of 3.2 V, brightness over 8000 cd/m² and current efficiency up to 2.55 cd/A. Double layered device by inserting TPBI as the hole-blocking electron-transporting layer increases the maximum efficiency to 5.83 cd/A.     

A new ultra low-power,universal OTA-C filter in subthreshold region using bulk-drive technique

In this paper, a new ultra low-power universal OTA-C filter which can properly operate in all modes of operation (voltage, current, trans-resistance and trans-conductance) is presented. However, in order to reduce the power consumption effectively, the proposed circuit uses subthreshold transistors which are biased at I_a = 50 nA, I_b = 150 nA. Furthermore, using the bulk-drive technique leads to a reduced power consumption as well as the supply voltage of ±0.3 V. Moreover, the grounded capacitors are used to effectively reduce the parasitic effects. However, the result of sensitivity analysis shows that the proposed circuit has a very low sensitivity to the values of active and passive circuit elements such as: trans-conductance (g_m) and capacitance (C) values. Furthermore, the proposed circuit uses the minimum number of active elements to effectively reduce the power consumption as well as the chip area. Finally, the proposed filter is designed and simulated in HSPICE using 0.18µm CMOS technology parameters, while HSPICE simulation results have very close agreement with theoretical results obtained from MATLAB, which justifies the design accuracy and low-power performance of the proposed universal filter.     

Study of process induced variability of germanium-pTFET in analog and RF domain

Germanium (Ge) tunnel field effect transistor (TFET) is considered to be an excellent solution to resolve the low on-currents issue of Silicon-based TFETs. Whereas, process variability in any low technology node devices (sub-100 nm) is a crucial subject of matter which affects the device reliability and dependability in advanced SoC applications. In this brief, we have investigated the two main process induced variability a) the thickness of the germanium body b) the thickness of gate oxide in Ge-pTFET using Sentaurus TCAD device simulation. The analysis is performed in complete analog domain along with the study of intrinsic RF performance parameters using small signal equivalent model with non-quasi static effect of the device under consideration. The process induced variability is estimated on the figure of merits (FOMs) such as drain current (I_ds), transconductance (g_m), output resistance (R_o), intrinsic gain (g_mR_o), unity-gain cutoff frequency (f_T), transit frequency of maximum available power gain (f_MAX), transport delay (τ_m), intrinsic resistance (R_gd) and intrinsic capacitances (C_gs, C_gd).     

High-performance diketopyrrolopyrrole-based organic field-effect transistors for flexible gas sensors

We demonstrate high-performance flexible polymer OFETs with P-29-DPP-SVS in various geometries. The mobilities of TG/BC OFETs are approximately 3.48 ± 0.93 cm²/V s on a glass substrate and 2.98 ± 0.19 cm²/V s on a PEN substrate. The flexible P-29-DPP-SVS OFETs exhibit excellent ambient and mechanical stabilities under a continuous bending stress of 1200 times at an R = 8.3 mm. In particular, the variation of μ_FET, V_Th and leakage current was very negligible (below 10%) after continuous bending stress. The BG/TC P-29-DPP-SVS OFETs on a PEN substrate applies to flexible NH₃ gas sensors. As the concentration of NH₃ increased, the channel resistance of P-29-DPP-SVS OFETs increased approximately 100 times from ∼10⁷ to ∼10⁹ Ω at V_SD = −5 V and V_GS = −5 V.