Resonant amplifier-based sub-harmonic mixer for zero-IF transceiver applications

This paper describes a novel low voltage low power resonant amplifier-based sub-harmonic mixer using current-reuse-bleeding technique for zero-IF transceiver systems applications. The novel resonant amplifier-based sub-harmonic balun is designed and used in the mixer, which can double the frequency of the local oscillation (LO) signal. Moreover, the sub-harmonic balun can provide a pair of double frequency LO signals, unlike the conversional mixers, the novel sub-harmonic requires only one low power LO input. The proposed mixer delivers a remarkable conversion gain of 14.5 dB with local oscillator (LO) power of −2 dBm, and its power consumption is 0.65 mW with 0.8 V supply voltage. The input-referred third-order intercept point (IIP3) of the mixer is 1 dBm, and the chip area is only 0.52 mm².     

A 0.1–1 GHz low power RF receiver front-end with noise cancellation technique for WSN applications

A low power 0.1–1 GHz RF receiver front-end composed of noise-cancelling trans-conductor stage and I/Q switch stage was presented in this paper. The RF receiver front-end chip was fabricated in 0.18 µm RF CMOS. Measurement results show the receiver front-end has a conversion gain of 28.1 dB at high gain mode, and the single-sideband (SSB) noise figure is 6.2 dB. In the low gain mode, the conversion gain of the receiver front-end is 15.5 dB and the IP1dB is −12 dBm. In this design, low power consumption and low cost is achieved by current-reuse and inductor-less topology. The receiver front-end consumes only 5.2 mW from a 1.8 V DC supply and the chip size of the core circuit is 0.12 mm².     

Design of ultra-low voltage integrated CMOS based LNA and mixer for ZigBee application

This work describes the design and implementation of an ultra-low voltage, ultra-low power fully differential low noise amplifier (LNA) integrated with a down-conversion mixer for 2.4 GHz ZigBee application. An inductive-degenerated cascoded LNA is adapted and integrated with a double-balanced mixer which is targeted for low-power application. The proposed design has been extracted and simulated in a 0.13 μm standard CMOS technology. With a power consumption of 905 μW at a voltage headroom of 0.5 V, the proposed LNA-mixer integration reaches out to an integrated noise figure (NF) of 7.2 dB, a gain of 22.3 dB, 1 dB compression point (P1 dB) of −22.3 dBm and input-referred third-order intercept point (IIP3) of −10.8 dBm.     

An Inductor-less Sub-mW Low Noise Amplifier for Wireless Sensor Network Applications

This paper presents a Sub-mW differential Common-Gate Low Noise Amplifier (CGLNA) for ZigBee standard. The circuit takes the advantage of shunt feedback and Dual Capacitive Cross Coupling (DCCC) to reduce power consumption and the bandwidth extension capacitors to support 2.4 GHz ISM band. An amplifier employing these techniques has been designed and simulated in 0.18 µm TSMC CMOS technology. The Simulation results show a gain of 18.2 dB, an IIP3 of −4.32 dBm and a noise figure of 3.38 dB at 2.4 GHz. The proposed LNA consumes only 967 µW from a 1-V supply.     

A wideband RF receiver with extended statistical element selection based harmonic rejection calibration

In this paper we present a wideband harmonic rejection (HR) RF receiver design. Both gain mismatch and phase mismatch of the HR mixer have been calibrated using a design and calibration method called extended statistical element selection to achieve best-in-class HR ratio (HRR) performance. The achieved concurrent 3rd order HRR and 5th order HRR are greater than 80 dB and 70 dB, respectively, after calibration. The even order HRR is also calibrated to greater than 80 dB. A single calibration performed at 750 MHz was further observed to be effective over more than two octaves of bandwidth with greater than 70 dB HRR. The receiver was manufactured in 65 nm CMOS technology. Input RF frequency range was 0.15–1 GHz and the receiver consumes 64 mW at 1 GHz. Noise figure is 3.2 dB and out-of-band IIP3 is −7 dBm at a total gain of 48 dB.     

A linear ultra wide band low noise amplifier using pre-distortion technique

This paper presents an Ultra Wide-Band (UWB) high linear low noise amplifier. The linearity of Common Gate (CG) structure is improved based on pre-distortion technique. An auxiliary transistor is used at the input to sink the nonlinear terms of source current, resulting linearity improvement. Furthermore, an inductor is used in the gate of the main amplifying transistor, which efficiently improves gain, input matching and noise performance at higher frequencies. Detailed mathematical analysis show the effectiveness of both linearity improvement and bandwidth extension techniques. Post-layout simulation results of the proposed LNA in TSMC 0.18 µm RF-CMOS process show a gain of 13.7 dB with −3 dB bandwidth of 0.8–10.4 GHz and minimum noise figure (NF) of 3 dB. Input Third Intercept Point (IIP3) of 10.3–13 dBm is achieved which shows 8 dB improvement compared to conventional common gate structure. The core circuit occupies an area of 0.19 mm² including bond pads, while consuming 4 mA from a 1.8-V supply.     

A RF front-end for DVB-SH based on current conveyors

Inductors are used extensively in Radio Frequency Integrated Circuits to design matching networks, load circuits of voltage controlled oscillators, filters, mixers and many other RF circuits. However, on-chip inductors are large and cannot be ported easily from one process to the next. Due to modern CMOS scaling, inductorless RF design is rapidly becoming possible. In this paper a new methodology for designing the RF frontend necessary for the DVB-SH in a 90 nm CMOS technology based on the use current conveyors (CC) is presented. The RF frontend scheme is composed of a second generation CC (CCII) LNA with asymmetric input and output, an asymmetric to differential converter, and a passive differential mixer followed by two CCII transimpedance amplifiers to obtain a high gain conversion. Measurements show a conversion gain of 20.8 dB, a 14.5 dB noise figure, an input return loss (S11) of −14.3 dB and an output compression point of −3.9 dBm. This combination draws 28.4 mW from a ±1.2 V supply.     

Design of an active CMOS subharmonic mixer with enhanced transconductance

This paper presents a wideband Gilbert subharmonic mixer (SHM) that partly overcomes the fundamental trade-off between radio frequency (RF) and intermediate frequency (IF) currents. Compared to the conventional SHM, the proposed SHM features large gain, low noise figure (NF) and moderate linearity over a wide bandwidth by concurrent usage of regulated-cascode RF-stage and inductive connection between RF and LO stages. Numerical analyses along with circuit-level simulations are given to evaluate the performance of the proposed mixer and facilitate its optimum design. Simulations using a 0.18 μm RF-CMOS process demonstrate that the proposed mixer, at a fixed IF of 100 MHz, exhibits more than 5 dB and 2 dB improvements in conversion gain (CG) and NF, respectively.     

A low-voltage low-power CMOS transmitter front-end using current mode approach for 2.4 GHz wireless communications

This paper presents a low-voltage low-power transmitter front-end using current mode approach for 2.4 GHz wireless communication applications, which is fabricated in a chartered 0.18 μm CMOS technology. The direct up-conversion is implemented with a current mode mixer employing a novel input driver stage, which can significantly improve the linearity and consume a small amount of DC current. The driver amplifier utilizes a transimpedance amplifier as the first stage and employs an inter-stage capacitive cross-coupling technique, which enhances the power conversion gain as well as high linearity. The measured results show that at 2.4 GHz, the transmitter front-end provides 15.5 dB of power conversion gain, output P?1 dB of 3 dBm, and the output-referred third-order intercept point (OIP3) of 13.8 dBm, while drawing only 6 mA from the transmitter front-end under a supply voltage of 1.2 V. The chip area including the testing pads is only 0.9 mm×1.1 mm.     

3.1–10.6 GHz ultra-wideband LNA design using dual-resonant broadband matching technique

This paper presents an ultra-wideband low noise amplifier design using the dual-resonant broadband matching technique. The proposed LNA achieves a 10.2 dB gain with ±0.9 dB gain flatness over a frequency range of 3.1–10.6 GHz and a ?3-dB bandwidth of 2.4–11.6 GHz. The measured noise figure ranges from 3.2 to 4.7 dB over 3.1–10.6 GHz. At 6.5 GHz, the measured IIP3 and input-referred P1dB are +6 dBm and ?5 dBm, respectively. The proposed LNA occupies an active chip area of 0.56 mm² in a TSMC 0.18 μm RF-CMOS process and consumes 16 mW from a 1.8 V supply.     

A 77 GHz SiGe sub-harmonic balanced mixer

A novel SiGe 77 GHz sub-harmonic balanced mixer is presented with a goal to push the technology to its limit [SiGe2-RF transistor (f/sub T/=80 GHz)]. This new topology uses a compact input network not only to achieve high isolation between the LO and RF ports, but also to result in excellent 2LO-RF isolation. The measured results demonstrate a conversion gain of 0.7 dB at 77 GHz with an LO power of 10 dBm at 38 GHz, LO-RF isolation better than 30 dB, 2LO-RF isolation of 25 dB, and a P/sub 1dB/ of -8 dBm. The mixer core consumes 4.4 mA at 5 V. The circuit demonstrates that SiGe sub-harmonic mixers have comparable performance with GaAs designs, at a fraction of the cost.     

A hybrid ring coupler quasi-optical antenna-mixer

This paper proposes a hybrid ring coupler quasi-optical antenna-mixer for mitigating local oscillator retransmission. By demonstrating at K-band, the antenna element consists of back-to-back aperture coupled inverted square patch antenna to couple the RF signal at 18.8 GHz to the sigma port of a hybrid ring mixer while the LO signal at 17.5 GHz is coupled to the delta port. The HSCH-9101 Schottky diodes are used to transform the RF signal to the intermediate frequency signal at 1.3 GHz. The results show that the RF/LO isolation is better than 29 dB at 18.19 GHz, and the isotropic conversion loss of the down converted signal is better than 16 dB at 19.25 GHz. The application of the interest is an inverse measurement technique for dielectric property determination.     

An inductorless wideband common-gate LNA with dual capacitor cross-coupled feedback and negative impedance techniques

A wideband common-gate (CG) low-noise amplifier (LNA) with dual capacitor cross-coupled (CCC) feedback and negative impedance techniques is presented for multimode multiband wireless communication applications. Double CCC technique boosts the input transconductance of the LNA, and low power consumption is obtained by using current-reuse technique. Negative impedance technique is employed to alleviate the correlation between the transconductance of the matching transistors and input impedance. Meanwhile, it also allows us to achieve a lower noise figure (NF). Moreover, current bleeding technique is adopted to allow the choice of a larger load resistor without sacrificing the voltage headroom. The proposed architecture achieves low noise, low power and high gain simultaneously without the use of bulky inductors. Simulation results of a 0.18-μm CMOS implementation show that the proposed LNA provides a maximum voltage gain of 25.02 dB and a minimum NF of 2.37 dB from 0.1 to 2.25 GHz. The input-referred third-order intercept point (IIP3) and input 1-dB compression point (IP_1dB) are better than –7.8 dBm and –19.2 dBm, respectively, across the operating bandwidth. The circuit dissipates 3.24 mW from 1.8 V DC supply with an active area of 0.03 mm².     

High LO-RF isolation of zero-IF mixer in 0.18 μm CMOS technology

In this study, we introduce a zero-IF sub-harmonic mixer with high isolation in the 5 GHz band using 0.18 μm CMOS technology. Placing an LC-Tank between the class AB stage and the mixer core improves the isolation between the LO to RF at low supply voltage. The measured isolation is 48 dB between the LO and RF ports, and the 9.5 dB conversion gain is achieved with a supply voltage of 7 mA at 2.5 V. In order to alleviate the degradation of linearity due to the high conversion gain, we adopt the class AB stage as RF input stage. The measured IIP₃ is −7.5 dBm. This work was supported by National Science Council of Taiwan, ROC under contract no. NSC94-2220-E-005-002.     

10-GHz Highly Symmetrical Sub-Harmonic Gilbert Mixer Using GaInP/GaAs HBT Technology

A 10-GHz sub-harmonic Gilbert mixer is demonstrated using GaInP/GaAs hetero-junction bipolar transistor technology. The local oscillator (LO) signal time-delay path in the sub-harmonic LO stage is compensated using the fully symmetrical stacked-LO doubler; therefore, the balance of the sub-harmonic LO stage, the radio frequency to intermediate frequency isolation, and IIP₂ are improved. The demonstrated 10-GHz sub-harmonic mixer achieves 10 dB conversion gain, IP_1dB of -12 dBm, IIP₃ of 2 dBm and IIP₂ of 33 dBm     

High performance quadruple sub-harmonic mixer for millimeter-wave applications

In this paper, we present high performance quadruple sub-harmonic mixers for millimeter-wave applications. The sub-harmonic mixer was designed by using 0.1 μm GaAs PHEMT's and the coplanar wave-guide library. We show the low conversion loss of 5.8 dB at a local oscillator (LO) power of 13 dBm from the fabricated sub-harmonic mixers. The V-band sub-harmonic mixer also ensure a high degree of isolation showing −75.0 dB in the LO-to-IF and −48.1 dB in the LO-to-RF at a frequency of 14.5 GHz, respectively. The fabricated V-band sub-harmonic mixer has a lower conversion loss characteristics compared with ever reported mixers for millimeter frequencies.     

Low power high gain CMOS LNA based on inverter cell and self-body bias for UWB receivers

A low-power low-noise amplifier (LNA) utilized a resistive inverter configuration feedback amplifier to achieve the broadband input matching purposes. To achieve low power consumption and high gain, the proposed LNA utilizes a current-reused technique and a splitting-load inductive peaking technique of a resistive-feedback inverter for input matching. Two wideband LNAs are implemented by TSMC 0.18 μm CMOS technology. The first LNA operates at 2–6 GHz. The minimum noise figure is 3.6 dB. The amplifier provides a maximum gain (S₂₁) of 18.5 dB while drawing 10.3 mW from a 1.5-V supply. This chip area is 1.028×0.921 mm². The second LNA operates at 3.1–10.6 GHz. By using self-forward body bias, it can reduce supply voltage as well as save bias current. The minimum noise figure is 4.8 dB. The amplifier provides a maximum gain (S₂₁) of 17.8 dB while drawing 9.67 mW from a 1.2-V supply. This chip area is 1.274×0.771 mm².     

A resistive-feedback LNA in 65 nm CMOS with a gate inductor for bandwidth extension

In order to get a wideband and flat gain, a resistive-feedback LNA using a gate inductor to extend bandwidth is proposed in this paper. This LNA is based on an improved resistive-feedback topology with a source follower feedback to match input. A relative small inductor is connected in series to transistor׳s gate, which boosts transistor׳s effective transconductance, compensates gain loss and then leads the proposed LNA with a flat gain and wider bandwidth. Moreover, the LNA׳s noise is partially inhibited by the gate inductor, especially at high frequency. Realized in standard 65-nm CMOS process, this LNA dissipates 12 mW from a 1.5-V supply while its core area is 0.076 mm². Across 0.4–10.6 GHz band, the proposed LNA provides 9.5±0.9 dB power gain (S₂₁), better than −11-dB input matching, 3.5-dB minimum noise figure, and higher than −17.2-dBm P_1 dB.     

Noise and mixing properties of high-Tc Josephson junctions at W-band frequencies

We report on the noise and Josephson mixing properties of high-T_c superconductor (HTS) Josephson junctions. Direct radiation measurements and heterodyne mixing experiments in the frequency range 45–141 GHz have been performed by using YBa₂Cu₃O_7−x (YBCO) step-edge junctions (SEJ) on LaAlO₃ and MgO and bicrystal junctions (BCJ) on MgO substrates. Junctions with current voltage characteristics (CVC) close to predictions of the resistivity shunted junction (RSJ) model were mounted into a high sensitive radiometer system. From linewidth measurements we calculated an effective noise temperature of our junctions. In heterodyne mixing experiments we obtained conversion efficiencies around −14 dB in the 11 GHz intermediate frequency (IF) band under the radiation of two monochromatic signals. In the fundamental mixing regime we observed response at IF at working temperatures up to 72 K. The measured receiver and mixer noise temperature of the Josephson mixer at 94 GHz local oscillator (LO) frequency, an IF of 1.4 GHz and at a working temperature of 10 K was 4700 and 3400 K, respectively.     

Heuristic receiver for implantable UWB applications

High data rate implantable wireless systems come with many challenges, chief among them being low power operation and high linearity. A low noise amplifier (LNA) designed for this application must include high gain, low noise figure (NF) and better linearity at low power consumption within the required frequency band. The down converter also requires a passive mixer to achieve low power and better linearity. In this paper, design is based on an Impulse Response (IR) Ultra-wideband (UWB) receiver operating at (3.1–5) GHz implemented in 0.25 μm CMOS Silicon on Sapphire (SOS). This paper reports the design and measurement of a UWB receiver with a designed and measured linearity of 17 dBm, a gain of 30.5 dB and a minimum NF of 4.5 dB, which make it suitable for implantable radio applications.