Sn whisker evaluations in 3D microbumped structures

Sn whiskering remains a reliability concern in electronic applications. Despite extensive research on growth rates and mitigation strategies, no predictive theory is in place. Literature data are available for Cu/Sn-based films and coatings as well as for board-level and flip-chip solder bumps but data are scarce for scaled-down solder volumes and for higher intermetallic-to-solder ratios. The current work investigates whiskers in “isolated geometries” for 3D solder-capped Cu microbumps with >2 orders of magnitude smaller solder volumes compared to state-of-the-art. To the best of the authors’ knowledge, this is the first time Sn whisker growth is reported in isolated solder volumes (e.g. <8 μm-side cube). Whiskers propensity was evaluated using JEDEC industrial specifications. The tested structures were: 5/3.5 μm-thick Cu/Sn films and 15 μm-diameter electroplated solder capping (Sn, SnAg, SnCu) on Cu microbumps (as-plated vs. reflowed). Selected Sn whiskers and “whisker-like” features were analysed and identified experimentally with SEM, EDX and FIB. In the absence of a predictive model, first-order and “what if” calculations based on IMC molar volume and oxide cracking hypotheses were carried out. This approach quantifies “figures of merit” for Sn whisker propensity with (1) different bump-limiting metallization (BLM) cases e.g. Cu, Ni, Co and (2) further microbump scaling. Future research recommendations are outlined to mitigate manufacturing risks by controlling “sit time” between bumping and stacking.     

Comparative studies on microelectronic reliability issue of Sn whisker growth in Sn-0.3Ag-0.7Cu-1Pr solder under different environments

In this study, comparative studies on Sn whisker growth in Sn-0.3Ag-0.7Cu-1Pr solder under different environments were conducted to investigate factors like ambient temperature, oxygen level, and 3.5 wt% NaCl solution on whisker growth. The experimental results revealed that ambient temperature and oxygen level are two important factors that could determine the oxidation rate of PrSn₃ phase, thus indirectly affecting the growth rate of Sn whiskers. In addition, mechanisms of whisker growth under these three environments were established from the perspective of atom diffusion based on the “compressive stress-induced” theory. Although whiskers under different environments were all squeezed out from Pr oxides (hydroxides), the forms of their driving forces were different. For whiskers squeezed out in air whether at room temperature or 150 °C, the driving force is the compressive stress produced by lattice expansion due to the oxidation of PrSn₃ phase. The representative example was whiskers' growth at 150 °C, which could be simplified as three stages: (1) squeezing out, (2) cracking and (3) bursting out. For whisker growth in 3.5 wt% NaCl solution, the driving force for much fewer whiskers' growth was proposed to come from lateral stress provided by interfacial IMC layer growth. Moreover, Sn nanoparticles and their agglomerations were also found to form under the driving force of the potential difference between Sn atoms and Sn crystals. Their morphologies could also be affected by factors of ambient temperature, oxygen level and Cl⁻ ions in corrosive liquid.     

Growth competition between layer-type and porous-type Cu3Sn in microbumps

Experimental study of growth competition between the co-existing layer-type and porous-type Cu₃Sn in solder microbumps of Cu/SnAg/Cu is reported. The thickness of the SnAg solder is about 14 μm and the Cu column on both sides is 20 μm. Upon wetting-reflow, the solder is reacted completely to form CuSn intermetallic compounds in a multi-layered structure of Cu/Cu₃Sn/Cu₆Sn₅/Cu₃Sn/Cu. Upon further annealing at 220 °C and 260 °C, we obtain Cu/Cu₃Sn/porous Cu₃Sn/Cu₃Sn/Cu, in which both types of Cu₃Sn co-exist and form an interface. In the layer-type growth, we assume Cu to be the dominant diffusing species, coming from the Cu column. The Cu reacts with Cu₆Sn₅ to grow the Cu₃Sn layer. In the porous-type growth, we assume Sn to be the dominant diffusing species, coming from the depletion of Sn in Cu₆Sn₅. The depleted Cu₆Sn₅ transforms to the porous-type Cu₃Sn. At the same time, the Sn diffuses to the side-wall of Cu column to form a coating of Cu₃Sn. Experimental observations of 3-dimensional distribution of voids in the porous-type Cu₃Sn are performed by synchrotron radiation tomography; the voids are interconnected for the out-diffusion of Sn. The competing growth between the layer-type and the porous-type Cu₃Sn is analyzed.     

Non-conductive film with Zn-nanoparticles (Zn-NCF) for 40 μm pitch Cu-pillar/Sn–Ag bump interconnection

Non-conductive film with Zn nano-particles (Zn-NCF) is an effective solution for fine-pitch Cu-pillar/Sn–Ag bump interconnection in terms of manufacturing process and interfacial reliability. In this study, NCFs with Zn nano-particles of different acidity, viscosity, and curing speed were formulated and diffused Zn contents in the Cu pillar/Sn–Ag bumps were measured after 3D TSV chip-stack bonding. Amount of Zn diffusion into the Cu pillar/Sn–Ag bumps increased as the acidity of resin increased, as the viscosity of resin decreased, as the curing speed of resin decreased, and as the bonding temperature increased. Diffusion of Zn nano-particles into the Cu pillar/Sn–Ag bumps are maximized when the resin viscosity became lowered and the solder oxide layer was removed. To analyze the effects of Zn-NCF on IMC reduction, IMC height depending on aging time was measured and corresponding activation energies for IMC growth were calculated. For the evaluation of joint reliabilities, test vehicles were bonded using NCFs with 0 wt%, 1 wt%, 5 wt%, and 10 wt% of Zn nano-particles and aged at 150 °C up to 500 h. NCF with 10 wt% Zn nano-particle showed remarkable suppression in Cu₆Sn₅ and (Cu,Ni)₆Sn₅ IMC compared to NCFs with 0 wt%, 1 wt%, and 5 wt% of Zn nano-particles. However, in terms of Cu₃Sn IMC suppression, which is the most critical goal of this experiment NCFs with 1 wt%, 5 wt%, and 10 wt% showed an equal amount of IMC suppression. As a result, it was successfully demonstrated that the suppression of Cu–Sn IMCs was achieved by the addition of Zn nano-particles in the NCFs resulting an enhanced reliability performance in the Cu/Sn–Ag bumps bonding in 3D TSV interconnection.     

Effect of Electromigration and Isothermal Aging on the Formation of Metal Whiskers and Hillocks in Eutectic Sn-Bi Solder Joints and Reaction Films

Numerous electronic system failures have been attributed to short circuits caused by metal whiskers that bridged closely spaced circuit elements when they were maintained in a high-current-density environment. Typically, in single-phase interconnect materials, atoms are driven from the cathode to the anode and a compressive stress can build up at the anode end of the stripe, which can induce the formation of whiskers and hillocks. However, the electronic solders used in interconnects are multiphase materials where primary and secondary diffusion atoms/ions exist. In order to accelerate the growth of whiskers and hillocks, a high current density (10⁴ A/cm²) combined with high ambient temperatures (80°C) was applied to eutectic Sn-Bi solder joints. Metal whiskers and hillocks were observed on the overflowed solder film above the Cu substrate. However, in the absence of the electric field, metal whiskers and hillocks could also be squeezed out from the solder reaction films after several days of isothermal aging (125°C), demonstrating that the chemical reaction between Sn atoms and Cu atoms can provide the driving force for the formation and growth of metal whiskers and hillocks.     

Investigation of soldering process and interfacial microstructure evolution for the formation of full Cu3Sn joints in electronic packaging

Within electronic products, solder joints with common interfacial structure of Cu/IMCs/Sn-based solders/IMCs/Cu cannot be used under high temperature for relatively low melting points of Sn-based solders (200–300 °C). However, there is a trend for solder joints to service under high temperature because of the objective for achieving multi-functionality of electronic products.With the purpose of ensuring that solder joints can service under high temperature, full Cu₃Sn solder joints with the interfacial structure of Cu/Cu₃Sn/Cu can be a substitute due to the high melting point of Cu₃Sn (676 °C). In this investigation, soldering process parameters were optimized systematically in order to obtain such joints. Further, interfacial microstructure evolution during soldering was analyzed. The soldering temperature of 260 °C, the soldering pressure of 1 N and the soldering time of 5 h were found to be the optimal parameter combination. During soldering of 260 °C and 1 N, the Cu₆Sn₅ precipitated first in a planar shape at Cu-Sn interfaces, which was followed by the appearance of planar Cu₃Sn between Cu and Cu₆Sn₅. Then, the Cu₆Sn₅ at opposite sides continued to grow with a transition from a planar shape to a scallop-like shape until residual Sn was consumed totally. Meanwhile, the Cu₃Sn grew with a round-trip shift from a planar shape to a wave-like shape until the full Cu₃Sn solder joint was eventually formed at 5 h. The detailed reasons for the shape transformation in both Cu₆Sn₅ and Cu₃Sn during soldering were given. Afterwards, a microstructure evolution model for Cu-Sn-Cu sandwich structure during soldering was proposed. Besides, it was found that no void appeared in the interfacial region during the entire soldering process, and a discuss about what led to the formation of void-free joints was conducted.     

Preparation of in-plane textured buffer layers for YBa2Cu3Oy film growth by modified bias sputtering

A modified bias sputtering technique has been proposed to grow in-plane textured yttria-stabilized zirconia buffer layers on polycrystalline metallic substrates for deposition of YBa₂Cu₃O_y films. The principle of developing an in-plane texturing by this technique is basically the same as that of ion beam assisted deposition; an in-plane texturing occurs by off-normal ion beam bombardment because of the higher sputtering yields of all orientations other than the channelling direction. In our process, however, a flux of energetic particles impinging on the growing film is generated using specially devised negatively biased electrodes installed in a magnetron sputtering system instead of a separate ion-source in IBAD. So far an X-ray phi-scan width of 18° was attained for YSZ films on Hastelloy tapes. Epitaxial YBCO films grown on these buffer layers using pulsed laser deposition showed the J_c’s exceeding 10⁵ A cm⁻² (77 K, 0 T). In this paper, we present variation of the bias sputtering technique also used to obtain the textured films on large area substrates. Although the proposed process offers a very convenient method to grow textured films, more efforts must be made to increase growth rates of the films (currently ∽0.1 nm s⁻¹) for large-scale applications of YBCO films.     

Formation of low-resistance and transparent indium tin oxide ohmic contact for high-brightness GaN-based light-emitting diodes using a Sn–Ag interlayer

We report on the formation of low-resistance and highly transparent indium tin oxide (ITO) ohmic contacts to p-GaN using a Sn–Ag alloy interlayer. Although the as-deposited Sn–Ag(6 nm)/ITO(200 nm) contacts show non-ohmic behaviors, the scheme becomes ohmic with specific contact resistance of 4.72×10⁻⁴ Ω cm² and produce transmittance of ∼91% at wavelength of 460 nm when annealed at 530 °C. Blue light-emitting diodes (LEDs) fabricated with the Sn–Ag/ITO contacts give forward-bias voltage of 3.31 V at injection current of 20 mA. LEDs with the Sn–Ag/ITO contacts show the improvement of the output power by 62% (at 20 mA) compared with LEDs with Ni/Au contacts.     

In Situ Measurement of Stress and Whisker/Hillock Density During Thermal Cycling of Sn Layers

Compressive stress is believed to be the primary driving force that makes Sn whiskers/hillocks grow, but the mechanisms that create the stress (e.g., intermetallic compound growth) are difficult to control. As an alternative, the thermal expansion mismatch between the Sn layer and the substrate can be used to induce stress in a controlled way via heating and cooling. In this work, we describe real-time experiments which quantify the whiskering behavior and stress evolution during cyclic heating. The density of whiskers/hillocks is measured with an optical microscope, while the stress is measured simultaneously with a wafer-curvature-based multi-beam optical stress sensor. Results from three thermal cycles are described in which the samples are heated from room temperature to 65 °C at rates of 10, 30, and 240 °C/h. In each case, we find that the whisker/hillock formation is the primary source of stress relaxation. At fast heating rates, the relaxation is proportional to the number of hillocks, indicating that the stress is relaxed by the nucleation of many small surface features. At slower heating rates, the whisker/hillock density is lower, and continual growth of the features is suggested after nucleation. Long whiskers are found to be more likely to form in the slow heating cycle.     

Whisker mitigation measures for Sn-plated Cu for different stress tests

The effectiveness of the widely-used whisker mitigation measures for Sn-plated Cu base material (annealing at 150 °C for 1 h or a Ni interlayer) were investigated after temperature cycling and after storage at room temperature. It was found that these measures prevent whisker growth during isothermal storage, but not during temperature cycling. These mitigation measures do apparently not reduce the compressive stress that builds up during temperature cycling due to different coefficients of thermal expansion of Sn and Cu. A change of the Sn microstructure to globular grains is proposed and investigated as potential whisker mitigation measure for temperature cycling.     

Development of chip-on-flex bonding using Sn-based bumps and non-conductive adhesive

We developed a reliable and low cost chip-on-flex (COF) bonding technique using Sn-based bumps and a non-conductive adhesive (NCA). Two types of bump materials were used for the bonding process: Sn bumps and Sn–Ag bumps. The bonding process was performed at 180 °C for 10 s using a thermo-compression bonder after dispensing the NCA. Sn-based bumps were easily deformed to contact Cu pads during the bonding process. A thin layer of Cu₆Sn₅ intermetallic compound was observed at the interface between Sn-based bumps and Cu pads. After bonding, electrical measurements showed that all COF joints had very low contact resistance, and there were no failed joints. To evaluate the reliability of COF joints, high temperature storage tests (150 °C, 1000 h), thermal cycling tests (−25 °C/+125 °C, 1000 cycles) and temperature and humidity tests (85 °C/85% RH, 1000 h) were performed. Although contact resistance was slightly increased after the reliability test, all COF joints passed failure criteria. Therefore, the metallurgical bond resulted in good contact and improved the reliability of the joints.     

Planar copper-tin inter-metallic film formation on strained substrates

This paper presents the results of four-point bending tests investigating the effects of substrate strain on the growth ɛ of interfacial Cu–Sn inter-metallic compounds (IMCs). Test specimens were cut into strips, 27.5 mm in length and 5 mm in width, from 4 in. double polished silicon wafers. A very thin adhesion layer (Ta) was deposited on the silicon substrate by sputtering followed by a 10 μm thick layer of copper using electroplating. Finally, a 30 μm tin layer was deposited over the copper film also by electroplating. Samples were then placed in a furnace at 200 °C to undergo bending in order to introduce in-plane strain under tension or compression. Control samples also underwent the same treatment without applied strain. Our aim was to investigate the influence of substrate strain and aging time on the formation of IMCs (1.54 × 10⁻⁴, 2.3 × 10⁻⁴ and 3.46 × 10⁻⁴). The thickness and separation of each phase (Cu₃Sn) and η (Cu₆Sn₅) are clearly visible in scanning electron microscope images. Compressive strain and tensile strain both increased the thickness of the IMC layer during the aging process; however, the effects of compressive strain were more pronounced than those of tensile strain. We hypothesize that the increase in IMC thickness is related to the strain enhanced out-diffusion of Cu towards the solder as well as strain in the underlying lattice at the diffusion interface.     

Band gap engineered resistor for mitigating linear energy transfer sensitivities in scaled submiron CMOS technology SRAM cells

Use of cross-coupling latch resistors is a prime method of mitigating single event upsets (SEU). Scaling has dramatically reduced ability of using this technique because of the large area needed as well as high temperature coefficient of resistance (TCR) of lightly doped polysilicon resistors. We present results of a study of the electrical properties of Al_1?xIn_xN films resistor which offers distinct advantage over polysilicon resistors. The films were grown on silicon nitride by magnetron sputter deposition at room temperature. Sheet resistance in the range of 8–10 kΩ/□ was reproducibly grown. The resistor film is thermally stable with TCR of less than minus 0.09%/°C for temperature range of minus 55 °C to +125 °C.     

Acceleration of the growth of Cu3Sn voids in solder joints

Soldering to Cu surface finishes usually leads to the formation of a bi-layer intermetallic structure, Cu₃Sn/Cu₆Sn₅, that provides a more robust bond than common alternatives. Occasionally, and so far unpredictably, voids may however grow within the Cu₃Sn over time and allow for premature failure of microelectronics products in service. A quantitative assessment of the reliability risk of voids observed after accelerated aging requires the knowledge of the variation of void growth with temperature and time. It is argued that in the case of realistic solder joints diffusion controlled void growth kinetics are unlikely to follow simple Arrhenius and parabolic dependencies, respectively. Nevertheless, three very different sets of samples were all shown to exhibit void growth that could be well approximated by a parabolic time dependence and an effective activation energy of 0.65–0.80 eV.     

Low cycle fatigue performance of ball grid array structure Cu/Sn–3.0Ag–0.5Cu/Cu solder joints

Low cycle fatigue performance of ball grid array (BGA) structure Cu/Sn–3.0Ag–0.5Cu/Cu joints with different standoff heights (h, varying from 100 to 500 μm) and two pad diameters (d, d = 320 and 480 μm) under displacement-controlled cyclic loading was studied by experimental method and finite element (FE) simulation. A prediction method based on the plastic strain energy density and continuum damage mechanics (CDM) framework was proposed to evaluate the initiation and propagation of fatigue crack in solder joints. The results show that fatigue failure of solder joints is a process of damage accumulation and the plastic strain energy density performs a power function correlation with the cycle numbers of crack initiation and propagation. Crack propagation rate is affected by the stress triaxiality, which is dependent on the loading mode and increases dramatically with decreasing h under tensile loading, while the change of standoff height has very limited influence on the stress triaxiality under shear loading mode. Moreover, crack growth correlation constants identified in Cu/Sn–3.0Ag–0.5Cu/Cu joints with a specific geometry (h = 100 μm and d = 480 μm) can be well used to predict the fatigue life of BGA joints with other geometries. Furthermore, the results have also shown that the fatigue life of solder joints increases with decreasing the geometric ratio of h/d under the same nominal shear strain amplitude, while it drops with decreasing h/d under the same shear displacement amplitude in cyclic loading. When the geometric ratio (i.e., h/d ratio) is unchanged, the miniaturization of BGA joints brings about a decrease in fatigue life of the joints.     

An area efficient and high throughput multi-rate quasi-cyclic LDPC decoder for IEEE 802.11n applications

In this paper, an area efficient and high throughput multi-rate quasi-cyclic low-density parity-check (QC-LDPC) decoder for IEEE 802.11n applications is proposed. An overlapped message passing scheme and the non-uniform quantization scheme are incorporated to reduce the overall area and power of the proposed QC-LDPC decoder. In order to enhance the decoding throughput and reduce the size of memories storing soft messages, an improved early termination (ET) scheme and base matrix reordering technique is employed. These techniques significantly reduce the total number of decoding iterations and memory accessing conflicts without mitigating the decoding performance. Equipped with these techniques an area efficient and high throughput multi-rate QC-LDPC decoder is designed, simulated and implemented with Xilinx Virtex6 (XC6VLX760-2FF1760) for an irregular LDPC code of length 1944 and code rates (1/2–5/6) specified in IEEE 802.11n standard. With a maximum clock frequency of 574.136–587.458 MHz the proposed QC-LDPC decoder can achieve throughput in the range of 1.27–2.17 Gb/s for 10 decoding iterations. Furthermore, by using Cadence RTL compiler with UMC 130 nm VLSI technology, the core area of the proposed QC-LDPC decoder is found to be 1.42 mm² with a power dissipation in the range of 101.25–140.42 mW at 1.2 V supply voltage.     

Sn addition on the tensile properties of high temperature Zn–4Al–3Mg solder alloys

The Zn–4Al–3Mg based solder alloy is a promising candidate to replace the conventional Pb–5Sn alloy in high-temperature electronic packaging. In this study, the tensile properties of Zn–4Al–3Mg–xSn alloys (x = 0, 6.8 and 13.2 wt.%) at high temperatures (e.g., 100 °C, and 200 °C) were investigated. It was found that the uniaxial tensile strength (UTS) of Zn–4Al–3Mg–xSn solder alloys all decrease monotonously with the increment of temperature. The elongation ratio at 100 °C is superior to that at room temperature whereas follows a significant drop at 200 °C. The microstructure observations show that a typical brittle fracture of Zn–4Al–3Mg alloy occurs at room temperature and 200 °C under normal tension, whereas a ductile fracture is found at 100 °C. The 6.8 wt.% Sn addition in Zn–4Al–3Mg alloy causes a dramatic decrease of yield strength, and a slight deterioration of the ductility.     

Direct MBE growth of GaN on GaAs substrates for integrated short wavelength emitters

The growth and material properties of GaN heteroepitaxial layers on vicinal (1 0 0) and exact (1 1 1)B substrates have been investigated, using molecular beam epitaxy (MBE) with N₂ RF-plasma source. We examined the approach to grow GaN directly on the oxide desorbed GaAs, without the incidence of an As beam during oxide desorption or the following stages of growth. Perfect smooth surfaces were obtained on (1 1 1)B GaAs but excellent luminescence properties were observed on vicinal (1 0 0) GaAs. Four growth temperatures (T_G) were compared for the (1 0 0) orientation and a monotonic increase of photoluminescence intensity with increasing T_G, in the range of 570–680°C, was observed. The best surface morphology of less than 10 nm rms roughness was also determined, by atomic force microscopy, for the maximum (680°C) temperature. The layers exhibited up to 10¹⁷ cm⁻³ electron concentration and it could be compensated by Mg impurities. Metallizations of Pt and Pd gave ohmic contacts on GaN/GaAs (1 0 0) but a Schottky diode contact was achieved by Ir metallization. The obtained material properties are probably sufficient for realizing efficient GaN light emitters on (1 0 0) GaAs substrates.     

Electro- and thermomigration induced Cu3Sn and Cu6Sn5 formation in SnAg3.0Cu0.5 bumps

Two important trends in the microelectronics business are the development of three dimensional packaging solutions which increase the number electronics components on the same area, and the application of VLSI electronics under harsh environment conditions. Both trends lead to a growing importance of intermetallic compound (IMC) formation in Sn based solder joints. Due to miniaturization a growing part of the solder joint volume is transformed into IMCs and finally the reflow process becomes a transient liquid phase soldering (TLPS) process. For harsh environment applications TLPS enables the transformation of low melting Sn contacts into high melting IMC joints. In both cases a model for the prediction of migration-induced IMC formation is required for the fabrication of IMC joints.For the general prediction of the migration induced IMC formation the related material parameters are needed. Against this background the Cu₃Sn and Cu₆Sn₅ formation was observed during temperature storage tests on Amkor® Package-on-Package packages (12 × 12 mm) with SnAg_3.0Cu_0.5 ball grid arrays. A mathematical model was developed to calculate the average mass flux of Sn and Cu during the stress tests. Based on the mass flux values the activation energies and diffusion constants for Cu and Sn in Cu₃Sn and Cu₆Sn₅ were determined. Afterwards the temperature storage was combined with an AC and a DC current load to investigate thermo- and electromigration-related phenomena. Based on the IMC formation speed during the AC and the DC tests the heat of transport Q^* and the effective charge of the moving ion Z^* were calculated. An interpretation of the material parameters is given in consideration of the high defect density in Cu₃Sn and Cu₆Sn₅.     

Formation of Cu6Sn5 phase by cold homogenization in nanocrystalline Cu–Sn bilayers at room temperature

Solid state reaction between nanocrystalline Cu and Sn films was investigated at room temperature by depth profiling with secondary neutral mass spectrometry and by X-ray diffraction. A rapid diffusion intermixing was observed leading to the formation of homogeneous Cu₆Sn₅ layer. There is no indication of the appearance of the Cu₃Sn phase. This offers a way for solid phase soldering at low temperatures, i.e. to produce homogeneous Cu₆Sn₅ intermediate layer of several tens of nanometers during reasonable time (in the order of hours or less). From the detailed analysis of the growth of the planar reaction layer, formed at the initial interface in Sn(100 nm)/Cu(50 nm) system, the value of the parabolic growth rate coefficient at room temperature is 2.3 × 10^− 15 cm²/s. In addition, the overall increase of the composition near to the substrate inside the Cu film was interpreted by grain boundary diffusion induced solid state reaction: the new phase formed along the grain boundaries and grew perpendicular to the boundary planes. From the initial slope of the composition versus time function, the interface velocity during this reaction was estimated to be about 0.5 nm/h.