一种基于不变量的测试空间约简方法

测试用例的自动生成在带来方便的同时引入了大量的等价输入及过多的冗余测试用例,对于测试空间的约简能够有效地解决这一矛盾。程序不变量是用于描述程序运行过程中某些保持不变的性质的逻辑断言,可以用于指导测试用例的生成。通过程序不变量来判断测试用例的有效性,再根据无效测试用例来确定无效空间,并对无效空间进行删减,从而达到减少冗余测试用例、提高测试用例集生成速度的目的。     

基于模板框架结构的自动调测系统软件设计

针对复杂电子设备生产过程中存在的调测需求不确定、调试流程不易固化等问题,介绍了一种基于模板框架结构的自动调测系统,用户可根据调测需求,在其中定制调测项目,安排调测流程。与传统自动测试系统相比,它具有强大的扩展性、通用性和易用性。     

A Simulated Annealing Inspired Test Optimization Method for Enhanced Detection of Highly Critical Faults and Defects

When testing resources are severely limited, special attention should be paid to critical faults/defects so that important or frequent field failures arising from test escapes can be minimized. We present a new algorithm to optimize test sets aimed at significantly reducing the criticality of test escapes—especially for very short test sets that may be applied in the field. The algorithm proposes an exponential-based test set quality model to evaluate the criticality of potential undetected defects and develops a programming model to search for a test set that effectively reduces this criticality.     

Thermal-Aware SoC Test Scheduling with Test Set Partitioning and Interleaving

High temperature has become a major problem for system-on-chip testing. In order to reduce the test application time while keeping the temperatures of the cores under test within safe ranges, a thermal-aware test scheduling technique is required. This paper presents an approach to minimize the test application time and, at the same time, prevent the temperatures of cores under test going beyond given limits. We employ test set partitioning to divide test sets into shorter test sequences, and add cooling periods between test sequences so that overheating can be avoided. Moreover, test sequences from different test sets are interleaved, such that the cooling periods and the bandwidth of the test bus can be utilized for test data transportation, and hence the test application time can be reduced. The test scheduling problem is formulated as a combinatorial optimization problem, and we use the constraint logic programming (CLP) to build the optimization model and find the optimal solution. As the optimization time of the CLP-based approach increases exponentially with the problem size, we also propose a heuristic which generates longer test schedules but requires substantially shorter optimization time. Experimental results have shown the efficiency of the proposed approach.     

基于TCL的网络自动化测试系统设计

网络自动化测试系统是从网络测试的需求出发对传统的手动测试进行改进。通过采用分布式IP网络测试架构,设计了一套基于TCL的自动化测试平台,能较好地完成对待测IP网络性能进行全面综合的评价。测试例脚本将网络的性能、功能以及IP协议的测试配置流程代码化,在搭建好的测试平台上执行测试,实现了网络测试的自动化。结合＂指定VLAN...     

旋转靶标平行光束空间交叠区域的分析与验证

分析了旋转靶标工作时平行光束在空间的交叠区域,提出了该区域为可准确定义的纺锤形圆锥体区域.使用旋转靶标测试时,只需将被测设备的方位俯仰视轴交点放置在此区域内即可.使用旋转靶标对摆放在纺锤形圆锥体区域内不同位置的某型光电设备进行了多次测角和跟踪精度的验证试验,测试值标准差和平均差的最大值均远小于该型设备的对应指标.测试结果表明,只要将被测设备方位俯仰视轴的交点放置在以旋转靶标光锥顶点为中心的纺锤形圆锥体区域内,由摆放位置偏差引入的测试误差就极其有限.测试结果的离散程度很低,重复性很好,能满足测试应用的需求.验证试验证明了纺锤形圆锥体区域定义的正确性,表明该定义可作为测试时判断被测设备是否与旋转靶对准的理论依据.     

海量测试数据的场景化指标精细分析研究

本文提出了一种基于军事栅格、地理信息的多场景海量数据的精细化分析方法,能够支持用户在GIS地图上自定义测试场景;同时基于军事栅格,将海量测试数据进行切割和存储;从而实现测试数据与测试场景的关联,完成场景化指标的精细化分析。该方法能够提高场景化分析效率,深度挖掘大数据资源,节约测试和分析成本。     

一种MCU的测试解决方案

对MCU进行测试时,如何高效生成测试向量是测试的难点.文章以8位MCU STC12C5410AD为例,详细地介绍了通过使用仿真环境,以C语言编写功能测试程序,完成芯片寄存器控制和主要逻辑单元运算,然后使用集成电路测试系统直接生成测试向量的解决方案.使用此解决方案,可根据测试要求,在较短时间内开发出MCU测试程序,节约测试开发成本.     

Boundary scan based interconnect testing design for silicon interposer in 2.5D ICs

Interposer-based 2.5-dimensional integrated circuit (2.5D IC) is considered as a promising solution to problems like wire delay and power consumption faced by the semiconductor industry today. Since the interconnect wires in the silicon interposer may be defective during fabrication and assembly, they must be adequately tested to ensure product qualification. This paper presents an efficient interconnect test architecture to detect open, short and delay faults, which is compatible with the IEEE 1149.1 standard. It provides a new boundary scan structure with low test power consumption. To reduce the overall test cost, a data-package based test structure is proposed to match the test data transfer volume between TSVs and scan chains. Interconnects of multiple dies can be tested simultaneously under constrains of test power with minimum external test pins. The simulation results validate the effectiveness of the proposed test method. We also present synthesis results to evaluate the area overhead.     

Modern Test Techniques: Tradeoffs, Synergies, and Scalable Benefits

This paper will propose an overall portfolio of different modern test techniques, like reduced pin-count test, SoC multi-site test, low channel cost ATE, test vector compression, bandwidth matching, and advanced probing technologies, to lower the cost of test. The overall economic benefits, the potential synergies, the overall tradeoffs, and the scalability of the benefits of these techniques, are complex to understand and currently not well understood. This problem will be analyzed in this paper by using technical cost modeling. The dependency of the benefits on different applications will be analyzed by modeling the test cost for four different applications. It will be shown that the right match between the application and a combination of the described techniques can result in a significant reduction of the cost of test. Moreover, it will be shown that this optimal match evolves during technology progress and can enable a scalable reduction of the cost of test.     

功率VDMOS稳态热阻测试的关键影响因素

热阻值是衡量功率VDMOS器件热性能优劣的重要参数,但在实际的热阻测试过程中,诸如测试电流、延迟时间、壳温控制等因素都会对测试结果造成直接的影响。因此,测试时应当深入理解和分析各种影响因素,依据严格的测试标准灵活的使用测试设备,以达到较高的测试精度和重复性。按照稳态热阻测试的步骤,详细论述了影响其测试结果的关键因素,并提出较为准确的修正方法,设计了针对性试验对其进行了验证。试验表明,该测试方法实现了较为精确的稳态热阻测量,可为功率VDMOS热阻测试标准的制定提供参考和借鉴。     

A practical approach to evaluating test results

The author describes the procedure used at NCR Corporation to evaluate the data collected during usability tests. He points out that it can be overwhelming to face a mass of data to be compiled, categorized, analyzed, and evaluated at the end of a test, with limited time available for producing a report. This situation is avoided by defining, before a test, the tools that will be used to collect the test data and the process by which the results will be evaluated, and then performing the preliminary evaluation of data in a process parallel with the test itself. At the end of the test, an evaluation meeting is held at which the cumulative results are reviewed and solutions to the problems that have been identified are defined     

合理安排电磁兼容测试在产品测试中的顺序

实例表明,将电磁兼容试验置于气候环境影响试验与机械要求试验之前与之后进行所得的结果存在较大的差异。通过分析认为气候环境影响试验与机械要求试验可能会影响被测设备中的某些材料特性,从而影响设备的电磁兼容性能。因此电磁兼容测试应与其他测试一起形成一个有机的整体,合理安排测试顺序,可以更好地发现产品的质量问题,提高产品的技术优势和市场竞争力。     

Built-in self-test (BIST) design of high-speed carry-free dividers

This paper presents the built-in self-test (BIST) design of a C-testable high-speed carry-free divider which can be fully tested by 72 test patterns irrespective of the divider size. Using a graph labeling scheme, the test patterns, expected outputs, and control signals can be represented by sets of labels and generated by a simple circuitry. As a result, test patterns can be easily generated inside chips, responses to test patterns need not to be stored, and use of expensive test equipment is not necessary. Results show that the hardware cost for generating such labels is virtually constant irrespective of the circuit size. For the BIST design of a 64 b C-testable divider, its hardware overhead is less than 5%     

ON SHORTENING TEST SEQUENCE LENGTH FOR SIGNATURE ANALYZER

Based on the built-in self-test for logic circuit, a new approach is proposed to reduce pseudorandom test length. After finding worst faults in the circuit and creating their circuit models the output signals of these models will be compressed by linear feedback shift register. The test length for the worst faults can be obtained by analyzing compressed signature . Finally, using the relation between input probability and test length, we propose a new algorithm to shorten the test sequence length. So the optimum input probability and the shortest test length can be received.     

An on-chip frequency programmable test clock generation and application method for small delay defect detection

Small delay defects are posing a serious challenge to the quality and reliability of modern fabricated chips. A promising way for screening the timing-related defects in nanometer technology designs is faster-than-at-speed delay testing. However, the use of external automatic test equipment for faster-than-at-speed delay testing could be costly. In this paper, we present an on-chip frequency-programmable test clock generation method which facilitates faster-than-at-speed delay testing for both launch on capture and launch on shift test frameworks. With a reconfigurable launch-and-capture clock generator (LCCG) embedded on-chip, the required test clock, with a reconfigurable frequency and a high resolution, can be achieved by specifying the control information in the test patterns, which is then used to configure the LCCG. Similarly, the control information regarding test framework and clock signal selection can also be embedded in the test patterns. Experimental results are presented to validate the proposed method.     

Linking diagnostic software to hardware self test in telecomsystems

This article presents a novel approach to telecom system design that links hardware structural testing to system diagnostics software. Issues related to access of the hardware test features in the system are discussed. Linking the built-in self-test to diagnostic software reduces software complexity while increasing diagnostic accuracy. Furthermore, the use of structural test features in a routine diagnostic test permits subcritical faults to be detected and recorded in nonvolatile memory, thus facilitating failure analysis. It can then be seen that the superior test coverage, fault resolution, and flexibility that access to hardware test features gives, will be beneficial in improving overall system quality and reliability     

Multiple-Constraint Driven System-on-Chip Test Time Optimization

The cost of testing SOCs (systems-on-chip) is highly related to the test application time. The problem is that the test application time increases as the technology makes it possible to design highly complex chips. These complex chips include a high number of fault sites, which need a high test data volume for testing, and the high test data volume leads to long test application times. For modular core-based SOCs where each module has its distinct tests, concurrent application of the tests can reduce the test application time dramatically, as compared to sequential application. However, when concurrent testing is used, resource conflicts and constraints must be considered. In this paper, we propose a test scheduling technique with the objective to minimize the test application time while considering multiple conflicts. The conflicts we are considering are due to cross-core testing (testing of interconnections between cores), module testing with multiple test sets, hierarchical conflicts in SOCs where cores are embedded in cores, the sharing of the TAM (test access mechanism), test power limitations, and precedence conflicts where the order in which tests are applied is important. These conflicts must be considered in order to design a test schedule that can be used in practice. In particular, the limitation on the test power consumption is important to consider since exceeding the system's power limit might damage the system. We have implemented a technique to integrate the wrapper design algorithm with the test scheduling algorithm, while taking into account all the above constraints. Extensive experiments on the ITC'02 benchmarks show that even though we consider a high number of constraints, our technique produces results that are in the range of results produced be techniques where the constraints are not taken into account.     

A Multilayer Data Copy Test Data Compression Scheme for Reducing Shifting-in Power for Multiple Scan Design

The random-like filling strategy pursuing high compression for today's popular test compression schemes introduces large test power. To achieve high compression in conjunction with reducing test power for multiple-scan-chain designs is even harder and very few works were dedicated to solve this problem. This paper proposes and demonstrates a multilayer data copy (MDC) scheme for test compression as well as test power reduction for multiple-scan-chain designs. The scheme utilizes a decoding buffer, which supports fast loading using previous loaded data, to achieve test data compression and test power reduction at the same time. The scheme can be applied automatic test pattern generation (ATPG)-independently or to be incorporated in an ATPG to generate highly compressible and power efficient test sets. Experiment results on benchmarks show that test sets generated by the scheme had large compression and power saving with only a small area design overhead.