Algorithm-based low-power and high-performance multimedia signalprocessing

Low power and high performance are the two most important criteria for many signal-processing system designs, particularly in real-time multimedia applications. There have been many approaches to achieve these two design goals at many different implementation levels ranging from very-large-scale-integration fabrication technology to system design. We review the works that have been done at various levels and focus on the algorithm-based approaches for low-power and high-performance design of signal processing systems. We present the concept of multirate computing that originates from filterbank design, then show how to employ it along with the other algorithmic methods to develop low-power and high-performance signal processing systems. The proposed multirate design methodology is systematic and applicable to many problems. We demonstrate that multirate computing is a powerful tool at the algorithmic level that enables designers to achieve either significant power reduction or high throughput depending on their choice. Design examples on basic multimedia processing blocks such as filtering, source coding, and channel coding are given. A digital signal-processing engine that is an adaptive reconfigurable architecture is also derived from the common features of our approach. Such an architecture forms a new generation of high-performance embedded signal processor based on the adaptive computing model. The goal of this paper is to demonstrate the flexibility and effectiveness of algorithm-based approaches and to show that the multirate approach is an effective and systematic design methodology to achieve low-power and high throughput signal processing at the algorithmic and architectural level     

Development of modular electrical systems

Modular systems provide the ability to achieve product variety through the combination and standardization of components. A methodology that combines system modeling, integration analysis, and optimization techniques for development of modular systems is presented. The approach optimizes integration and interactions of system elements and creates functional and physical modules for the electrical system. The Hatley/Pirbhai methodology (1987) is used for modeling functional requirements of a system. The model defines system interfaces (interactions) to support its functions. Once the interactions among functions are identified, an incidence matrix of the interfaces is developed. A clustering algorithm is developed to identify clusters in the incidence matrix, group the functions, and create modules. A Hatley/Pirbhai architecture model is developed to represent modular system design. A detailed discussion on the importance of system modeling in design of modular systems and on the constraints that limit development of modular vehicle systems is also presented. The approach presented is systematic and can be used to support product development and decision-making in engineering design     

Power electronic converter and system control

This paper deals with modern control systems technology that is frequently applied to power conversion systems. The discussion goes far beyond the basic level of switch control in switching regulators. System-level control issues are important in expanding the market base of power electronics. Improvement in system performance involves not only the use of advanced control techniques, but also the integration of several converters or converter systems into a larger system. A fully controlled rectifier and an induction motor drive system are presented as typical applications to illustrate the use of many techniques for controlling power converters. The paper then points out how a wide variety of control techniques can be applied to enhance the controller performance and bandwidth in power electronics. These techniques include observers and adaptive control, nonlinear control, sliding and dead-beat control, and intelligent control. Finally, the paper points out how power electronic system performance can be enhanced through the use of condition monitoring and diagnostics     

X波段双极化收/发组件优化设计

介绍了一种X波段双极化收/发组件的优化设计过程。通过对组件的拓扑结构、极化隔离度、功能集成度等方面进行优化,设计出一种双极化收/发组件。该组件工作于X波段,具备发射分时、接收同时双极化工作能力;组件设计中采用了低温共烧陶瓷微波基板,提高了组件集成度;组件内部集成了定标耦合器及定标二合一合成网络,简化了系统应用中的阵面馈电;通过优化设计使组件实现了35dB以上的极化隔离度,解决了传统设计中该指标实现上的难题。     

卫星导航抗干扰专用芯片后端版图设计

随着电磁环境的日益复杂,卫星导航接收系统的抗干扰性能要求越来越高。在小型卫导接收系统的抗干扰设计中,体积和功耗已经成为最大的限制因素,抗干扰芯片的设计已成为解决该问题的有效途径。本文基于SoC Encounter后端版图设计工具,通过布局规划、电源设计、标准单元放置、时钟树综合及优化、布线等后端版图设计流程,完成了一款卫星导航抗干扰专用芯片的后端版图设计工作。     

Simulation of communication systems

When both a complex system and a complex channel model are encountered, the result is typically a design or analysis problem that cannot be solved using traditional (pencil and paper) mathematical analysis. Computer-aided techniques, which usually involve some level of numerical simulation, can be a very valuable tool in these situations. The purpose of this article is to provide a tutorial review of some of the basic techniques of communication system simulation. The authors consider the basic techniques used to represent signals, generate signals, and model linear systems, nonlinear systems, and time-varying systems within a simulation. They consider the important problem of using a simulation to estimate the performance of a communication system     

Timing of Multi-Gigahertz Rapid Single Flux Quantum Digital Circuits

Rapid Single Flux Quantum (RSFQ) logic is a digital circuit technology based on superconductors that has emerged as a possible alternative to advanced semiconductor technologies for large scale ultra-high speed, very low power digital applications. Timing of RSFQ circuits at frequencies of tens to hundreds of gigahertz is a challenging and still unresolved problem. Despite the many fundamental differences between RSFQ and semi- conductor logic at the device and at the circuit level, timing of large scale digital circuits in both technologies is principally governed by the same rules and constraints. Therefore, RSFQ offers a new perspective on the timing of ultra-high speed digital circuits.This paper is intended as a comprehensive review of RSFQ timing, from the viewpoint of the principles, concepts, and language developed for semiconductor VLSI. It includes RSFQ clocking schemes, both synchronous and asynchronous, which have been adapted from semiconductor design methodologies as well as those developed specifically for RSFQ logic. The primary features of these synchronization schemes, including timing equations, are presented and compared.In many circuit topologies of current medium to large scale RSFQ circuits, single-phase synchronous clocking outperforms asynchronous schemes in speed, device/area overhead, and simplicity of the design procedure. Synchronous clocking of RSFQ circuits at multigigahertz frequencies requires the application of non-standard design techniques such as pipelined clocking and intentional non-zero clock skew. Even with these techniques, there exist difficulties which arise from the deleterious effects of process variations on circuit yield and performance. As a result, alternative synchronization techniques, including but not limited to asynchronous timing, should be considered for certain circuit topologies. A synchronous two-phase clocking scheme for RSFQ circuits of arbitrary complexity is introduced, which for critical circuit topologies offers advantages over previous synchronous and asynchronous schemes.     

An optimization based design for integrated dependable real-time embedded systems

Moving from the traditional federated design paradigm, integration of mixed-criticality software components onto common computing platforms is increasingly being adopted by automotive, avionics and the control industry. This method faces new challenges such as the integration of varied functionalities (dependability, responsiveness, power consumption, etc.) under platform resource constraints and the prevention of error propagation. Based on model driven architecture and platform based design’s principles, we present a systematic mapping process for such integration adhering a transformation based design methodology. Our aim is to convert/transform initial platform independent application specifications into post integration platform specific models. In this paper, a heuristic based resource allocation approach is depicted for the consolidated mapping of safety critical and non-safety critical applications onto a common computing platform meeting particularly dependability/fault-tolerance and real-time requirements. We develop a supporting tool suite for the proposed framework, where VIATRA (VIsual Automated model TRAnsformations) is used as a transformation tool at different design steps. We validate the process and provide experimental results to show the effectiveness, performance and robustness of the approach.     

Low-energy wireless communication network design

Energy-efficient wireless communication network design is an important and challenging problem. Its difficulty lies in the fact that the overall performance depends, in a coupled way, on the following subsystems: antenna, power amplifier, modulation, error control coding, and network protocols. In addition, given an energy constraint, improved operation of one of the aforementioned subsystems may not yield better overall performance. Thus, to optimize performance one must account for the coupling among the above subsystems and simultaneously optimize their operation under an energy constraint. In this article we present a generic integrated design methodology that is suitable for many kinds of mobile systems and achieves global optimization under an energy constraint. By pointing out some important connections among different layers in the design procedure, we explain why our integrated design methodology is better than traditional design methodologies. We present numerical results of the application of our design methodology to a situational awareness scenario in a mobile wireless network with different mobility models. These results illustrate the improvement in performance that our integrated design methodology achieves over traditional design methodologies, and the tradeoff between energy consumption and performance.     

A design framework for e-business infrastructure integration andresource management

One of the challenges faced by an enterprise with employees in multiple locations is to design a high performance, secure and interoperable distributed computing system (DCS) to interconnect all locations and operations. The problem is computationally hard; hence, subcomponents of it have been studied in detail. These tend to be complex, predominantly theoretical, and somewhat limited from a practical standpoint in terms of providing an integrated solution. Researchers have indicated the need to study the integrated DCS design problem. We merge the complex components and demonstrate that this intrinsically hard problem can be modeled using a component-wise iterative approach. We present a methodology for resource planning and integration that is simple and practical, and can be applied to real-life problems. The methodology includes performance, cost, security and interoperability issues as DCS design objectives. It distributes data and application systems across multiple locations, and aids in security and interoperability configuration, such that the overall design objectives are satisfied. This is one of the first attempts at combining the various components of DCS design and applying it to a real-life problem. The design framework has been successfully used to design a distributed training system for a large, geographically dispersed organization     

A co-synthesis approach to embedded system design automation

Embedded systems are targeted for specific applications under constraints on relative timing of their actions. For such systems, the use of pre-designed reprogrammable components such as microprocessors provides an effective way to reduce system cost by implementing part of the functionality as a program running on the processor. However, dedicated hardware is often necessary to achieve the requisite timing performance. Analysis of timing constraints is, therefore, key to determination of an efficient hardware-software implementation. In this paper, we present a methodology for embedded system design as a co-synthesis of interacting hardware and software components. We present a decomposition of the co-synthesis problem into sub-problems, that is useful in building a framework for embedded system CAD. In particular, we present operation-level timing constraints and develop the notion of satisfiability of constraints by a given implementation both in the deterministic and probabilistic sense. Constraint satisfiability analysis is then used to define hardware and software portions of functionality. We describe algorithms and techniques used in developing a practical co-synthesis framework, vulcan. Examples are presented to show the utility of our approach.     

应用于低功耗SoC的动态时钟管理技术

文章着重分析了基于系统级的低功耗技术,提出了动态时钟管理技术,介绍了其背景、原理以及在系统低功耗中发挥的重要作用。最后,将该技术应用到一款LCD控制器中。事实表明,动态时钟管理技术在保证系统性能的前提下,大大降低了功耗,取得了很好的效果。     

Architectural Design Issues in a Clockless 32‐Bit Processor Using an Asynchronous HDL

As technology evolves into the deep submicron level, synchronous circuit designs based on a single global clock have incurred problems in such areas as timing closure and power consumption. An asynchronous circuit design methodology is one of the strong candidates to solve such problems. To verify the feasibility and efficiency of a large‐scale asynchronous circuit, we design a fully clockless 32‐bit processor. We model the processor using an asynchronous HDL and synthesize it using a tool specialized for asynchronous circuits with a top‐down design approach. In this paper, two microarchitectures, basic and enhanced, are explored. The results from a pre‐layout simulation utilizing 0.13‐μm CMOS technology show that the performance and power consumption of the enhanced microarchitecture are respectively improved by 109% and 30% with respect to the basic architecture. Furthermore, the measured power efficiency is about 238 μW/MHz and is comparable to that of a synchronous counterpart.     

Design and Management of Voltage-Frequency Island Partitioned Networks-on-Chip

The design of many core systems-on-chip (SoCs) has become increasingly challenging due to high levels of integration, excessive energy consumption and clock distribution problems. To deal with these issues, we consider network-on-chip (NoC) architectures partitioned into several voltage-frequency islands (VFIs) and propose a design methodology for runtime energy management. The proposed approach minimizes the energy consumption subject to performance constraints. Then, we present efficient techniques for on-the-fly workload monitoring and management to ensure that the system can cope with variability in the workload and various technology-related parameters. Simulation results demonstrate the effectiveness of our approach in reducing the overall system energy consumption for a real video application. Finally, the results and functional correctness are validated using an field-programmable gate-array (FPGA) prototype for an NoC with multiple VFIs.      

Reliability Analysis of Industrial Electrical Systems Using Bayesian Networks Considering Power Quality and Security Characteristics Applied to the IEEE 493 Standard Network

The application of power electronics in industrial systems has increased the use of a wide variety of reliability analysis software for commercial and industrial electrical systems. However, there are power quality and security events that are not considered by these tools. This paper describes a methodology for the reliability evaluation of industrial electrical systems using Bayesian networks which incorporates the power quality and security characteristics under events such us short-circuits, random outages and electrical transients. This methodology is applied to the standard network proposed by the IEEE 493 Gold Book to compare the system reliability indices with the ones obtained by others methodologies. This work offers a solid and practical tool for the design of industrial electrical systems     

Toward a unified and automated design methodology for multi-domain dynamic systems using bond graphs and genetic programming

This paper suggests a unified and automated design methodology for synthesizing designs for multi-domain systems, such as mechatronic systems. A multi-domain dynamic system includes a mixture of electrical, mechanical, hydraulic, pneumatic, and/or thermal components, making it difficult use a single design tool to design a system to meet specified performance goals. The multi-domain design approach is not only efficient for mixed-domain problems, but is also useful for addressing separate single-domain design problems with a single tool. Bond graphs (BGs) are domain independent, allow free composition, and are efficient for classification and analysis of models, allowing rapid determination of various types of acceptability or feasibility of candidate designs. This can sharply reduce the time needed for analysis of designs that are infeasible or otherwise unattractive. Genetic programming is well recognized as a powerful tool for open-ended search. The combination of these two powerful methods is therefore an appropriate target for a better system for synthesis of complex multi-domain systems. The approach described here will evolve new designs (represented as BGs) with ever-improving performance, in an iterative loop of synthesis, analysis, and feedback to the synthesis process. The suggested design methodology has been applied here to three design examples. The first is a domain-independent eigenvalue placement design problem that is tested for some sample target sets of eigenvalues. The second is in the electrical domain––design of analog filters to achieve specified performance over a given frequency range. The third is in the electromechanical domain––redesign of a printer drive system to obtain desirable steady-state position of a rotational load.     

A survey of design techniques for system-level dynamic powermanagement

Dynamic power management (DPM) is a design methodology for dynamically reconfiguring systems to provide the requested services and performance levels with a minimum number of active components or a minimum load on such components. DPM encompasses a set of techniques that achieves energy-efficient computation by selectively turning off (or reducing the performance of) system components when they are idle (or partially unexploited). In this paper, we survey several approaches to system-level dynamic power management. We first describe how systems employ power-manageable components and how the use of dynamic reconfiguration can impact the overall power consumption. We then analyze DPM implementation issues in electronic systems, and we survey recent initiatives in standardizing the hardware/software interface to enable software-controlled power management of hardware components