Potential‐based threshold voltage and subthreshold swing models for junctionless double‐gate metal‐oxide‐semiconductor field‐effect transistor with dual‐material gate

On the basis of quasi‐two‐dimensional solution of Poisson's equation, an analytical threshold voltage model for junctionless dual‐material double‐gate (JLDMDG) metal‐oxide‐semiconductor field‐effect transistor (MOSFET) is developed for the first time. The advantages of JLDMDG MOSFET are proved by comparing the central electrostatic potential and electric field distribution with those of junctionless single‐material double‐gate (JLSMDG) MOSFET. The proposed model explicitly shows how the device parameters (such as the silicon thickness, oxide thickness, and doping concentration) affect the threshold voltage. In addition, the variations of threshold voltage roll‐off, drain‐induced barrier lowering (DIBL), and subthreshold swing with the channel length are investigated. It is proved that the device performance for JLDMDG MOSFET can be changed flexibly by adjusting the length ratios of control gate and screen gate. The model is verified by comparing its calculated results with those obtained from three‐dimensional numerical device simulator ISE. Copyright © 2015 John Wiley & Sons, Ltd.     

Threshold voltage modeling for dual‐metal quadruple‐gate (DMQG) MOSFETs

In this paper, a three‐dimensional (3D) model of threshold voltage is presented for dual‐metal quadruple‐gate metal‐oxide‐semiconductor field effect transistors. The 3D channel potential is obtained by solving 3D Laplace's equation using an isomorphic polynomial function. Threshold voltage is defined as the gate voltage, at which the integrated charge (Q_inv) at the ‘virtual‐cathode’ reaches to a critical charge Q_th. The potential distribution and the threshold voltage are studied with varying the device parameters like gate metal work functions, channel cross‐section, oxide thickness, and gate length ratio. Further, the drain‐induced barrier lowering has also been analyzed for different gate length ratios. The model results are compared with the numerical simulation results obtained from 3D ATLAS device simulation results. Copyright © 2015 John Wiley & Sons, Ltd.     

Green's function approach for modeling of electrostatic effects in nanoscale fully depleted double‐gate silicon‐on‐insulator metal‐oxide‐semiconductor field‐effect transistors

Exact solution of two‐dimensional (2D) Poisson's equation for fully depleted double‐gate silicon‐on‐insulator metal‐oxide‐semiconductor field‐effect transistor is derived using three‐zone Green's function solution technique. Framework consists of consideration of source–drain junction curvature. 2D potential profile obtained forms the basis for estimation of threshold voltage. Temperature dependence of front surface potential distribution, back surface potential distribution and front‐gate threshold voltage are modeled using temperature sensitive parameters. Applying newly developed model, surface potential and threshold voltage sensitivities to gate oxide thickness have been comprehensively investigated. Device simulation is performed using ATLAS 2D (SILVACO, 4701 Patrick Henry Drive, Bldg. Santa Clara, CA 95054 USA) device simulator, and the results obtained are compared with the proposed 2D model. The model results are found to be in good agreement with the simulated data. Copyright © 2013 John Wiley & Sons, Ltd.     

Asymmetric halo and symmetric Single‐Halo Dual‐Material Gate and Double‐Halo Dual‐Material Gate n‐MOSFETs characteristic parameter modeling

This paper presents an analytical subthreshold surface potential model of novel structures called asymmetric pocket‐implanted Double‐Halo Dual‐Material Gate (DHDMG) and Single‐Halo Dual‐Material Gate (SHDMG) Metal Oxide Semiconductor Field Effect Transistor (MOSFET), which combines the advantages of both the channel engineering (halo) and the gate engineering techniques (dual‐material gate) to effectively suppress the short‐channel effects (SCEs). The model is derived using the pseudo‐2D analysis by applying the Gauss's law to an elementary rectangular box in the channel depletion region, considering the surface potential variation with the channel depletion layer depth. The asymmetric pocket‐implanted model takes into account the effective doping concentration of the two linear pocket profiles at the source and the drain ends. The inner fringing field capacitances are also considered in the model for accurate estimation of the subthreshold surface potential at the two ends of the MOSFET. The same model is used to find the characteristic parameters for dual‐material gate with single‐halo and double‐halo implantations. It is concluded that the DHDMG device structure exhibits better suppression of the SCEs and the threshold voltage roll‐off than a pocket‐implanted and SHDMG MOSFET after investigating the characteristics parameter improvement. In order to validate our model, the modeled expressions have been extensively compared with the simulated characteristics obtained from the 2D device simulator DESSIS. A nice agreement is achieved with a reasonable accuracy over a wide range of device parameter and bias condition. Copyright © 2012 John Wiley & Sons, Ltd.     

Shielded channel double-gate MOSFET: a novel device for reliable nanoscale CMOS applications

In this paper, the unique features exhibited by a novel double-gate (DG) metal-oxide-semiconductor field-effect transistor (MOSFET) in which the front gate consists of two side gates to 1) electrically shield the channel region from any drain voltage variation and 2) act as an extremely shallow virtual extension to the source/drain are presented. This structure exhibits significantly reduced short-channel effects (SCEs) when compared with the conventional DG MOSFET. Using two-dimensional (2-D) and two-carrier device simulation, the improvement in device performance focusing on threshold voltage dependence on channel length, electric field in the channel, subthreshold swing, and hot carrier effects, all of which can affect the reliability of complementary metal oxide semiconductor (CMOS) devices, was investigated.     

Monte Carlo analysis of dynamic characteristics and high‐frequency noise performances of nanoscale double‐gate MOSFETs

In this paper, a full‐band Monte Carlo simulator is employed to study the dynamic characteristics and high‐frequency noise performances of a double‐gate (DG) metal–oxide–semiconductor field‐effect transistor (MOSFET) with 30 nm gate length. Admittance parameters (Y parameters) are calculated to characterize the dynamic response of the device. The noise behaviors of the simulated structure are studied on the basis of the spectral densities of the instantaneous current fluctuations at the drain and gate terminals, together with their cross‐correlation. Then the normalized noise parameters (P, R, and C), minimum noise figure (NF_min), and so on are employed to evaluate the noise performances. To show the outstanding radio‐frequency performances of the DG MOSFET, a single‐gate silicon‐on‐insulator MOSFET with the same gate length is also studied for comparison. The results show that the DG structure provides better dynamic characteristics and superior high‐frequency noise performances, owing to its inherent short‐channel effect immunity, better gate control ability, and lower channel noise. Copyright © 2012 John Wiley & Sons, Ltd.     

An analytic drain current model for long‐channel undoped gate stack surrounding‐gate MOSFETs including interface fixed charges

On the basis of the exact solution of Poisson's equation and Pao–Sah double integral for long‐channel bulk MOSFETs, a continuous and analytic drain current model for the undoped gate stack (GS) surrounding‐gate (SRG) metal–oxide–semiconductor field‐effect transistor (MOSFET) including positive or negative interface fixed charges near the drain junction is presented. Considering the effect of the interface fixed charges on the flat‐band voltage and the electron mobility, the model, which is expressed with the surface and body center potentials evaluated at the source and drain ends, describes the drain current from linear region to saturation region through a single continuous expression. It is found that the surface and body center potentials are increased/decreased in the case of positive/negative interface fixed charges, respectively, and the positive/negative interface fixed charges can decrease/increase the drain current. The model agrees well with the 3D numerical simulations and can be efficiently used to explore the effects of interface fixed charges on the drain current of the gate stack surrounding‐gate MOSFETs of the charge‐trapped memory device. Copyright © 2013 John Wiley & Sons, Ltd.     

A 2‐D surface‐potential‐based threshold voltage model for short channel asymmetric heavily doped DG MOSFETs

In recent times, transistors with heavily doped body have generated much interest because of junctionless channel. In addition, proper threshold voltage regulation requires adjustment of the channel doping, as a result of which most of the compact models become invalid as they consider an intrinsic body. In this paper, a compact surface‐potential‐based threshold voltage model is developed for short channel asymmetric double‐gate metal–oxide–semiconductor field‐effect transistors with heavily/lightly doped channel. The 2‐D surface potential is computed and compared with Technology Computer Aided Design, and a relative error of 2–4 % was obtained. The threshold voltage is solved from 2‐D Poisson's equation using ‘virtual cathode’ method, and a good agreement is observed with the numerical simulations. Also, the model is compared with a reference model and a better result is obtained for heavily doped channel. Copyright © 2014 John Wiley & Sons, Ltd.     

Investigation of multi‐layered‐gate electrode workfunction engineered recessed channel (MLGEWE‐RC) sub‐50 nm MOSFET: A novel design

In this paper, a two‐dimensional (2D) analytical sub‐threshold model for a novel sub‐50 nm multi‐layered‐gate electrode workfunction engineered recessed channel (MLGEWE‐RC) MOSFET is presented and investigated using ATLAS device simulator to counteract the large gate leakage current and increased standby power consumption that arise due to continued scaling of SiO₂‐based gate dielectrics. The model includes the evaluation of surface potential, electric field along the channel, threshold voltage, drain‐induced barrier lowering, sub‐threshold drain current and sub‐threshold swing. Results reveal that MLGEWE‐RC MOSFET design exhibits significant enhancement in terms of improved hot carrier effect immunity, carrier transport efficiency and reduced short channel effects proving its efficacy for high‐speed integration circuits and analog design. Copyright © 2008 John Wiley & Sons, Ltd.     

A study of threshold voltage fluctuations of nanoscale double gate metal-oxide-semiconductor field effect transistors using quantum correction simulation

In this paper, we computationally investigate fluctuations of the threshold voltage introduced by random dopants in nanoscale double gate metal-oxide-semiconductor field effect transistors (DG MOSFETs). To calculate variance of the threshold voltage of nanoscale DG MOSFETs, a quantum correction model is numerically solved with the perturbation and the monotone iterative techniques. Fluctuations of the threshold voltage resulting from the random dopant, the gate oxide thickness, the channel film thickness, the gate channel length, and the device width are calculated. Quantum mechanical and classical results have similar prediction on fluctuations of the threshold voltage with respect to different designing parameters including dimension of device geometry as well as the channel doping. Fluctuation increases when the channel doping, the channel film thickness, and/or the gate oxide thickness increase. On the other hand, it decreases when the channel length and/or the device width increase. Calculations of the quantum correction model are quantitatively higher than that of the classical estimation according to different quantum confinement effects in nanoscale DG MOSFETs. Due to good channel controllability, DG MOSFETs possess relatively lower fluctuation, compared with the fluctuation of single gate MOSFETs (less than a half of the fluctuation[-11pc] of SG MOSFETs). To reduce fluctuations of the threshold voltage, epitaxial layers on both sides of channel with different epitaxial doping are introduced. For a certain thickness of epitaxial layers, the fluctuation of the threshold voltage decreases when epitaxial doping decreases. In contrast to conventional quantum Monte Carlo approach and small signal analysis of the Schrödinger-Poisson equations, this computationally efficient approach shows acceptable accuracy and is ready for industrial technology computer-aided design application.     

RF modeling of 40‐nm SOI triple‐gate FinFET

These last years, the triple‐gate fin field‐effect transistor (FinFET) has appeared as attractive candidate to pursue the complementary metal‐oxide semiconductor technology roadmap for digital and analog applications. However, the development of analog applications requires models that properly describe the static and RF behaviors as well as the extrinsic parameters related to the three‐dimensional FinFET architecture, in order to establish adequate design strategies. We demonstrate the feasibility of the compact model developed for symmetric doped double‐gate metal‐oxide‐semiconductor field‐effect transistor (symmetric doped double‐gate MOSFET) to reproduce the experimental dc and RF behaviors for 40‐nm technology node Silicon‐on‐Insulator triple‐gate FinFETs. Extrinsic gate capacitances and access extrinsic resistances have been included in order to properly predict the transistor small‐signal behavior, the current gain, and the maximum available power gain cut‐off frequencies. Finally, the improvement of the FinFET RF characteristics by the reduction of the parasitics is addressed. Copyright © 2014 John Wiley & Sons, Ltd.     

Device circuit co‐design to reduce gate leakage current in VLSI logic circuits in nano regime

In this paper, nanoscale metal–oxide–semiconductor field‐effect transistor (MOSFET) device circuit co‐design is presented with an aim to reduce the gate leakage curren t in VLSI logic circuits. Firstly, gate leakage current is modeled through high‐k spacer underlap MOSFET (HSU MOSFET). In this HSU MOSFET, inversion layer is induced in underlap region by the gate fringing field through high‐k dielectric (high‐k) spacer, and this inversion layer in the underlap region acts as extended source/drain region. The analytical model results are compared with the two‐dimensional Sentaurus device simulation. Good agreement is obtained between the model and Sentaurus simulation. It is observed that modified HSU MOSFET had improved off current, subthreshold slope, and drain‐induced barrier lowering characteristics. Further, modified HSU MOSFET is also analyzed for gate leakage in generic logic circuits. Copyright © 2015 John Wiley & Sons, Ltd.     

Two-dimensional analytical model of threshold voltage and drain current of a double-halo gate-stacked triple-material double-gate MOSFET

We have developed a two-dimensional analytical model for the channel potential, threshold voltage, and drain-to-source current of a symmetric double-halo gate-stacked triple-material double-gate metal–oxide–semiconductor field-effect transistor (MOSFET). The two-dimensional Poisson’s equation is solved to obtain the channel potential. For accurate modeling of the device, fringing capacitance and effective surface charge are considered. The basic drift–diffusion equation is used to model the drain-to-source current. The midchannel potential of the device is used instead of the surface potential in the current modeling, considering the fact that the punch-through current is not confined only to the surface in a fully depleted MOSFET. An expression for the pinch-off voltage is derived to model the drain current in the saturation region accurately. Various short-channel effects such as drain-induced barrier lowering, gate leakage, threshold voltage, and roll-off have also been investigated. This structure shows excellent ability to suppress various short-channel effects. The results of the proposed model are validated against data obtained from a commercially available numerical device simulator.     

An analytical study of undoped symmetric double gate MOSFET (SDG)

In the present paper, compact analytical models for the threshold voltage, threshold voltage roll‐off and subthreshold swing of undoped symmetrical double‐gate MOSFET have been developed based on analytical solution of two‐dimensional Poisson's equation for potential distribution. The developed models include drain‐induced barrier lowering (DIBL) through the V_ds‐dependent parameter. The calculated threshold voltage value, obtained from the proposed model, shows a good agreement with the experimental and published results. The simulation results for potential show that the conduction is highly confined to the surfaces. The threshold voltage sensitivity to the thickness is found to be approximately 0.2%. Model prediction indicates that subthreshold slope is not linearly related to DIBL parameter for thick silicon film. The proposed analytical models not only provide useful insight into behavior of symmetrical DG MOSFETs but also serve as the basis for compact modeling. Copyright © 2010 John Wiley & Sons, Ltd.     

Performance enhancement of recessed silicon channel double gate junctionless field-effect-transistor using TCAD tool

In this paper, we propose an n-type double gate junctionless field-effect-transistor using recessed silicon channel. The recessed silicon channel reduces the channel thickness between the underlap regions, results in lowering the number of charge carriers in the silicon channel, and therefore, diminishing the OFF-current in the device. The proposed device shows similar electrical characteristics with improved transconductance, as compared to the conventional double gate junctionless field-effect-transistor. The effect of channel length scaling on the performance have been investigated, and it has been found that the recessed junctionless device shows higher ON-to-OFF current ratio, lower subthreshold swing and better immunity against the short channel effects, namely threshold voltage roll-off and drain-induced-barrier-lowering. For a channel length of 20 nm the OFF-current of the order of 1.20?×?10^–14 A/µm, ON-to-OFF current ratio of the order of 6.01?×?10¹⁰, subthreshold swing of the value of 67 mV/dec, and DIBL of 37.8 mV V^?1 has been achieved with the proposed junctionless device, in comparison of conventional double gate junctionless FET. The performance of proposed device with respect to the variations in depth and length of recessed silicon area, has also been presented as a roadmap for further tuning of its electrical behaviour. Comparatively, steeper DC transfer characteristics and improved rail-to-rail swing in transient behaviour has been reported with the designed complementary metal–oxide–semiconductor inverter, based on recessed double gate junctionless FET. The proposed recessed silicon channel double gate junctionless field-effect-transistor has been simulated using TCAD tool.

     

Impact of high‐κ gate dielectric and other physical parameters on the electrostatics and threshold voltage of long channel gate‐all‐around nanowire transistor

High‐κ gate‐all‐around structure counters the Short Channel Effect (SCEs) mostly providing excellent off‐state performance, whereas high mobility III–V channel ensures better on‐state performance, rendering III–V nanowire GAAFET a potential candidate for replacing the current FinFETs in microchips. In this paper, a 2D simulator for the III–V GAAFET based on self‐consistent solution of Schrodinger–Poisson equation is proposed. Using this simulator, capacitance–voltage profile and threshold voltage are characterized, which reveal that gate dielectric constant (κ) and oxide thickness do not affect threshold voltage significantly at lower channel doping. Moreover, change in alloy composition of In_xGa_1‐xAs, channel doping, and cross‐sectional area has trivial effects on the inversion capacitance although threshold voltage can be shifted by the former two. Although, channel material also affects the threshold voltage, most sharp change in threshold voltage is observed with change in fin width of the channel (0.005 V/nm for above 10 nm fin width and 0.064 V/nm for sub‐10 nm fin width). Simulation suggests that for lower channel doping below 10²³ m⁻³, fin width variation affects the threshold voltage most. Whereas when the doping is higher than 10²³ m⁻³, both the thickness and dielectric constant of the oxide material have strong effects on threshold voltage (0.05 V/nm oxide thickness and 0.01 V/per unit change in κ). Copyright © 2014 John Wiley & Sons, Ltd.     

A compact interband tunneling current model for Gate-on-Source/Channel SOI-TFETs

A tunneling probability-based drain current model for tunnel field-effect transistors (FETs) is presented. First, an analytical model for the surface potential and the potential at the channel–buried oxide interface is derived for a Gate-on-Source/Channel silicon on insulator (SOI)-tunnel FET (TFET), considering the effect of the back-gate voltage. Next, a drain current model is derived for the same device by using the tunneling probability at the source–channel junction. The proposed model includes physical parameters such as the gate oxide thickness, buried oxide thickness, channel thickness, and front-gate oxide dielectric constant. The proposed model is used to investigate the effects of variation of the front-gate voltage, drain voltage, back-gate voltage, and front-gate dielectric thickness. Moreover, a threshold voltage model is developed and the drain-induced barrier lowering (DIBL) is calculated for the proposed device. The effect of bandgap narrowing is considered in the model. The model is validated by comparison with Technology Computer-Aided Design (TCAD) simulation results.     

Impact of channel length,gate insulator thickness,gate insulator material,and temperature on the performance of nanoscale FETs

Aggressive technology scaling as per Moore’s law has led to elevated power dissipation levels owing to an exponential increase in subthreshold leakage power. Short channel effects (SCEs) due to channel length reduction, gate insulator thickness change, application of high-k gate insulator, and temperature change in a double-gate metal–oxide–semiconductor field-effect transistor (DG MOSFET) and carbon nanotube field-effect transistor (CNTFET) were investigated in this work. Computational simulations were performed to investigate SCEs, viz. the threshold voltage (V_th) roll-off, subthreshold swing (SS), and I_on/I_off ratio, in the DG MOSFET and CNTFET while reducing the channel length. The CNTFET showed better performance than the DG MOSFET, including near-zero SCEs due to its pure ballistic transport mechanism. We also examined the threshold voltage (V_th), subthreshold swing (SS), and I_on/I_off ratio of the DG MOSFET and CNTFET with varying gate insulator thickness, gate insulator material, and temperature. Finally, we handpicked almost similar parameters for both the CNTFET and DG MOSFET and carried out performance analysis based on the simulation results. Comparative analysis of the results showed that the CNTFET provides 47.8 times more I_on/I_off ratio than the DG MOSFET. Its better control over the threshold voltage, near-zero SCEs, high on-current, low leakage power consumption, and ability to operate at high temperature make the CNTFET a viable option for use in enhanced switching applications and low-voltage digital applications in nanoelectronics.     

GaN-based double-gate (DG) sub-10-nm MOSFETs: effects of gate work function

Double-gate (DG) metal–oxide–semiconductor field-effect transistors (MOSFETs) with GaN channel material are very promising for use in future high-performance low-power nanoscale device applications. In this work, GaN-based sub-10-nm DG-MOSFETs with different gate work function, \(\varPhi \), were designed and their performance evaluated. Short-channel effects (SCEs) were significantly reduced by introduction of gates made of dual metals. Use of gold at the source side, having higher \(\varPhi \) (\(\varPhi _{\mathrm{Au}}=5.11\,\hbox {eV}\)) compared with aluminum (\(\varPhi _{\mathrm{Al}}=4.53\,\hbox {eV}\)), at the drain side enhanced the gate control over the channel and screened the effect of the drain on the channel. Dual-metal (DM) DG-MOSFETs showed better results in the nanoscale regime and were more robust to SCEs. Therefore, GaN-based sub-10-nm DM DG-MOSFETs are suitable candidates for use in future complementary metal–oxide–semiconductor (CMOS) technology.     

Compact 2D modeling and drain current performance analysis of a work function engineered double gate tunnel field effect transistor

The ongoing trend of device dimension miniaturization is attributed to a large extent by the development of several non-conventional device structures among which tunneling field effect transistors (TFETs) have attracted significant research attention due to its inherent characteristics of carrier conduction by built-in tunneling mechanism which in turn mitigates various short channel effects (SCEs). In this work, we have, incorporated the innovative concept of work function engineering by continuously varying the mole fraction in a binary metal alloy gate electrode along the horizontal direction into a double gate tunneling field effect transistor (DG TFET), thereby presenting a new device structure, a work function engineered double gate tunneling field effect transistor (WFEDG TFET). We have presented an explicit analytical surface potential modeling of the proposed WFEDG TFET by the solving the 2-D Poisson’s equation. From the surface potential expression, the electric field has been derived which has been utilized to formulate the expression of drain current by performing rigorous integration on the band-to-band tunneling generation rate over the tunneling region. Based on this analytical modeling, an overall performance comparison of our proposed WFEDG TFET with its normal DG TFET counterpart has been presented in this work to establish the superiority of our proposed structure in terms of surface potential and drain current characteristics. Analytical results have been compared with SILVACO ATLAS device simulator results to validate our present model.