一个0.14 THz同轴波导五路径向功率合成器

基于同轴波导径向合成器提出了一款可用于太赫兹频段的任意路数功率合成器。该功率合成器采用二阶阶梯变换结构,实现电场方向从同轴轴向到径向的扩散传播,并通过径向外围均匀分布的Y型功分结构实现任意路数功分。以D波段五路功率合成器为例,采用背靠背测试,在130 GHz到150 GHz频带内,背靠背插入损耗优于2 dB,带内回波损耗优于15 dB。由于是背靠背测试,因此该功率合成器单边损耗约为0.72 dB,折合合成效率为84.7%。     

Ka 波段宽带单边带调制器集成电路的设计

基于相移法实现SSB(单边带)调制器理论,设计制造了一种Ka 波段宽带SSB 调制器集成电路。对相移法产生单边带调制信号的原理进行了分析,利用无源电路的3D 电磁仿真分析和ADS 整体电路非线性仿真相结合的方法对调制器进行了优化。设计制造的90°相移电桥网络和同相合成器满足了产生Ka 波段SSB 信号的幅相要求,同时给出了测试结果。调制器在30 ~36GHz 频带内插入损耗臆14dB;载波和对称边带抑制逸15dB;其它边带抑制逸13dB;输入1dB 压缩功率38dBm;外形尺寸18mm×6mm。这种相移法单边带调制器不需要带通滤波器,具有电路简单,载波抑制比高,对相位误差要求不高的优点。     

一种Ka 波段固态功率合成器

：文章介绍了一种新型的Ka 波段固态空间功率合成器。在此功率合成器H 面中插入一个电阻片,可以极大地提 高功率合成器的隔离度和回波损耗,通过三维仿真软件HFSS 仿真计算证明了可行性,最后实现一个完全对称的两路功 率分配/合成器。仿真结果显示,此功率合成器在29-31GHz 内,插入损耗小于0.21dB,隔离度优于19dB,端口回波损耗 优于27dB。     

一种S波段线性CDMA用高功率放大器

利用推挽电路和宽边耦合线合成器设计了一种S波段300 W固态高线性功率放大器。推挽电路利于宽带功率匹配,宽边耦合线合成器提高了功率合成的功率容量,从而实现了高线性输出功率的平坦特征。该功率放大器在S波段90 MHz频率范围内实现了线性300 W的功率输出,带内增益65±0.5 dB,三阶互调≤-45 dBc。     

调频立体声多工广播全固态发射技术与覆盖方式

本阐述了调频立体声多工广播编码激励器、RF功率放大合成器、VL10RF功率放大器、天馈线分路系统单单元的工作过程,并对调频立体声多工广播的覆盖方式进行了简要叙述。     

毫米波10W空间功率合成放大器研制

提出了一种结构新颖的2×2空间功率合成结构.该结构在30~36GHz范围内,回波损耗优于10dB,插入损耗小于1dB.以此结构为基础再利用4块GaAs MMIC单片制作出了一个新型的功率合成器.该功率合成器在31~34GHz的频率范围内,在±0.64dB的增益波动下能得到大于10W的输出功率,并且在31GHz时具有最大的饱和输出功率13.8W,在带内的平均合成效率大于80%.     

L波段宽带8路功率合成器设计

本文设计了一种L波段宽带8路功率合成器,在传统Wilkinson级联的合成器的基础上,提出一种在第二级和第三级Wilkinson功分器之间加入匹配电路的新型功率合成器,从而工作在宽带系统中。设计的功率合成器工作频段为1.2-1.4GHz,合成器输出端口S11-24dB,幅度不一致性ΔA0.15dB,相位不一致性Δφ0.5o,插损︱S21︱9.4dB。考虑功放的抗失配能力,每个输入端口的电压驻波系数VSWR in1.2。     

HDTV中立体声转化为5.1声道环绕声的实现

介绍了高清电视制作的全过程都采用立体声录制和剪辑,在播出时采用环绕声场合成器或多用途视音频处理器实现立体声向5.1声道环绕声的转换,指出高清电视前期拍摄立体声传声器的选择、立体声传声器的摆放、现场的立体声监听、立体声录音电平的调节、立体声的剪辑和加工是实现5.1声道环绕声转换的保证,使用环绕声处理器是实现5.1声道环绕...     

C波段E面扇形波导等功率合成器的设计北大核心CSCD

设计了一种16路等功率分配功率合成器。该功率合成器采用径向功率合成的方式,基于E面扇形波导原理进行设计。最终设计的功率合成器总体尺寸为480.1 mm×457.7 mm×60.3 mm。仿真和测试结果显示,该功率合成器工作频段为5.2~5.9 GHz,各路带内插入损耗≤0.5 dB,相位平衡度≤3°。该合成器在空气击穿阈值的条件下,可以承受最大输入峰值功率8000 W,满足大功率合成需要,可用于C波段固态发射机的相关应用中。     

L波段紧凑型平面三路功率合成器设计

提出了一种平面结构的L波段三路功率合成器,通过两节三路四分之一波长阻抗变换器与平面隔离电阻构成的微带电路实现。合成器使用仿真软件优化计算结果并得到最终设计。测试结果与仿真结果吻合：在1.1GHz至1.7GHz带宽内,各个端口驻波比小于1.13;输入端口间隔离度大于25dB;合成效率大于94.5％且最大幅度不平坦度小于0.05dB。这种功率合成器结构紧凑,性能达到设计要求。     

新型高性能调频发射机的研究

介绍了一种全新的FM调制器结构.该调制器基于小数分频锁相环技术,并在电荷泵单元中引入额外偏差电流消除电荷泵失配对带内噪声的影响.该芯片采用CSMC 0.5μm DPTM CMOS工艺,测试结果表明,其SNR≥82dB,THD≤0.08,最大带外辐射能量低于-90dBc/Hz.此外,该芯片还采用自动频率调整的方法避免调节片外电感.该芯片的这些特点十分适合调频发射的要求.     

A 1.2 mW RDS receiver for portable applications

A 0.9 V 1.2 mA fully integrated radio data system (RDS) receiver for the 88-108 MHz FM broadcasting band is presented. Requiring only a few external components (matching network, VCO inductors, loop filter components), the receiver, which has been integrated in a standard digital 0.18 /spl mu/m CMOS technology, achieves a noise figure of 5 dB and a sensitivity of -86dBm. The circuit can be configured and the RDS data retrieved via an I/sup 2/C interface so that it can very simply be used as a peripheral in any portable application. A 250 kHz low-IF architecture has been devised to minimize the power dissipation of the baseband filters and FM demodulator. The frequency synthesizer consumes 250 /spl mu/A, the RF front-end 450 /spl mu/A while providing 40 dB of gain, the baseband filter and limiters 100 /spl mu/A, and the FM and BPSK analog demodulators 300 /spl mu/A. The chip area is 3.6 mm/sup 2/.     

Molybdenum gate MOS applied to an AM/FM digital frequency synthesizer

An n-channel molybdenum self-aligned gate MOS technology has been developed and applied to an AM/FM digital frequency synthesizer. A high-frequency programmable divider operating at 180 MHz has been achieved by the use of molybdenum, low parasitic capacitance structures and zero-threshold MOS transistors, while maintaining conventional design rules. Molybdenum gate MOS has enabled the realization of a single-chip system, which consists of a directly programmable divider for the AM/FM local oscillators, a reference counter, a phase comparator, a circuit for dial tuning, and memories for storing the frequencies for 16 stations. A differential comparator has been fabricated on the LSI chip to simplify digital tuning in the receiver.     

基于DDS的高可靠性雷达信号发生器设计与实现

介绍了一种基于直接数字频率合成的高可靠性雷达信号发生器的设计方案,实现最高频率400 MHz的点频、线性调频和步进频率雷达信号输出。为提高系统可靠性设计加入了对系统工作状态进行监测和控制的闭环回路。测试结果表明系统输出信号频率稳定,可靠性高。     

Active feedback microstrip leaky wave antenna-synthesiser designwith suppressed back lobe radiation

The design of an active leaky-wave antenna which integrates the antenna with a feedback synthesizer is introduced. The measurement result shows that the antenna has very low back lobe radiation compared with that of traditional single-terminal feeding leaky-wave antennas. Single frequency measurement shows that the radiated power difference between the main beam and back lobe is >15 dB at 8.2 GHz. For the designed feedback synthesizer antenna, the measured radiated power difference between the main beam and back lobe is >15 dB at 9.25 GHz, and the scanning angle is ~5° as the synthesizer frequency sweeps from 9.25 to 9.37 GHz     

Noise performance of a 94-GHz Gunn-effect local oscillator

AM and FM noise has been measured on a Gunn-effect local oscillator at 94 GHz. Away from the carrier, AM noise was found to be 10 dB lower than either an IMPATT or a klystron at this frequency. Both AM and FM noise indicate1/fdependency close to the carrier frequency.     

Adaptive digital calibration techniques for narrow band low-IF receivers with on-chip PLL

Digital calibration and control techniques for narrow band integrated low-IF receivers with on-chip frequency synthesizer are presented. The calibration and control system, which is adopted to ensure an achievable signal-to-noise ratio and bit error rate, consists of a digitally controlled, high resolution dB-linear automatic gain control (AGC), an inphase (I) and quadrature (Q) gain and phase mismatch calibration, and an automatic frequency calibration (AFC) of a wideband voltage-controlled oscillator in a PLL based frequency synthesizer. The calibration system has a low design complexity with little power and small die area. Simulation results show that the calibration system can enlarge the dynamic range to 72 dB and minimize the phase and amplitude imbalance between I and Q to 0.08° and 0.024 dB, respectively, which means the image rejection ratio is better than 60 dB. In addition, the calibration time of the AFC is 1.12μs only with a reference clock of 100 MHz.     

Characteristics of a variable length ring oscillator and its use in PLL based systems

This paper describes the properties of a multiplexer based variable length ring oscillator and the effects of using it as a voltage controlled oscillator (VCO) in a phase locked loop (PLL) based system. The application of the proposed VCO in a PLL used as an FM demodulator or as a frequency synthesizer has been examined and it has been shown that the length control facility of the VCO could be used for improving the performances of those systems. Hardware experimental results confirm the predictions regarding the performance enhancement.     

A low-power monolithic CMOS transceiver for 802.11b wireless LANs

A single-chip low-power transceiver IC operating in the 2.4 GHz ISM band is presented. Designed in 0.18 μm CMOS, the transceiver system employs direct-conversion architecture for both the receiver and transmitter to realize a fully integrated wireless LAN product. A sigma-delta (∑△) fractional-N frequency synthesizer provides on-chip quadrature local oscillator frequency. Measurement results show that the receiver achieves a maximum gain of 81 dB and a noise figure of 8.2 dB, the transmitter has maximum output power of-3.4 dBm and RMS EVM of 6.8%. Power dissipation of the transceiver is 74 mW in the receiving mode and 81 mW in the transmitting mode under a supply voltage of 1.8 V, including 30 mW consumed by the frequency synthesizer. The total chip area with pads is 2.7×4.2 mm2.     

基于FPGA的相位式激光测距系统中信号源的研制

提出在相位式激光测距系统中以FPGA代替专用DDS芯片作为信号源的方法,并对在FPGA中实现DDS功能及其外围硬件实现作了具体阐述,最后系统验证信噪比可达60 dB以上.它比传统的相位测距拥有更好的信号源、频率转换率、以及更低的功耗和更小的体积.