集成电路高层故障模型间关系分析方法

集成电路的测试变得日益重要，传统的门级测试虽然效果很好，但是随着电路规模的增大而面临着测试时间太长的困境．高层测试可以很好地缓解测试时间过长的问题，但最大的困难是缺少恰当的故障模型．通过对高层故障模型与门级固定型故障模型间关系可以建立高层故障模型的评估规则。在该规则下可以再对高层故障模型间关系进行分析，以确定彼此间的覆盖关系．归纳模型间的互相覆盖以确定彼此是否包含，这有助于对高层故障模型进行评估，寻找能够对应逼近门级固定型（stuck-at）故障模型的高层故障模型序列，该模型序列有望指导新的测试生成．最后，以对ITC99中标准时序电路的实验来说明该理论方法．     

利用UML-RT序列图支持基于事务的SoC系统级功能验证

SoC基于事务的验证方法面临的一个重要问题是如何设计验证系统级复杂交互行为的事务测试序列。基于场景的序列图是设计人员捕获系统级功能规约的良好方法。本文提出了一种利用UML-RT序列图捕获SoC各个IP核之间的通信协作行为,为基于事务的验证建立高层规约,指导系统级测试序列生成的方法。我们自行开发了一个基于构件的事务验证环境SoC-CBTVE,并在该环境中利用本文的方法对一个典型的SoC设计进行了验证和分析。实验结果表明,利用UML-RT序列图能够捕获SoC系统级IP核之间的复杂通信行为,有效支持SoC系统级功能验证。     

High-level test generation for VLSI

The authors survey high-level approaches to test generation for VLSI circuits, which can significantly reduce test generation time while still providing good fault coverage. High-level approaches view the circuit with less structural detail, that is, from a more abstract viewpoint and often hierarchically. The authors first review some basic circuit and fault models and the two most widely known test-generation algorithms as a basis for comparison between high-level and low-level techniques. The authors then examine the more important high-level approaches, which fall into two broad classes, namely algorithmic and heuristic     

SPARC体系结构处理器测试方法研究与实现

处理器离线测试广泛采用随机测试技术,但是随机测试技术生成大量测试代码,并且测试覆盖率不高;主要针对随机测试的不足,借鉴基于软件内建自测试方法建立处理器模块级于系统级功能模型,后分析功能模型可能发生错误,针对错误模型开发测试代码来提高错误覆盖率;经测试,模块级测试覆盖到所有功能点,达到功能模块100%测试,系统级的测试覆盖到SPARC V8的所有指令异常、正常测试用例;测试结果表明,所采取的测试方案对提高错误覆盖率是行之有效的.     

ASIC测试生成和可测性分析系统ATGTA

本文介绍了一个面向非扫描设计的实用的ASIC测试生成和可测性分析系统—ATG－TA.它采用功能块组同步时序电路模型和功能块引腿固定故障模型．可接收四种常用语言描述的电路网表．用FDCM方法引导测试生成过程，用DRFM方法识别组合冗余故障，通过测度分析与规则判定相结合识别时序电路中的不可测故障．用G－F二值算法按有限回溯测试模式产生方法推导测试向量．反向追踪时，采用宽度和深度动态交替代先策略．ATGTA已实际用于四万门以内的非扫描单双向ASIC芯片，效果良好．     

Computing rank dependent utility in graphical models for sequential decision problems

This paper is devoted to automated sequential decision in AI. More precisely, we focus here on the Rank Dependent Utility (RDU) model. This model is able to encompass rational decision behaviors that the Expected Utility model cannot accommodate. However, the non-linearity of RDU makes it difficult to compute an RDU-optimal strategy in sequential decision problems. This has considerably slowed the use of RDU in operational contexts. In this paper, we are interested in providing new algorithmic solutions to compute an RDU-optimal strategy in graphical models. Specifically, we present algorithms for solving decision tree models and influence diagram models of sequential decision problems. For decision tree models, we propose a mixed integer programming formulation that is valid for a subclass of RDU models (corresponding to risk seeking behaviors). This formulation reduces to a linear program when mixed strategies are considered. In the general case (i.e., when there is no particular assumption on the parameters of RDU), we propose a branch and bound procedure to compute an RDU-optimal strategy among the pure ones. After highlighting the difficulties induced by the use of RDU in influence diagram models, we show how this latter procedure can be extended to optimize RDU in an influence diagram. Finally, we provide empirical evaluations of all the presented algorithms.     

Comprehensive analysis of FBD test coverage criteria using mutants

Function block diagram (FBD), a graphical modeling language for programmable logic controllers, has been widely used to implement safety critical system software such as nuclear reactor protection systems. With the growing importance of structural testing for FBD models, structural test coverage criteria for FBD models have been proposed and evaluated using mutation analysis in our previous work. We extend the previous work by comprehensively analyzing the relationships among fault detection effectiveness, test suite size, and coverage level through several research questions. We generate a large number of test suites achieving an FBD test coverage ranging from 0 to 100 %, and we also generate many artificial faults (i.e. mutants) for the FBD models. Our analysis results show that the fault detection effectiveness of the FBD coverage criteria increases with increasing coverage levels, and the coverage criteria are highly effective at detecting faults in all subject models. Furthermore, the test suites generated with the FBD coverage criteria are more effective and efficient than the randomly generated test suites. The FBD coverage criteria are strong at detecting faults in Boolean edges, while relatively weak at detecting wrong constants in FBD models. Empirical knowledge regarding our experiments provide the validity of using the FBD coverage criteria, and therefore, of FBD model-based testing.     

Efficient sequential test generation based on logic simulation

In this article, we present an efficient logic-simulation-based test generator that executes significantly more quickly than its fault-simulation-based counterparts. This test generator's fault coverage compares favorably with that of the latest techniques for large sequential circuits. It uses a genetic algorithm to achieve both high fault coverage and short test generation times     

On the Use of Functional Test Generation in Diagnostic Test Generation for Synchronous Sequential Circuits

We study the relationship between diagnostic test generation for a gate-level fault model, which is used for generating diagnostic test sets for manufacturing defects, and functional test generation for a high-level fault model. In general, a functional fault may partially represent some of the effects of one gate-level fault but not another. Generating a test sequence for the functional fault is then likely to detect one gate-level fault but not the other, thus distinguishing the two faults. This relationship points to the ability to use a functional test generation procedure (that targets functional fault detection) as a way of generating diagnostic test sequences for gate-level faults. We use this observation in two ways. The more direct way is to define functional faults that correspond to the differences between pairs of gate-level faults. The second way is to use functional test sequences as diagnostic test sequences without explicitly considering gate-level faults. We support the use of the resulting procedures with experimental results.     

Linking simulation with formal verification at a higher level

We use simulation to bridge the gap between specification and formal verification of high-level models and simulation of RTL models. The authors apply their practical, two-phase procedure for defining the refinement map to the Alpha 21364 multiprocessing hardware. The methodology and tools they present can improve simulation coverage. Our technique verifies that a hardware design described at the RTL is a correct implementation of an algorithm-level, executable formal specification. We use a high-level formal specification as the basis for monitoring functional correctness, measuring simulation coverage, and generating test cases.     

Functional-Level Fault Simulation with Concurrent and Parallel Mechanisms Using Object-Oriented VLSI Model

The functional-level test has been proposed as an alternative to reduc the complexity of test when VLSI gets larger and more complicated.It has been successful for circuits such as memories,PLAs and microprocessors.However,the functional-level test for general functional models has sedldom been studied.This paper presents an object-oriented VLSI model and a functional-level fault simulation methodology for general functional model.Based on the proposed VLSI model,FFS(Functional-level Fault Simulator)with friendly visual interface has been implemented on Microsoft Windows platform by use of C .It is an integral part of MVS(Functional test Modeling and Verification System)--an extended subsystem of TeDS(Test Development System).The goal of FFS is to determine the fault coverage,generate fault dictionary and compact original test set at the function-level.In order to be efficient,FFS uses the concurrent and parallel mechanisms by taking advantage of the object-oriented VLSI model.The object-oriented VLSI model based fault simulation has been validated in the functional-level test by simulation results and the satisfying performance of FFS.     

A practical model‐based statistical approach for generating functional test cases: application in the automotive industry

With the growing complexity of industrial software applications, industrials are looking for efficient and practical methods to validate the software. This paper develops a model‐based statistical testing approach that automatically generates online and offline test cases for embedded software. It discusses an integrated framework that combines solutions for three major software testing research questions: (i) how to select test inputs; (ii) how to predict the expected results of a test; and (iii) when to stop testing software. The automatic selection of test inputs is based on a stochastic test model that accounts for the main particularity of embedded software: time sensitivity. Software test practitioners may design one or more test models when they generate random, user‐oriented, or fault‐oriented test inputs. A formal framework integrating existing and appropriate specification techniques was developed for the design of automated test oracles (executable software specifications) and the formal measurement of functional coverage. The decision to stop testing software is based on both test coverage objectives and cost constraints. This approach was tested on two representative case studies from the automotive industry. The experiment was performed at unit testing level in a simulated environment on a host personal computer (automatic test execution). The two software functionalities tested had previously been unit tested and validated using the test design approach conventionally used in the industry. Applying the proposed model‐based statistical testing approach to these two case studies, we obtained significant improvements in performing functional unit testing in a real and complex industrial context: more bugs were detected earlier and in a shorter time. Copyright © 2012 John Wiley & Sons, Ltd.     

基于仿真的电路板级故障诊断测试方法

针对某雷达定时器板的电路特点,提出了一种基于仿真的电路板级故障诊断测试方法。首先,利用pspice对被测电路进行功能模型建模和故障模型建模,根据功能模型构建电路仿真原理图进行功能仿真,进而利用故障模型做故障注入进行故障仿真,仿真结束获取功能仿真和故障仿真数据,通过小波分析的方法提取仿真数据的特征,包括能量分布特征提取、极值特征提取和熵特征提取,并做测试节点优化删除冗余数据,最后通过概念格的方法对特征数据做训练,生成应用于被测对象的故障诊断模型。通过获取的故障诊断模型对诊断数据进行故障推理,验证了测试方法的可行性。     

A time/structure based software reliability model

The past 20 years have seen the formulation of numerous analytical software reliability models for estimating the reliability growth of a software product. The predictions obtained by applying these models tend to be optimistic due to the inaccuracies in the operational profile, and saturation effect of testing. Incorporating knowledge gained about some structural attribute of the code, such as test coverage, into the time-domain models can help alleviate this optimistic trend. In this paper we present an enhanced non-homogeneous Poisson process (ENHPP) model which incorporates explicitly the time-varying test-coverage function in its analytical formulation, and provides for defective fault detection and test coverage during the testing and operational phases. It also allows for a time varying fault detection rate. The ENHPP model offers a unifying framework for all the previously reported finite failure NHPP models via test coverage. We also propose the log-logistic coverage function which can capture an increasing/decreasing failure detection rate per fault, which cannot be accounted for by the previously reported finite failure NHPP models. We present a methodology based on the ENHPP model for reliability prediction earlier in the testing phase. Expressions for predictions in the operational phase of the software, software availability, and optimal software release times subject to various constraints such as cost, reliability, and availability are developed based on the ENHPP model. We also validate the ENHPP model based on four different coverage functions using five failure data sets. This revised version was published online in June 2006 with corrections to the Cover Date.     

Implicit GSPN reachability set generation using decision diagrams

Implicit techniques for representing and generating the reachability set of a high-level model have become quite efficient. However, such techniques are usually restricted to models whose events have equal priority. Models containing events with differing classes of priority or complex priority structure, in particular models with immediate events, have thus been required to use less-efficient explicit reachability set generation techniques. In this paper, we present an efficient implicit technique, based on multi-valued decision diagram (MDD) representations for sets of states and matrix diagram representations for next-state functions, that can handle models with complex priority structure. We adapt an efficient Kronecker-based reachability set generation algorithm to work with matrix diagrams. If the model contains immediate events, the vanishing states can be eliminated either during generation, by manipulating the matrix diagram, or after generation, by manipulating the MDD. We apply both techniques to several models and give detailed experimental results.     

基于通信多端口有限状态机的协议互操作性测试生成研究

协议测试是一种保证网络通信协议实现质量的重要技术，互操作性测试是一类常用的协议测试技术．文章提出了一种基于通信多端口有限状态机模型的协议互操作忡测试生成方法．首先采用已有的基于可达性分析的方法生成集中式测试序列；然后采用单一错误模型对其进行系统的错误覆盖分析，为达到更高的错误覆盖度，进一步提出一种增强的测试生成算法；最后讨论了互操作性测试巾的控制观察问题，选择适当的分布式测试架构，并进而生成分布式同步测试序列．实验结果表明：与原有方法相比，该方法可以有效地提高测试集的错误覆盖，并具备一定的可行性和有效性．     

一种基于粗集理论的车地无线通信设备故障诊断方法*

针对车地无线通信设备故障诊断信息不一致的情况下进行故障的推理和诊断,提出了一种基于粗集理论的车地无线通信装备故障诊断方法。该方法从诊断决策支持系统定义出发,将车地无线通信设备故障诊断问题用一个不同简化层次的故障决策网络表示,由网络节点根据定义出的规则置信度和覆盖度可推导出对应有效的故障诊断规则集合。通过故障诊断规则匹配,便可方便得出车地通信单元故障诊断结果,实例分析表明该方法具有较好诊断有效性。     

VFSim: Concurrent Fault Simulation at Register Transfer Level

VLSI testing is being pushed to the high-level based technology. In this paper a Verilog Register transfer level Model (VRM) for integrated circuits is proposed. The model provides a text format file, which is convenient and more practical for developing succeeding Register Transfer Level (RTL) test tools, such as fault simulation, test pattern generation and so forth. Based on the VRM, an RTL concurrent fault simulation approach is presented. After RTL fault models and super faults defined, the concurrent fault simulation algorithm is given. The corresponding RTL concurrent fault simulator, VFSim, was implemented. The initial experiments show that the RTL fault simulator is efficient for VLSI circuits.     

故障树转化为二元决策树的算法研究

故障树分析法在实施过程中会遇到计算量大的问题,二元决策图是解决这个问题的一种新途径。故障树转化为二元决策图涉及的一个关键问题就是对基本事件的排序,但是基本事件排序是一个NP问题。为了解决这个问题提出了一个将故障树转化为二元决策图的启发式算法,此算法既避免了基本事件排序这个难题,同时又充分考虑了故障树的具体结构,使得到的二元决策图尽量的简单。     

Influence diagrams with multiple objectives and tradeoff analysis

Influence diagrams have been important models for decision problems because of their ability to both model a problem rigorously at its mathematical level and depict its high-level structure graphically. Once the structure and numerical details of an influence diagram have been specified, it can be evaluated to determine the optimal decision policy. However, when evaluating multiple objectives, in the past this determination was based on the assumption that utility functions that commensurate the objectives are available. This paper extends the structure and solution algorithm for influence diagrams to allow for the inclusion of noncommensurate objectives using multiobjective tradeoff analysis instead of utility theory. This eliminates the need to specify any preference information before the influence diagram is solved. The proposed multiobjective-based methodology is also useful for decision makers who either do not want to accept the assumptions of utility theory for a particular problem, or are confronted with a problem in which it is neither practical nor viable to construct a utility function. Additionally, this paper establishes the relationship between multiobjective influence diagrams and multiobjective decision trees. This relationship is important because it allows a decisionmaker to utilize the advantages of both representations. An example problem is presented to introduce both the extended multiobjective influence diagram methodology and the relationship linking multiobjective decision trees to multiobjective influence diagrams.