A 13 bit 10 MHz bandwidth MASH 3–2 Σ∆ modulator in 90 nm CMOS

In this paper, a new multi loop sigma‐delta (ΣΔ) modulator is proposed which employs one order redundant noise shaping in the first stage so the effect of the quantization noise leakage is minimized. Thus, analog circuit requirements are considerably relaxed compared to the conventional Multi‐stAge‐noise‐SHaping (MASH) structures. This enhancement makes the structure appropriate for low voltage and broadband applications. The proposed architecture is compared with traditional high‐order structures, and the advantages are demonstrated by both the analysis and behavioral system level simulations. As a prototype, the proposed MASH 3–2 sigma‐delta modulator is designed, and the detailed design procedure is presented from the system level to the circuit level in a 90 nm CMOS technology. Circuit level simulation results show that the modulator achieves a peak signal‐to‐noise and distortion ratio of 79.4 dB and 79 dB dynamic range over a 10 MHz bandwidth with a sampling frequency of 160 MHz. It consumes 35.4 mW power from a single 1 V supply. Copyright © 2012 John Wiley & Sons, Ltd.     

A 1.2 V 83 dB DR single‐ended input SC ΔΣ modulator including a large‐swing analog buffer for portable ECG applications

This study proposes a subsystem consisting of an analog buffer and a single‐ended input to a fully differential ΔΣ modulator to obtain low‐power consumption for portable electrocardiogram applications. With the proposed subsystem, the need for an inverting amplifier is avoided, and low‐power consumption is achieved. The ΔΣ modulator with a second order, 1 bit, and cascade of integrators feedforward structure consumes a low power, in which an inverting and a non‐inverting path implement a single‐ended input to fully‐differential signals. A double sampling technique is proposed for a digital‐to‐analog converter feedback circuit to reduce the effect of the reference voltage, reduce the amplifier requirements, and obtain low‐power consumption. Input‐bias and output‐bias transistors working in the weak‐inversion region are implemented to obtain an extremely large swing for the analog buffer. At a supply voltage of 1.2 V, signal bandwidth of 250 Hz, and sampling frequency of 128 kHz, the measurement results show that the modulator with a buffer achieves a 77 dB peak signal‐to‐noise‐distortion ratio, an effective‐number‐of‐bits of 12.5 bits, an 83 dB dynamic range, and a figure‐of‐merit of 156 dB. The total chip size is approximately 0.28 mm² with a standard 0.13 µm Complementary Metal‐Oxide‐Silicon (CMOS) process. Copyright © 2016 John Wiley & Sons, Ltd.     

A wideband time‐based continuous‐time sigma‐delta modulator with 2nd order noise‐coupling based on passive elements

Embedding the time encoding approach inside the loop of the sigma‐delta modulators has been shown as a promising alternative to overcome the resolution problems of analog‐to‐digital converters in low‐voltage complementary metal‐oxide semiconductor (CMOS) circuits. In this paper, a wideband noise‐transfer‐function (NTF)‐enhanced time‐based continuous‐time sigma‐delta modulator (TCSDM) with a second‐order noise‐coupling is presented. The proposed structure benefits from the combination of an asynchronous pulse width modulator as the voltage‐to‐time converter and a time‐to‐digital converter as the sampler to realize the time quantization. By using a novel implementation of the analog‐based noise‐coupling technique, the modulator's noise‐shaping order is improved by two. The concept is elaborated for an NTF‐enhanced second‐order TCSDM, and the comparative analytical calculations and behavioral simulation results are presented to verify the performance of the proposed structure. To further confirm the effectiveness of the presented structure, the circuit‐level implementation of the modulator is provided in Taiwan Semiconductor Manufacturing Company (TSMC) 90 nm CMOS technology. The simulation results show that the proposed modulator achieves a dynamic range of 84 dB over 30 MHz bandwidth while consuming less than 25 mW power from a single 1 V power supply. With the proposed time‐based noise‐coupling structure, both the order and bandwidth requirements of the loop filter are relaxed, and as a result, the analog complexity of the modulator is significantly reduced. Copyright © 2015 John Wiley & Sons, Ltd.     

A subthreshold current‐sensing ΣΔ modulator for low‐voltage and low‐power sensor interfaces

A continuous‐time (CT) ΣΔ modulator for sensing and direct analog‐to‐digital conversion of nA‐range (subthreshold) currents is presented in this work. The presented modulator uses a subthreshold technique based on subthreshold source‐coupled logic cells to efficiently convert subthreshold current to digital code without performing current‐to‐voltage conversion. As a benefit of this technique, the current‐sensing CT ΣΔ modulator operates at low voltage and consumes very low power, which makes it convenient for low‐power and low‐voltage current‐mode sensor interfaces. The prototype design is implemented in a 0.18 µm standard complementary metal‐oxide semiconductor technology. The modulator operates with a supply voltage of 0.8 V and consumes 5.43 μW of power at the maximum bandwidth of 20 kHz. The obtainable current‐sensing resolution ranges from effective number of bits (ENOB) = 7.1 bits at a 5 kHz bandwidth to ENOB = 6.5 bits at a 20 kHz bandwidth (ENOB). The obtained power efficiency (peak FoM = 1.5 pJ/conv) outperforms existing current‐mode analog‐to‐digital converter designs and is comparable with the voltage‐mode CT ΣΔ modulators. The modulator generates very low levels of switching noise thanks to CT operation and subthreshold current‐mode circuits that draw a constant subthreshold current from the voltage supply. The presented modulator is used as a readout interface for sensors with current‐mode output in ultra low‐power conditions and is also suitable to perform on‐chip current measurements in power management circuits. Copyright © 2014 John Wiley & Sons, Ltd.     

A single‐bit continuous‐time delta‐sigma modulator using clock‐jitter and inter‐symbol‐interference suppression technique

This paper presents a technique for mitigating two well‐known DAC non‐idealities in continuous‐time delta‐sigma modulators (CTDSMs), particularly in wide‐band and low over‐sampling‐ratio (OSR) cases. This technique employs a special digital‐to‐analog convertor (DAC) waveform, called modified return‐to‐zero (MRZ), to reduce the time uncertainty effect because of the jittered clock at the sampling time instances and eliminate the effect of inter‐symbol‐interference (ISI) which degrades the modulator performance, especially when non‐return‐to‐zero (NRZ) DAC waveform is chosen in the modulator design. A third‐order single‐bit CTDSM is designed based on the proposed technique and step‐by‐step design procedure at circuit and system levels, considering clock jitter and ISI, is explained. Circuit simulations in 180‐nm CMOS technology show that in the presence of circuit non‐idealities which generate jitter and asymmetrical rise and fall times in the DAC current pulse, signal‐to‐noise‐distortion‐ratio (SNDR) of the proposed modulator is higher than the conventional modulator with NRZ waveform by about 10 dB. In these simulations, clock jitter standard deviation is 0.3% of the sampling period (T_S) and the difference between fall/rise times in the DAC current pulse is 4%T_S. Simulated at 600‐MHz sampling frequency (f_S) with an oversampling ratio (OSR) of 24, SNDR figure of merit (FOM_SNDR) of the proposed modulator in 180‐nm CMOS is 300 fj/conversion. Copyright © 2016 John Wiley & Sons, Ltd.     

A 7.5‐μW 0.08‐mm2 single‐ended SC delta‐sigma ADC for acoustic sensor applications

This study presents an ultra‐low‐power, small‐size, 1‐bit, single‐ended, and switched‐capacitor (SC) delta‐sigma analog‐to‐digital converter (ADC) for wireless acoustic sensor nodes. This wireless sensor node has a delta‐sigma ADC that converts the sensed signal to a digital signal for convenient data processing and emphasizes the features of small size and low‐power consumption. The chip area of the delta‐sigma ADC is dominated by the capacitor; therefore, a novel common‐mode (CM) controlling technique with only transistors is proposed. This ADC achieves an extremely small size of 0.08 mm² in a 130‐nm CMOS process. The conventional operational transconductance amplifiers (OTAs) are replaced by inverters in the weak inversion region to achieve high power efficiency. At 4‐MHz sampling frequency and 0.7‐V power supply voltage, the delta‐sigma ADC achieves a 55.8‐dB signal‐to‐noise‐plus‐distortion ratio (SNDR) and a 298‐fJ/step figure‐of‐merit (FOM) in a signal bandwidth of 25 kHz, while consuming only 7.5 μW of power. Copyright © 2015 John Wiley & Sons, Ltd.     

A 0.6 V, 2.11 MHz, 62 dB SFDR active‐RC filter in 0.13µm CMOS process

Active‐RC biquad is proposed, which allows the DC level of the input of operational amplifier (op‐amp) to be different from that of the op‐amp output, enabling the low‐voltage operation. The proposed biquad realizes a second‐order transfer function with only one op‐amp, rendering even lower power consumption. By cascading two biquads, a 0.6 V fourth‐order filter is realized in a 0.13µm CMOS technology. While dissipating only 0.42 mW, the filter shows 2.11 MHz cut‐off frequency and 62 dB spurious‐free dynamic range. Copyright © 2008 John Wiley & Sons, Ltd.     

Design‐oriented model for power‐driven design optimization of SC‐ΣΔ modulators

A behavioral model for switched‐capacitors sigma‐delta modulators, suitable for power‐driven design, is presented. Because of the oversampling behavior of this kind of analog‐to‐digital converters, transistor‐level simulations are extremely time consuming. Thus, accurate behavioral models are mandatory in the preliminary design steps to cut the development time. However, when the power consumption of the modulator is pushed down to the absolute minimum level, second‐order effects affecting the settling behavior of the switched‐capacitor integrator must be taken into account. Furthermore, by means of an accurate noise model, based on a second‐order transfer function of the amplifier, a global power minimization is achieved, and the optimum partitioning between the switch and op‐amp noise is obtained. In spite of the improved accuracy, the proposed model requires only a few parameters of the amplifier in the integrator. This allows to easily link the model to an external set of circuit equations, to be derived for the specific amplifier used in the modulator. The model was used in the design of a third‐order modulator in an STM 90‐nm technology. The silicon samples exhibit an effective resolution of 15.2‐b with a 500‐Hz output rate, an oversampling ratio of 500, and a Schreier figure‐of‐merit of 162 dB, with a 38‐μW power consumption at 1.2‐V supply.     

High‐tuning‐range CMOS band‐pass IF filter based on a low‐Q cascaded biquad optimization technique

A design procedure for high‐order continuous‐time intermediate‐frequency band‐pass filters based on the cascade of low‐Q biquadratic cells is presented. The approach is well suited for integrated‐circuit fabrication, as it takes into account the maximum capacitance spread dictated by the available technology and maximum acceptable sensitivity to component variations. A trade‐off between noise and maximum linear range is also met. A novel, wide‐tuning‐range transconductor topology is also described. Based on these results, a 10‐pole band‐pass filter for a code division multiple‐access satellite receiver has been designed and tested. The filter provides tunable center frequency (f₀) from 10 to 70 MHz and exhibits a 28‐MHz bandwidth around f₀ = 70 MHz with more than 39‐dB attenuation at f₀/2 and 2f₀. Third‐order harmonic rejection is higher than 60 dB for a 1‐Vpp 70‐MHz input, and equivalent output noise is lower than 1 mV_rms. The circuit is fabricated in a 0.25‐µm complementary metal oxide semiconductor process, and the core consumes 12 mA from a 2.5‐V supply, offering the best current/pole ratio figure. The die area resulted to be 0.9 × 1.1 mm². Copyright © 2014 John Wiley & Sons, Ltd.     

A power‐area‐efficient, 3‐band, 2‐RX MIMO,TD‐LTE receiver with direct‐coupled ADC

In this work, a power‐area‐efficient, 3‐band, 2‐RX MIMO, and TD‐LTE (backward compatible with the HSPA+, HSUPA, HSDPA, and TD‐SCDMA) CMOS receiver is presented and implemented in 0.13‐μm CMOS technology. The continuous‐time delta‐sigma A/D converters (CT ?Σ ADCs) are directly coupled to the outputs of the transimpedance amplifiers, eliminating the need of analog anti‐aliasing filters between RX front‐end and ADCs in conventional structures. The strong adjacent channel interference without low‐pass filter attenuation is handled by proper gain control. A low‐power small‐area solution for excess loop delay compensation is implemented in the CT ?Σ ADC. At 20 MHz bandwidth, the CT ?Σ ADC achieves 66 dB dynamic range and 3.5 dB RX chip noise figure is measured. A maximum of 2.4 dB signal‐to‐noise ratio degradation is measured in all the adjacent channel selectivity (ACS) and blocking tests, demonstrating the effectiveness of the strategy against the low‐pass filter removal from the conventional architecture. The receiver dissipates a maximum of 171 mW at 2‐RX MIMO mode. To our best knowledge, it is the first research paper on the design of fully integrated commercial TD‐LTE receiver. Copyright © 2014 John Wiley & Sons, Ltd.     

A 0.7‐dB NF, +8.2‐dBm IIP3 CMOS low noise amplifier using frequency selective feedback

A CMOS amplifier employing the frequency selective feedback technique using a shunt feedback capacitor is designed and measured. The proposed amplifier can achieve a high IIP3 (input referred third‐order intercept point) by reducing the third‐ and second‐order nonlinearity contributions to the IMD3 (third‐order intermodulation distortion), which is accomplished using a capacitor as the frequency selective element. Also, the shunt feedback capacitor improves the noise performance of the amplifier. By applying the technique to a cascode LNA using 0.18‐µm CMOS technology, we obtain the NF of 0.7 dB, an IIP3 of +8.2 dBm, and a gain of 15.1 dB at 14.4 mW of power consumption at 900 MHz. Copyright © 2015 John Wiley & Sons, Ltd.     

0.5‐V bulk‐driven differential amplifier

A new 0.5‐V fully differential amplifier is proposed in this article. The structure incorporates a differential bulk‐driven voltage follower with conventional gate‐driven amplification stages. The bulk‐driven voltage follower presents differential gain equal to unity while suppressing the input common‐mode voltage. The amplifier operates at a supply voltage of less than 0.5 V, performing input transconductance almost equal to a gate transconductance and relatively high voltage gain without the need for gain boosting. The circuit was designed and simulated using a standard 0.18‐µm CMOS n‐well process. The low‐frequency gain of the amplifier was 56 dB, the unity gain bandwidth was approximately 3.2 MHz, the spot noise was 100 nV/√Hz at 100 kHz and the current consumption was 90 μΑ. Copyright © 2012 John Wiley & Sons, Ltd.     

0.3‐V bulk‐driven programmable gain amplifier in 0.18‐µm CMOS

A new solution for an ultra low voltage bulk‐driven programmable gain amplifier (PGA) is described in the paper. While implemented in a standard n‐well 0.18‐µm complementary metal–oxide–semiconductor (CMOS) process, the circuit operates from 0.3 V supply, and its voltage gain can be regulated from 0 to 18 dB with 6‐dB steps. At minimum gain, the PGA offers nearly rail‐to‐rail input/output swing and the input referred thermal noise of 2.37 μV/Hz^1/2, which results in a 63‐dB dynamic range (DR). Besides, the total power consumption is 96 nW, the signal bandwidth is 2.95 kHz at 5‐pF load capacitance and the third‐order input intercept point (IIP₃) is 1.62 V. The circuit performance was simulated with LTspice. Copyright © 2016 John Wiley & Sons, Ltd.     

A 120–420 MHz delay‐locked loop with multi‐band voltage‐controlled delay unit

A low‐jitter and low‐power dissipation delay‐locked loop (DLL) is presented. A proposed multi‐band voltage control delay unit (MVCDU) is employed to extend the operation frequency of the DLL by controlling the delay cell within the MVCDU. The jitter of DLL is reduced due to MVCDU's low sensitivity. The delay cell in the MVCDU employs a differential configuration to further reduce the noise impact from the fluctuation in the supply and ground voltage. The operating frequency of the proposed DLL ranges from 120 to 420 MHz. The proposed design has been fabricated in a TSMC 0.18µm CMOS process. The measured RMS and peak‐to‐peak jitters are 4.86 and 34.55 ps, respectively, at an operating frequency of 300 MHz. The power dissipation is below 14.85 mW at an operating frequency of 420 MHz. Copyright © 2010 John Wiley & Sons, Ltd.     

DC–3 GHz low‐noise,flat‐gain‐response,and high‐linearity amplifier

This paper describes the design, fabrication, and testing of a DC–3 GHz ultra‐wideband low‐noise amplifier (LNA) using Avago ATF‐54143 enhanced‐mode pseudomorphic high‐electron mobility transistor. Negative feedback network is introduced to ensure unconditional stability of the LNA over the full waveband. Simulation results show that the LNA provides a gain varying between 14.872 and 14.052 dB, a noise figure (NF) of less than 2.2 dB, and voltage standing wave ratios (VSWRs) approaching 2. A high simulated output third‐order intercept point (OIP₃) of >30.2 dBm is achieved. In contrast, in 1‐dB bandwidth of DC–3 GHz, the measured gain is nominal at 13.10 dB. The obtained NF changes in a small range of 2–2.178 dB, and the measured VSWRs are no more than 1.64, which are better than obtained from simulation results. At the same time, OIP₃ at 1, 2, and 3 GHz is 30.3, 29.13, and 29.34 dBm, respectively, while the output at the 1‐dB compression point (P _1dB ) is 15.43, 14.83, and 14.33 dBm, respectively. © 2016 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

Explicit design formulas for current‐mode leap‐frog OTA‐C filters and 300 MHz CMOS seventh‐order linear phase filter

The leap‐frog (LF) configuration is an important structure in analogue filter design. Voltage‐mode LF OTA‐C filters have recently been studied in the literature; however, general explicit formulas do not exist for current‐mode LF OTA‐C filters and there is also need for current‐mode LF‐based OTA‐C structures for realization of arbitrary transmission zeros. Three current‐mode OTA‐C structures are presented, including the basic LF structure and LF filters with an input distributor or an output summer. They can realize all‐pole characteristics and functions with arbitrary transmission zeros. Explicit design formulas are derived directly from these structures for the synthesis of, respectively, all‐pole and arbitrary zero filter characteristics of up to the sixth order. The filter structures are regular and the design formulas are straightforward to use. As an illustrative example, a 300 MHz seventh‐order linear phase low‐pass filter with zeros is presented. The filter is implemented using a fully differential linear operational transconductance amplifier (OTA) based on a source degeneration topology. Simulations in a standard TSMC 0.18µm CMOS process with 2.5 V power supply have shown that the cutoff frequency of the filter ranges from 260 to 320 MHz, group delay ripple is about 4.5% over the whole tuning range, noise of the filter is 420nA/√Hz, dynamic range is 66 dB and power consumption is 200 mW. Copyright © 2008 John Wiley & Sons, Ltd.     

Second‐order intermodulation cancelation and conversion‐gain enhancement techniques for CMOS active mixers

In this paper, two new techniques are proposed to improve the second‐order input intercept point (IIP2) and conversion‐gain in double‐balanced Gilbert‐cell complementary metal‐oxide semiconductor (CMOS) mixers. The proposed IIP2 improvement technique is based on canceling the common‐mode second‐order intermodulation (IM2) component at the output current of the transconductance stage. Additionally, the conversion‐gain is improved by increasing the fundamental component of the transconductance stage output current and creating a negative capacitance to cancel the parasitic capacitors. Moreover, in the proposed IM2 cancelation technique, by decreasing the bias current of the switching transistors, the flicker noise of the mixer is reduced. The proposed mixer has been designed with input frequency and output bandwidth equal to 2.4 GHz and 20 MHz, respectively. Spectre‐RF simulation results show that the proposed techniques simultaneously improve IIP2 and conversion‐gain by approximately 23.2 and 5.7 dB, respectively, in comparison with the conventional mixer with the same power consumption. Also, the noise figure (NF) at 20 kHz, where the flicker noise is dominant, is reduced by 4.9 dB. The average NF is increased nearly 0.9 dB, and the value of third‐order input intercept point (IIP3) is decreased approximately 1.8 dB. Copyright © 2014 John Wiley & Sons, Ltd.     

A 40 M–1000 MHz 77.2‐dB spurious free dynamic range CMOS RF variable gain amplifier for digital TV tuner ICs

In this paper, a 40 M–1000 MHz 77.2‐dB spurious free dynamic range (SFDR) CMOS RF variable gain amplifier (VGA) has been presented for digital TV tuner applications. The proposed RFVGA adopts a wideband operational‐amplifier‐based VGA and a wideband buffer with differential multiple gated transistor linearization method for wideband operation and high linearity. The SFDR of the proposed RFVGA is also analyzed in detail. Fabricated in a 0.13‐µm CMOS process, the RFVGA provides 31‐dB gain range with 1‐dB gain step, a minimum noise figure of 7.5 dB at a maximum gain of 27 dB, and maximum in‐band output‐referred third‐order intercept point of 27.7 dBm, while drawing an average current of 27.8 mA with a supply voltage of 3.3 V. The chip core area is 0.54 mm × 0.4 mm. Copyright © 2014 John Wiley & Sons, Ltd.     

Wide‐band aperture array using a four‐channel manifold‐type planar multiplexer and digital 2‐D IIR filterbank

Emerging wide‐band communications and spectrum‐sensing systems demand support for multiple electronically scanned beams while maintaining a frequency independent, constant far‐field beam width. Realizing existing phased‐array technology on a digital scale is computationally intensive. Moreover, digitizing wide‐band signals at Nyquist rate requires complex high‐speed analog‐to‐digital converters (ADCs), which is challenging for real developments driven by the current ADC technology. A low‐complexity alternative proposed in this paper is the use of radio‐frequency (RF) channelizers for spectrum division followed by sub‐sampling of the RF sub‐bands, which results in extensive reduction of the necessary ADC operative frequency. The RF‐channelized array signals are directionally filtered using 2‐D digital filterbanks. This mixed‐domain RF/digital aperture array allows sub‐sampling, without utilizing multi‐rate 2‐D systolic arrays, which are difficult to realize in practice. Simulated examples showing 14–19 dB of rejection of wide‐band interference and noise for a processed bandwidth of 1.6 GHz are demonstrated. The sampling rate is 400 MHz. The proposed VLSI hardware uses a single‐phase clock signal of 400 MHz. Prototype hardware realizations and measurement using 65‐nm Xilinx field‐programmable gate arrays, as well as Cadence RTL synthesis results including gate counts, area‐time complexity, and dynamic power consumption for a 45‐nm CMOS circuit operating at B _DC = 1.1 V, are presented. Copyright © 2016 John Wiley & Sons, Ltd.     

A reconfigurable high ultimate rejection inductorless band‐pass filter by the use of N‐path passive mixers

In this paper, a band‐pass filter with a tunable bandwidth and the center frequency is introduced, which employs N‐path and N × M‐path passive mixer structures, for multiband multistandard wireless receivers. The center frequency of the proposed filter is tunable from 0.1 to 1 GHz, while its bandwidth is also adjustable from 6% to 34% of the center frequency at 100 MHz. The passband ripple is reduced by applying a Miller compensation technique, resulting in a worst‐case ripple of only 1.6 dB over the entire tuning range. An additional eight‐path filter is also utilized at the input of the circuit, which highly improves the out‐of‐band rejection of the filter as well as its out‐of‐band linearity. The noise figure and the input return loss are, respectively, better than 5 and 10 dB, and depending on the desired center frequency, the total power consumption of the proposed filter varies from 41 to 70 mW.