A contribution to optimal lamp design in rapid thermal processing

Recent studies of wafer temperature control in rapid thermal processing systems have indicated that a multiring circularly symmetric lamp configuration with independent (multivariable) control of the power applied to each ring is likely to be more successful than the earlier lamp design approaches. An important issue in such multiring lamp systems is the optimal shaping of the output heat flux profile (HFP) of each ring to provide maximum controllability of the wafer temperature. In this paper we seek to optimize the ring HFP's via the lamp design parameters: ring positions and widths. We start by determining the heat loss profiles over the wafer surface for a variety of temperature setpoints and processing conditions. In order to maintain temperature uniformity across the wafer at a given setpoint, the lamp system should provide a compensating HFP. The total lamp HFP is the sum of the individual ring HFPs weighted by their respective applied powers. The HFP's are, in turn, functionally dependent on the lamp design parameters and this dependence can be measured through a calibration process. Therefore, the resulting optimization problem reduces to determining the lamp design parameters that result in lamp HFP's which best approximates the collection of the wafer heat loss profiles. Our method provides a practical technique for determining the optimal lamp design parameters     

Recent developments in rapid thermal processing

Rapid thermal annealing (RTA) with a short dwell time at maximum temperature is used with ion implantation to form shallow junctions and polycrystalline-Si gate electrodes in complementary, metal-oxide semiconductor (CMOS) Si processing. Wafers are heated by electric lamps or steady heat sources with rapid wafer transfer. Advanced methods use “spike anneals,” wherein high-temperature ramp rates are used for both heating and cooling while also minimizing the dwell time at peak temperature to nominally zero. The fast thermal cycles are required to reduce the undesirable effects of transient-enhanced diffusion (TED) and thermal deactivation of the dopants. Because junction profiles are sensitive to annealing temperature, the challenge in spike annealing is to maintain temperature uniformity across the wafer and repeatability from wafer to wafer. Multiple lamp systems use arrayed temperature sensors for individual control zones. Other methods rely on process chambers that are designed for uniform wafer heating. Generally, sophisticated techniques for accurate temperature measurement and control by emissivity-compensated infrared pyrometry are required because processed Si wafers exhibit appreciable variation in emissivity.     

A model for rapid thermal processing: achieving uniformity throughlamp control

A first-principles approach to the modeling of a rapid thermal processing (RTP) system to obtain temperature uniformity is described. RTP systems are single wafer and typically have a bank of heating lamps which can be individually controlled. Temperature uniformity across a wafer is difficult to obtain in RTP systems. A temperature gradient exists outward from the center of the wafer due to cooling for a uniform heat flux density on the surface of the wafer from the lamps. Experiments have shown that the nonuniform temperature of a wafer in an RTP system can be counteracted by adjusting the relative power of the individual lamps, which alters the heat flux density at the wafer. The model is composed of two components. The first predicts a wafer's temperature profile given the individual lamp powers. The second determines the relative lamp power necessary to achieve uniform temperature everywhere but at the outermost edge of the wafer (cooling at the edge is always present). The model has been verified experimentally by rapid thermal chemical vapor deposition of polycrystalline silicon with a prototype LEISK RTP system. The wafer temperature profile is inferred from the poly-Si thickness. Results showed a temperature uniformity of ±1%, an average absolute temperature variation of 5.5°C, and a worst-case absolute temperature variation of 6.5°C for several wafers processed at different temperatures     

Control of MMST RTP: repeatability, uniformity, and integration forflexible manufacturing [ICs]

A real-time multivariable strategy is used to control the uniformity and repeatability of wafer temperature in rapid thermal processing (RTP) semiconductor device manufacturing equipment. This strategy is based on a physical model of the process where the model parameters are estimated using an experimental design procedure. The internal model control (IMC) law design methodology is used to automatically compute the lamp powers to a multizone array of concentric heating zones to achieve wafer temperature uniformity. Control actions are made in response to real-time feedback information provided by temperature sensing, via pyrometry, at multiple points across the wafer. Several modules, including model-scheduling and antiovershoot, are coordinated with IMC to achieve temperature control specifications. The control strategy, originally developed for prototype equipment at Stanford University, is analyzed via the customization, integration, and performance on eight RTP reactors at Texas Instruments conducting thirteen different thermal fabrication operations of two sub-half-micron CMOS process technologies used in the the Microelectronics Manufacturing Science and Technology (MMST) program     

红外加热吸附反应外延系统的温度均匀性研究

为指导全新的吸附反应外延技术ARE(Absorption Reaction Epitaxy, ARE)设备红外热源的设计,分析在真空腔室中红外管阵列的热流分布。通过对灯管阵列灯管数量、灯管间距、灯阵与硅片之间距离等设计参数。采用COMSOL Multiphysics软件进行仿真模拟,研究了以红外为热源的设备腔室及硅片温度场分布情况,实测硅片表面温度及均匀性与仿真基本吻合。结果表明在保证源在硅片表面良好扩散效果的同时,当灯管阵列灯管长度为200 mm,数量为11根,间距10 mm,距离硅片15 mm时硅片表面温度不均匀度达到0.683%,满足红外加热吸附反应外延工艺需求,可为ARE红外热源及腔室设计提供参考。     

A novel illuminator design in a rapid thermal processor

The instantaneous insertion of an opaque shutter between the lamp arrays and the wafer in a rapid thermal processor can significantly increase the ramp-down rate from 90 to 400°C/s during the cooling period. This shutter can prevent the residual heating of lamp filament as well as the self-heating from the reflector due to the mirror image of the wafer. To compensate for the weak irradiation intensity close to the edge of the linear lamps, a multiplane reflector design is used to increase the uniformity of irradiation intensity in the direction along the linear lamps. The distance between the reflector plane and the linear lamp is designed to be smaller at the edge, as compared to the center, of the linear lamp. Together with two oblique reflectors at the ends of the linear lamps, a typical three-plane reflector design can increase the uniformity by 60% in a typical lamp configuration     

Decentralized control of wafer temperature for multizone rapidthermal processing systems

Decentralized control is shown through analysis and experimentation to be an appropriate strategy for wafer temperature control in certain multizone rapid thermal processing (RTP) systems. An input-output controllability analysis is conducted to illustrate that the direction associated with the reference command (set-point) corresponding to a spatially uniform temperature trajectory specification is nearly in alignment with the “most” controllable direction associated with the maximum singular value for a multiple concentric lamp configuration. Consequently, the control structure need not alter the directionality of the plant and, thus, can be achieved by a simple decentralized controller where the lamps are paired individually to sensors to achieve a multiloop structure where all interactions are not taken explicitly into account. This result is shown to produce acceptable performance even for an ill-conditioned plant since the directions corresponding to the smaller singular values are irrelevant to the uniform temperature control criteria. Moreover, straightforward nonmodel-based tuning of the controller is enabled due to the simplicity of the decentralized control structure     

Manufacturability of rapid-thermal oxidation of silicon: oxidethickness, oxide thickness variation, and system dependency

The dependence of oxide thickness, and oxide thickness variation within a wafer and wafer-to-wafer on process variables was studied in rapid-thermal processing systems that differed in chamber configuration and construction, incoherent light source, and pyrometers used for temperature measurement. Mechanisms for oxide growth and oxide thickness variation in rapid-thermal oxidation are discussed. Thermally induced stress, lamp configuration, and convective cooling affected the oxide thickness variation within a wafer. Wafer-to-wafer oxide thickness variation depended on the material of chamber construction, quartz or metal, and was related to residual heating for longer oxidations. For the same processing conditions, the oxide thickness was different for different systems, due to temperature error and a photonic component to rapid-thermal oxidation. Analysis of empirical oxide thickness models revealed a silicon orientation effect and a mechanism related to oxidant transport that was common to rapid-thermal oxidation in different systems     

Manufacturing issues related to RTP induced overlay errors in aglobal alignment stepper technology

The effect of rapid thermal processing on wafer distortion and overlay accuracy in global alignment photolithography in the fabrication of 0.85 μm CMOS Flash EPROM integrated circuits was studied. Both rapid thermal process parameters and system design (single and multi-lamp processors) were evaluated for their effect on overlay accuracy. It was found that a rapid thermal process (following contact etch and ion implantation) at set temperatures greater than or equal to 950°C resulted in interconnect metallization-to-contact overlay errors in excess of 1.0 μm across the wafer, which led to a 20% functional circuit yield loss. In the case of the single lamp processor, this misalignment was attributed to wafer distortion due to the temperature overshoot during the ramp step, which subsequently resulted in an across wafer temperature range of greater than 120°C. This temperature overshoot and nonuniformity was eliminated by reducing the ramp rate below 100°C/s. This ramp rate reduction, however, decreased the system wafer throughput, and required optimization to eliminate the overlay errors and minimize the effect on throughput. In this study, a 60°C/s ramp rate was found to be optimum. For the multi-lamp RTP system, the metal-to-contact overlay error was not observed. This was believed to be due to the design of the heating mechanism in the multi-lamp processor, which did not produce the large wafer temperature overshoot and nonuniformity that was observed in the single lamp processor     

Model reduction for optimization of rapid thermal chemical vapordeposition systems

A model of a three-zone rapid thermal chemical vapor deposition (RTCVD) system is developed to study the effects of spatial wafer temperature patterns on polysilicon deposition uniformity. A sequence of simulated runs is performed, varying the lamp power profiles so that different wafer temperature modes are excited. The dominant spatial wafer thermal modes are extracted via proper orthogonal decomposition and subsequently used as a set of trial functions to represent both the wafer temperature and deposition thickness. A collocation formulation of Galerkin's method is used to discretize the original modeling equations, giving a low-order model which loses little of the original, high order model's fidelity. We make use of the excellent predictive capabilities of the reduced model to optimize power inputs to the lamp banks to achieve a desired polysilicon deposition thickness at the end of a run with minimal deposition spatial nonuniformity. Since the results illustrate that the optimization procedure benefits from the use of the reduced-order model, our future goal is to integrate the model reduction methodology into real-time and run-to-run control algorithms. While developed in the context of optimizing a specific RTP process, the model reduction techniques presented in this paper are applicable to other materials processing systems     

Thermal modeling of a wafer in a rapid thermal processor

A model, using geometric optics, has been developed to calculate the illumination of a wafer inside a rapid thermal processor. The main parameters of the model are: the processing chamber geometry, the lamp number and location, the reflector characteristics, and the wafer temperature. Each incident light component, i.e., direct or reflected, is identified, its contribution to the illumination of the wafer is calculated through a 3D analytical model, and the corresponding contour maps are depicted. Then, the heat diffusion equation is numerically solved in two dimensions, and thermal maps of a Si wafer are given versus various experimental conditions, such as the effect of patterning the reflectors, of individually adjusting the electrical power applied to each lamp, and the impact of rotating the wafer or using crossed lamp banks. The latter method, while being easy to implement, is shown to give excellent thermal uniformity     

An In Situ Approach to Real-Time Spatial Control of Steady-State Wafer Temperature During Thermal Processing in Microlithography

We proposed an in situ method to control the steady-state wafer temperature uniformity during thermal processing in microlithography. Thermal processing of wafer in the microlithography sequence is conducted by the placement of the wafer on the bake-plate for a given period of time. A physical model of the thermal system is first developed by considering energy balances on the system. Next, by monitoring the bake-plate temperature and fitting the data into the model, the temperature of the wafer can be estimated and controlled in real-time. This is useful as production wafers usually do not have temperature sensors embedded on it, these bake-plates are usually calibrated based on test wafers with embedded sensors. However, as processes are subjected to process drifts, disturbances, and wafer warpages, real-time correction of the bake-plate temperatures to achieve uniform wafer temperature at steady state is not possible in current baking systems. Any correction is done based on run-to-run control techniques which depends on the sampling frequency of the wafers. Our approach is real-time and can correct for any variations in the desired steady-state wafer temperature. Experimental results demonstrate the feasibility of the approach     

Improvement in oxide thickness uniformity by repeated spikeoxidation

A new repeated spike oxidation (RSO) method used in a rapid thermal processing system was proposed in this work. Simulation results predict the temperature distribution on the wafer would be improved by this RSO method. We proposed that the improvement in wafer temperature uniformity is mainly caused by self-compensation in radiation heat absorption rate. Experimental data pointed out that the new method can produce more uniform oxide thickness than the conventional one under an intentionally created nonuniform heating environment     

Surface shape control of the workpiece in a double-spindle triple-workstation wafer grinder

Double-spindle triple-workstation(DSTW) ultra precision grinders are mainly used in production lines for manufacturing and back thinning large diameter(≥300 mm) silicon wafers for integrated circuits.It is important, but insufficiently studied,to control the wafer shape ground on a DSTW grinder by adjusting the inclination angles of the spindles and work tables.In this paper,the requirements of the inclination angle adjustment of the grinding spindles and work tables in DSTW wafer grinders are analyzed.A reasonable configuration of the grinding spindles and work tables in DSTW wafer grinders are proposed.Based on the proposed configuration,an adjustment method of the inclination angle of grinding spindles and work tables for DSTW wafer grinders is put forward. The mathematical models of wafer shape with the adjustment amount of inclination angles for both fine and rough grinding spindles are derived.The proposed grinder configuration and adjustment method will provide helpful instruction for DSTW wafer grinder design.     

Development of a hexagonal-shaped rapid thermal processor using avertical tube

A new RTP system concept is proposed and demonstrated. The system uses a vertical cylindrical quartz tube, while the wafer is placed horizontally. Linear halogen lamps are arranged in a hexagonal shape, and the hexagonal-shaped lamp groups are stacked vertically. Each lamp group is controlled independently, allowing a temperature difference within ±1.5°C to be achieved over a 6-in wafer in steady state. Oxidation under optimal power condition results in a 1.37% standard deviation for an average oxide thickness of 110.4 Å. The temperature nonuniformity during the transient has been greatly improved by using dynamic control. The convection loss in the system has been evaluated and its radial dependence is found to be smoother in this chamber than in a conventional rectangular chamber. The ray-tracing simulation in three-dimensional space did result in a better comprehension of the optically complex system. The system efficiency has turned out to be lower than in the case of a conventional rectangular chamber. A large portion of the radiation energy is absorbed by the reflectors. There is a strong side heating to the vertical edge of the wafer. Both are due to multiple horizontal reflections of the rays on the reflectors without hitting the wafer. The temperature profiles calculated from the ray-tracing results show an excellent agreement with experiments and confirm the accuracy of the ray-tracing simulation. The main advantages of this new system concept are its excellent temperature uniformity and the good accessibility of the wafer for technological treatments and in situ measurements     

Validation of a Rapid Thermal Processing model in steady-state

Rapid Thermal Processing (RTP) is widely used in advanced semiconductor manufacturing. The present work deals with the heat transfer from infrared lamps to the silicon wafer in a commercial RTP equipment. Both numerical and experimental approaches are considered. For numerical purposes, the RTP system is modelled in two (2D) and three dimensions (3D). Calculations are performed in steady-state. The computational fluid dynamics method (CFD) is used for solving the mass and heat conservation equations. The radiative heat transfer equation is solved with the Monte Carlo method. In order to validate these models, measurements of the wafer temperature are realized for five electric power values supplied to the infrared lamps. The experimental wafer temperature profiles are in good agreement with the numerically calculated ones. Moreover, a confrontation between the experimental temperature of the infrared lamp filaments evaluated from the Ohm law and the one used in the numerical calculations shows a good agreement with the 3D model. The slight difference observed with the 2D model is explained. So the numerical simulations are fully validated. Two relations are established in order to predict the power which has to be applied to infrared lamps to obtain the required wafer temperature.     

Coupled simulation of gas flow and heat transfer in an RTP-system with rotating wafer

In this study the concept of a lamp heated RTP-system with rotating wafer is considered. Using the fluid-flow-simulation software Phoenics-CVD, we investigated the cooling of the wafer by a process gas flow which is injected at room temperature into the hot process chamber through an inlet pipe in the side wall. In a full 3D-simulation of the gas flow and of the heat transfer in the gas and in the wafer the Navier–Stokes equations and the energy equation are solved. The radiative power consumption and the energy loss of the wafer have been modeled by the Stefan–Boltzmann law. Simulations without wafer rotation show a strong drop in the temperature distribution at the wafer near the inlet pipe. In contrast to this, simulations with rotation show an axisymmetric temperature distribution with a considerably smaller temperature gradient over the wafer. Comparisons with oxidation experiments showed good agreement with the simulation results.     

Temperature uniformity in RTP furnaces

The heat transfer to a wafer in a rapid thermal processing (RTP) furnace is simulated by an analytical/numerical model. The model includes radiation heat transfer to the wafer from the lamps, heat conduction within the wafer, and emission of radiation from the wafer. Geometric optics are used to predict the radiant heat flux distribution over the wafer. The predicted wafer surface temperature distribution is compared to measurements made in an RTP furnace for two different reflector geometries. Lamp configurations and the resulting irradiance required to produce a uniform wafer temperature are defined     

Photothermal Activation of Shallow Dopants Implanted in Silicon

Dopant impurities were implanted at high dose and low energy (10¹⁵ cm⁻², 0.5–2.2 keV) into double-side polished 200 mm diameter silicon wafers and electrically activated to form p–n junctions by 10 s anneals at temperatures of 1,025, 1,050, and 1,075°C by optical heating with tungsten incandescent lamps. Activation was studied for P, As, B, and BF₂ species implanted on one wafer side and for P and BF₂ implanted on both sides of the wafer. Measurements included electrical sheet resistance (Rs) and oxide film thickness. A heavily boron-doped wafer, which is optically opaque, was used as a hot shield to prevent direct exposure to lamp radiation on the adjacent side of the test wafer. Two wafers with opposing orientations with respect to the shield wafer were annealed for comparison of exposure to, or shielding from, direct lamp illumination. Differences in sheet resistance for the two wafer orientations ranged from 4% to 60%. n-Type dopants implanted in p-type wafers yielded higher Rs when the implanted surface was exposed to the lamps, as though the effective temperature had been reduced. p-Type dopants implanted in n-type wafers yielded lower Rs when the implanted surface was exposed to the lamps, as though the effective temperature had been increased. Effective temperature differences larger than 5°C, which were observed for the P, B, and BF₂ implants, exceeded experimental uncertainty in temperature control.     

Transient thermal analysis of sapphire wafers subjected to thermal shocks

Rapid heating and cooling are commonly encountered events in integrated circuit processing, which produce thermal shocks and consequent thermal stresses in wafers. The present paper studies the heat transfer in sapphire wafers during a thermal shock as well as the dependence of the wafer temperature on various process parameters. A three-dimensional finite-element model of a single sapphire wafer was developed to analyze the transient heat conduction in conjunction with the heat radiation and heat convection on the wafer surfaces. A silicon wafer was also investigated, for comparison. It was found that the rapid thermal loading leads to a parabolic radial temperature distribution, which induces thermal stresses even if the wafer is not mechanically restrained. The study predicted that for sapphire wafers the maximum furnace temperature of 800 /spl deg/C should be held for two hours in order to get a uniform temperature throughout the wafer.