Low-voltage, low-power BiCMOS digital circuits

A new BiCMOS buffer circuit, for low-voltage, low-power environment, is presented. The circuit is based on the deep submicron technology and utilizes the parasitic bipolar transistors associated with the CMOS structure. The analysis, simulations and SPICE results confirm the functionality of the circuit and its speed and voltage swing superiority, compared with conventional BiCMOS circuits at low supply voltages     

Low-voltage electronics for the stimulation of biological neuralnetworks using fully complementary BiCMOS circuits

This paper describes low-voltage neural stimulating circuitry developed using fully complementary BiCMOS (FC-BiCMOS) process technology for providing charge-balanced bipolar stimulating currents to tissue in the central nervous system. The electronics features an FC-BiCMOS buffer, a 7-b biphasic current-output digital-to-analog converter, a 14-b frequency divider, a nonoverlapping two-phase clock generator, and an auto timeout safety scheme while driving any two of eight selected sites from 0 to ±126 μA with ±2 μA resolution. The circuit area is 1.6 mm² in 3-μm features. Micropower circuit techniques allow the probe to dissipate <10 μW in standby and operate at 10 MHz from ±2.5 V supplies     

Novel circuits for high speed ROMs

Novel approaches in circuit design, such as overlap timing without precharge, complementary ROM cells with two access lines, and overall chain-delay optimization, greatly increase the operational speed of ROMs. The innovative circuits fabricated with an advanced CMOS/SOS process resulted in an experimental 18-kbit (2K/spl times/9) look-up ROM performing a cycle time of 4 ns, a silicon area of 7.2 kmil/SUP 2/ and a radiation hardness of >10/SUP 5/ rad(Si). The overlap timing can multiply the address and data change rate without reducing the overall chain delay. The utilization of complementary ROM cells increases data processing speed, noise margin, and radiation hardness. The overall chain delay is greatly reduced by finding the minimum of a device size dependent time function. The complementary cell features a size of 12/spl times/17.2 /spl mu/m, shared contacts, and tantalum polycide access lines. The circuits discussed here can be used for any high-speed memory design, although the demonstration vehicle is a CMOS/SOS ROM.     

Dynamic latch for high speed GaAs domino circuits

A latch for use with GaAs domino logic gates is presented. A hybrid of a GaAs domino logic gate and a two-phase dynamic FET logic gate, the latch stores data during the precharge phase of domino logic operation. It enables the use of domino logic in large scale systems without the need for interfacing with power consumptive static latches. It is implemented with depletion mode MESFETs and dissipates 0.8 mW.<>     

光纤通信高速电路研究进展

总结了国内外光纤通信用高速电路研究最新进展,并详细讨论了其中的关键器件－光调制器驱动电路。     

Air stable complementary polymer circuits fabricated in ambient condition by inkjet printing

Air stable complementary polymer inverters were demonstrated by inkjet printing of both top-gate electrodes and the semiconductors in ambient conditions. The p-type and n-type polymer semiconductors were also thermally annealed in ambient conditions after printing. The good performance of circuits in ambient condition shows that the transistors are not only air-stable in term of ambient humidity and oxygen, but also inert to ion migration through dielectrics from the printed gate. The result obtained here has further confirmed the feasibility of fabrication of low-cost polymer complementary circuits in a practical environment.     

Planar normally-off GaAs JFET for high speed logic circuits

Normally-off JFETs with 1.3 ?m-long gates were fabricated by selective double ion implantation for the n and n+ regions and selective Zn diffusion for the p-gate area. A JFET with a 10 ?m-wide gate had a transconductance of 2 mS in average and a high value of 3 mS. A 15 stage ring oscillator made of resistively loaded DCFLs showed the minimum delay time of 45 ps, the shortest value obtained based on optical lithography. The minimum power-delay product was 3.8 fJ with a delay time of 83 ps.     

Ultra-thin flexible screen printed rechargeable polymer battery for wearable electronic applications

This research has demonstrated how an ultra-thin rechargeable battery technology has been fabricated using screen printing technology. The screen printing process enabled the sequential deposition of current collector, electrode and separator/electrolyte materials onto a polyethylene terephthalate (PET) substrate in order to form both flexible and rechargeable electrodes for a battery application. The anode and cathode fabricated were based on the conducting poly (3,4-ethylenedioxythiophen): poly (styrene sulfonate) (PEDOT: PSS) and polyethyleneimine (PEI) which were combined to form the electrodes. The difference in the oxidation level between the two electrodes produced an open circuit voltage of 0.60 V and displayed a practical specific capacity of 5.5 mAh g⁻¹. The battery developed had an active surface area of 400 mm² and a device thickness of 440 μm. The chemistry developed during this study displayed long-term cycling potential and proves the stability of the cells for continued usage. This technology has direct uses in future personal wearable electronic devices.     

Coupling and crosstalk between high speed interconnects inultralarge scale integrated circuits

The advent of sophisticated lithographic techniques has made it possible to fabricate densely packed ultra-large-scale-integrated (ULSI) circuits. In these chips, interconnect lines are so narrow and spaced in such close proximity that signal from one line could easily get coupled to another, causing interference and crosstalk. A general theory to model coupling between optical interconnects (waveguides) and quantum-mechanical coupling between narrow and very closely spaced silicide interconnects embedded in dielectrics (SiO₂) is presented     

BiCMOS circuits for high speed current mode D/A converters

A new BiCMOS current cell and a BiCMOS current switch for high speed, self-calibrating, current-steering D/A converters are described. The BiCMOS current cell can be realized in a BiCMOS process or in a conventional CMOS process using a substrate PNP transistor, while the BiCMOS current switch is intended for implementation in a BiCMOS process. The performance of these circuits has been demonstrated in 0.8 μm BiCMOS and 1.2-μm CMOS technologies. A detailed noise analysis of the BiCMOS current cell indicates that noise during the calibration phase limits its relative accuracy to about 150 ppm. This is substantiated by measured results which show a relative matching of about 100-150 ppm, which is the equivalent of about 13 b performance. Measurement results also indicate that the absolute accuracy of the BiCMOS current cell is better than 0.5% over the designed current range, which is better than that of previously reported designs. Test results for the BiCMOS current switch indicate that a 10-90% switching time of 0.9 ns has been achieved. Furthermore, the switching time of the new BiCMOS switch is very insensitive to current level and input waveform compared to conventional CMOS switches. A 4-b D/A converter based on these components has been fabricated, and test results have demonstrated that it is functional. This DAC will be used as the internal DAC of a ΣΔ modulator for over-sampled video and digital radio applications     

Low-voltage, high dB-linear, exponential V-V converter

A new idea is proposed to make use of the disadvantages at low-voltage operations to widen the output dynamic range and the input swing of the exponential voltage-to-voltage circuit with differential input, at low-voltage low-power applications. The pseudo-exponential function is used to realise the exponential characteristic. Based on 0.25 /spl mu/m CMOS technology, simulations show a 16 dB linear improvement of the output voltage range while dissipating less than 0.2 mW from 1.25 V supply voltage.     

Fully-printed,all-polymer,bendable and highly transparent complementary logic circuits

In this contribution we show a simple approach for the development of all-polymer based complementary logic circuits fabricated by printing on plastic, at low temperature and in ambient conditions. This is achieved by patterning, with a bottom-up approach, solely synthetic carbon-based materials, thus incorporating earth-abundant elements and enabling in perspective the recycling – a critical aspect for low-cost, disposable electronics. Though very simple, the approach leads to logic stages with a delay down to 30 μs, the shortest reported to date for all-polymer circuits, where each single component has been printed. Moreover, our circuits combine bendability and high transparency, favoring the adoption in several innovative applications for portable and wearable large-area electronics.     

高速超宽带脉冲检测电路的设计

在介绍了一种基于TH-PPM调制方式的并行检测接收机方案的基础上,结合UWB脉冲信号的时域特征提出并实现了一种结构简单、性能稳定的脉冲能量检测电路.实验结果表明该电路可在100Mb/s的高传输速率情况下取得较好的超宽带信号检测效果.     

12.5 Gbps 1:16 DEMUX IC with high speed synchronizing circuits

A 12.5 Gbps 1:16 demultiplexer(DEMUX) integrated circuit is presented for multi-channel high-speed data transmission.A novel high-speed synchronizing technique is proposed and integrated in this DEMUX chip. Compared with conventional synchronizing techniques,the proposed method largely simplifies the system configuration. The experimental result demonstrates that the proposed circuit is effective in two-channel synchronization under a clock frequency of 12.5 GHz.The circuit is realized using 1μm GaAs heteroj unction bipolar transistor technology with die area of 2.3×2.3 mm~2.     

具有高速同步功能的12.5Gbps 1:16 解复用器集成电路

A 12.5 Gbps 1:16 demultiplexer (DEMUX) integrated circuit is presented for multi-channel high-speed data transmission. A novel high-speed synchronizing technique is proposed and integrated in this DEMUX chip. Compared with conventional synchronizing techniques, the proposed method largely simplifies the system configuration. The experimental result demonstrates that the proposed circuit is effective in two-channel synchronization under a clock frequency of 12.5 GHz. The circuit is realized using 1 μ m GaAs heterojunction bipolar transistor technology with die area of 2.3 × 2.3 mm².     

高速数字电路的传输线效应分析

在高速数字电路中,传输线效应可以引起信号的过冲、下冲及振铃现象。运用传输线的有关理论可以清晰地解释工程设计中遇到的这些信号畸变现象的原因,并且能够得到几种保持信号完整性的方法。在设计中利用这些办法可以得到满意的结果。深刻理解传输线理论的有关概念,有利于把工作中积累的一些经验上升为理性认识,从而提高设计水平。     

中国电子产业世界一道亮色

今年1月下旬，全国信息产业会议工作会议在北京召开，信息产业部部长吴基传作了报告，摘要如下：2002年，全国信息产业增加值占国内生产总值的比重由1997年的2.3%提高到5.7%，电话用户总数跃居世界第一位，电子信息产品制造产业规模跃居世界第三位，互联网上网人数跃居世界第二位。全年宏观调控目标全面完成，为实现“十五”计划奠定了坚实的基础。信息产业为我国的信息化、工业化和现代化建设做出了突出的贡献，各项工作取得了显著的成绩。2002年业绩辉煌通信业建成世界第一大电话网经过多年的发展，一个覆盖全国、连通世界、技术先进、业…     

基于OrCAD电路设计软件的高频电子线路仿真分析

本文基于OrCAD/Pspice电子线路计算机辅助分析设计软件以实现高频电子线路的综合电路分析仿真为目的,针对回路使用的信号频率比较高,电路实现的功能多、结构复杂,造成OrCAD设计软件在仿真过程时运算量大,电路调试过程变得复杂、电路的元器件参量优化难度大.通过采用复杂电路的仿真调试关联优化的方法对变容二极管调频与功率放大及发射电路的仿真过程进行分析,仿真效果表明,采用关联优化方法能有效提高优化设计效率。     

基于USB2．0的高速高精度数据采集系统模拟电路设计

为了满足数据采集系统对输入信号的高速高精度采集,本文重点介绍了模拟前端放大器件选型以及模拟前端信号调理电路的设计,深入的研究了影响数据采集精度的关键技术,给出了ADC电路设计中提高和保持转换精度的要点。系统已经设计完成,并已成功地应用到型号工程中。