An accurate digital low-pass filter for transmission line protection

The paper presents a procedure for designing, testing and evaluating digital low-pass filters for the removal of high-frequency transients from transmission line short-circuit voltage and current waveforms, as is required for certain digital distance relays and may be useful in other similar applications. The procedure is based on the ‘trapezoidal’ type of low-pass digital filter which has characteristics that enable low-order digital filters to be achieved. Criteria for the design and optimization of such filters in the foregoing type of application are also presented.     

基于离散Gabor变换和增量Wiener滤波器的冲击电压波形重构算法研究

分析了冲击电压经过数字化冲击测量系统后被测波形产生畸变的原因,讨论了因量化噪声造成波形反卷积重构的病态性.提出了一种基于离散Gabor变换和增量维纳滤波器的冲击电压波形重构方法,对IEC1083-2TDG波形计算结果表明该方法可以有效实现冲击电压数字化测量波形复原,具有较高的准确度和稳定性.     

Zero-Phase Filtering for Lightning Impulse Evaluation: A K-factor Filter for the Revision of IEC60060-1 and -2

The next revision of the international standard for high-voltage measurement techniques, IEC 60060-1, has been planned to include a new method for evaluating the parameters associated with lightning impulse voltages. This would be a significant improvement on the loosely defined existing method which is, in part, reliant on operator judgment and would ensure that a single approach is adopted worldwide to determine peak voltage, front, and tail times, realizing standardization in measured parameters across all laboratories. Central to the proposed method is the use of a K-factor to attenuate oscillations and overshoots that can occur with practical generation of impulse voltages for testing on high-voltage equipment. It is proposed that a digital filter that matches the K-factor gain characteristic be implemented and used for this purpose. To date, causal filter designs have been implemented and assessed. This paper is concerned with the potential application of a noncausal digital filter design to emulate the K-factor. The approach has several advantages; the resulting design is only second order, it can be designed without using optimization algorithms, it is a zero-phase design and it matches the K-factor almost perfectly. Parameter estimation using waveforms from the IEC 61083-2 test data generator and experimental impulse voltages has been undertaken and obtained results show that the zero-phase filter is the ideal digital representation of the proposed K-factor. The effect of evaluating parameters by the proposed method is compared to mean-curve fitting and the challenge of effective front-time evaluation is discussed.     

Selective digital filters with quadratic phase

A method for design of a new class of digital infinite impulse response filters realized as parallel connection of two all‐pass filters is presented in this paper. A new approach to approximation of quadratic phase of all‐pass filter at all frequencies is given. Chosen parallel structure offers opportunity for realization of filters with arbitrary shape phase. The presented algorithm is based on all‐pass filter phase approximation. Phases of both all‐pass filters approximate ideal quadratic phase in minimax sense at all frequencies. Such filters can be applied for chirp signal compression or expansion. Magnitude characteristic of described filters is very selective and elliptic‐like. Obtained filters are compared with elliptic filter and group delay corrector in cascade. For the same specifications, much better results are achieved by the proposed filters. Parallel connection of all‐pass filters introduces lower signal delay, and for a given maximal phase, approximation error demands less complex network. Examples to illustrate the proposed method are given. Copyright © 2016 John Wiley & Sons, Ltd.     

一种数字化冲击电压波形重构新算法

为减少数字化冲击测量系统的测量误差,分析了冲击电压经数字化冲击测量系统后被测波形产生畸变的原因;提出了一种利用离散Gabor变换展开去噪与增量维纳滤波器相结合的冲击电压波形重构算法。IEC1083-2测试数据发生器产生的波形信号的研究表明,该法可有效去除噪声,波形复原准确度和稳定性较高。     

IIR filter scaling for real-time signal processing

Students generally have difficulty implementing infinite impulse response filters (IIR) using fixed-point arithmetic. Most of the trouble is with amplitude scaling the filter and representing the coefficients in the fixed-point format. The authors present a systematic procedure for scaling a second-order IIR filter which is used as the basic building block of higher-order filters. A simple simulation program is used to estimate the size of the signals at the summing nodes of the filter section. Once the estimates are known, the filter section can he reliably scaled. The procedure is clarified by implementing a second-order resonant filter on a digital signal processor: the TMS320C25     

一种用于继电保护测试装置的闭环控制正弦基准生成系统

针对目前继电保护测试装置在应用中实现小型化、智能化的需求,设计出了基于FPGA的闭环控制正弦信号基准生成系统。该系统采用FPGA作为片上系统,在芯片内集成了数字滤波器和PID控制器。设计出了低通和高通两种数字滤波器的原型,并通过递推算法在片内实现其功能。分析了解调中的幅值相位分离理论,并给出了相位环路和幅度环路的闭环控制框图,推导了控制器的离散表达式。实验结果表明,所设计的信号处理系统在输出信号幅值大于5V时,误差小于万分之一。当输出幅值信号较小时,相比开环系统,采用闭环控制系统的输出精度得到了明显的改善。在FPGA片内实现闭环正弦生成系统,为继电保护测试装置在保证精度的前提下提高系统集成度,提供了一种全新的设计思路和实现方法。     

Systolic digital filters with reduced latency—serial implementation

Schemes that implement finite impulse response (FIR) and infinite impulse response (IIR) digital filters when bit-serial or digit-serial arithmetic is used are proposed in this paper. The main objective is to obtain reduced latency (minimal latency at the word level) of the filter outputs while maintaining the word rate. Existing schemes (systolic or not) for filters are transferred down to the digit level and regular structures systolic at the bit or digit level are proposed. First a modified representation of a digital filter signal flow-graph appropriate for bit-serial or digit-serial arithmetic is presented. Next we show how the resulting flow-graph can be transformed to lead directly to a systolic implementation at the bit or word level. We aim towards minimizing the latency of the filter response. For this reason we work with bidirectional signal flow-graphs that lead to systolic arrays where data and partial results move in opposite directions, otherwise called two-way pipeline systolic arrays. The multipliers that are used in the implementation of the filters must have low latency themselves. For this reason they have the same two-way pipeline structure. In order to maintain the data word rate, the full-bit output of a multiplier must be rounded by a number of bits equal to the length of the data words. We propose a composite bit-serial multiplier that performs this rounding while preserving low latency and incorporate it in schemes for direct implementation of low-latency high-throughput systolic arrays for FIR and IIR digital filters. These schemes for bit-serial multipliers and filters are also extended to digit-serial arithmetic.     

Digital recording techniques for electrical insulation measurements

The problems of measuring the characteristics of transient voltage and current waveforms occurring in high-voltage power systems are discussed, and the analog recorders that have been used in the past are reviewed. The theory of operation of digital recorders is described, and sources of recording errors are examined. Applications of digital oscilloscopes to measuring switching surges and partial discharges and to high-voltage impulse testing are discussed     

Digital laguerre filters

This paper presents the theory and a time domain synthesis procedure for a class of orthogonal digital filters. These filters are derived from discrete Laguerre polynomials and in the case of exact representation possess an infinitely long structure whilst exhibiting an infinite impulse response. In practice the desired impulse response of a filter to be synthesized is truncated in time whilst speed and economic considerations impose a constraint on its length. By the nature of these filters, very few stages usually suffice to yield excellent fidelity in most practical cases. The filters, whose cascaded stages are eminently suited to multiplexing, are inherently stable. A computer-aided design algorithm using a Fibonacci search algorithm is presented for optimizing the practical case having finite length and span. Two examples illustrate the procedure.     

LabVIEW数字调制误差测量模块的改进

本文首先介绍了数字调制误差的概念,给出了LabVIEW调制工具包中PSK数字调制误差测量模块（MT Measure PSK Quadrature Impairments）工作原理,然后以EVM测量为例分析了测量误差,根据数字调制解调过程中所使用的数字脉冲成形滤波器与匹配滤波器实现方法,得到测量误差是由数字滤波器引入的截断误差导致的结论。根据误差分析结果,本文建立了新的数字调制误差测量模块,新模块的参考信号生成过程使用与调制解调过程相同的滤波器环节,引入相同的截断误差,从而抵消被测信号在数字调制解调过程存在的滤波器截断误差。最后通过LabVIEW仿真测量实验,证明了新模块提高了测量精度。     

结合中值滤波的介损数字化算法

针对介损测量用的电压和泄漏电流信号存在脉冲干扰影响介损测量准确性的问题,提出了使用中值滤波算法对信号进行滤波,然后对滤波后信号使用数字化算法计算介损的算法。针对普通中值滤波算法使信号长度减少的情况,提出了一种不改变滤波后信号长度的中值滤波算法。对含脉冲噪声信号的滤波和滤波后信号的计算结果表明,提出的算法能有效抑制信号中的脉冲噪声,滤波后信号计算所得介损的精确度均要高于滤波前。同时,使用改进中值滤波算法避免了因为信号长度变短给介损测量造成误差的可能性。     

一种改进的去除数字图像脉冲噪声方法

提出了一种新的高效的数字图像脉冲噪声检测和去噪方法.该方法主要由2部分组成:噪声的检测和噪声的去除.检测阶段主要的任务是将图像信号点和噪声点区分开来,噪声去除阶段的主要任务是对检测到的噪声进行滤波处理.用一种改进的中值滤波器和均值滤波器来去除检测到的噪声点.实验结果表明该方法与其他方法相比,在噪声去除和图像细节保护方面...     

Application of step‐response test for evaluation of uncertainty of standard measuring system for lightning‐impulse high voltage

In evaluating the uncertainty of the standard measuring system for lightning‐impulse high voltages, which is composed of a standard voltage divider, a digital recorder, and calibrators, step‐response tests of the standard voltage divider may be useful. In this paper, a convolution algorithm is employed to calculate the output impulse voltage waveforms from measured step‐response waveforms. The uncertainties of peak‐value measurement due to the influence of the nominal epoch, uncertainty of the peak‐value measurement due to dispersion of the AC scale factor, and uncertainty of the virtual front‐time measurement due to long‐term stability are evaluated. Furthermore, the error of the virtual front time of the output waveforms is discussed. The front part of the step‐response waveform, t≤ T₃₀%, does not influence the error of the virtual front time. Therefore, for the standard voltage divider, the step‐response parameters, that is, the experimental response time, partial response time, settling time, and overshoot, have almost nothing to do with the error of the virtual front time. © 2012 Wiley Periodicals, Inc. Electr Eng Jpn, 180(2): 24–32, 2012; Published online in Wiley Online Library ( wileyonlinelibrary.com ). DOI 10.1002/eej.21279     

Discretization of analogue filters via H∞ model-matching theory

Approximation of analogue filters by digital filters is performed using H∞ model-matching theory. In this approach the input signal is assumed to belong to a frequency-weighted ball in the Lebesgue space L₂ of continuous square-integrable signals and a digital filter is designed so as to minimize the norm of the worst error between the outputs of the digital and analogue filters. An analysis of the frequency response shows that if the set of input signals is sufficiently band-limited, the procedure corresponds to the minimization of a weighted minimax frequency response error criterion. Numerical examples show that the approach offers an efficient procedure for discretizing general multivariable systems.     

Digital filter model of power transmission line

An analytical formulation for power system electromagnetic transient analysis has been developed recently in which successive transformations are made between the frequency domain, the z plane, and the time domain. In this sequence, transmission line forward impulse responses and surge impedence functions formed in the z plane are similar to response functions typical of digital filters. From this starting point, the equations of a multiconductor power transmission line are given in scattering form. It is then shown how these lead to a digital filter model, which draws on the now standard canonical realizations of digital filter design. Procedures are given by which the z-plane functions of this filter representation are related to power transmission line parameter sets over the range of frequencies relevant to power system electromagnetic transients. The paper then considers two application areas of the filter models derived.     

Application of direct synthesis techniques to customize filters with complex frequency response

Recently, direct synthesis techniques (DSTs) have been presented for filter synthesis. Unlike conventional synthesis techniques, DSTs derive the filtering polynomials of the filters to be synthesized directly in their own frequency domain. These filtering polynomials are real coefficient so that they might find applications in various fields. Furthermore, DSTs might be used to customize filters with a more complex frequency response, such as asymmetric frequency response or multi‐band frequency response. In this paper, DSTs are compared with some well‐known filter synthesis techniques. Then, the application of DSTs in the design of lumped‐element LC filters, distributed‐element filters, active RC filters, and infinite impulse response digital filters with complex frequency response is discussed. Some examples are presented for demonstration. Copyright © 2015 John Wiley & Sons, Ltd.     

Optimal design of symmetric fractional delay filter using firefly algorithm

A fractional delay filter is used to increase the accuracy, preciseness, time synchronization, and stability of signal processing system. However, designing a fractional delay filter for a specified delay, without affecting spectral characteristics of the signal is challenging because of nondifferentiability and multimodal nature of its objective function. In this paper, a more accurate design technique has been proposed for designing fractional delay filters, based on a recently developed firefly algorithm and its improved version. The designed filters offer variable fractional delay. A novel symmetric structure of implementation has been used to design filters. The efficacy of the proposed technique is evaluated by considering a filter design example. The performance of the proposed technique is compared with the other exiting algorithm. The comparative analysis of finite impulse response (FIR) fractional delay filter design proves that the proposed algorithm has a smaller design error and an implementation complexity than the other reported existing algorithms. In addition to this, the designed FIR fractional delay filter is implemented on Xilinx Virtex-7 for experimental validation.     

复杂波形剩余电流保护器的设计

采用磁调制式电流互感器法对含有脉动直流分量、甚至含有平滑直流分量的复杂波形剩余电流进行检测,同时采用基于IIR数字低通滤波器对采集的信号进行滤波处理,提高了滤波精度。基于浮点型DSP TMS320F28335进行软件设计,实现复杂波形剩余电流的精确采样分析,对复杂波形剩余电流检测满足标准要求。