一种ARGB数据无损压缩解压算法的FPGA设计

提出了一种ARGB数据的无损压缩优化算法以及FPGA实现方法。为了避免对整个文件的解压和压缩,采用了Deflate算法的相关方法对图像按块进行压缩和解压,极大提高了存储器的访问效率。利用了Deflate算法对小块进行压缩,发挥了Deflate中LZ77压缩的Huffman压缩技术来优化压缩算法。通过VIVADO HLS将算法实现成FPGA电路,采用多张图片进行了实际应用,证实了算法的有效性,并分析了其功耗和时序信息。     

Adaptive and dynamic multi-grouping scheme for absolute moment block truncation coding

Image compression technique is widely used in multimedia signal processing. As a conventional lossy compression technique, block truncation coding (BTC) deserves further improvements to enhance its performance of compression. The improvements of BTC mainly focus on: 1) enhancing the quality of reconstructed image and 2) decreasing the bit rate. In this paper, an adaptive and dynamic multi-grouping scheme is proposed for the absolute moment block truncation coding (AMBTC), which is mainly based on an optimized grouping mechanism with the adaptive threshold setting according to the complexity of image blocks. Besides, the values of the reconstruction levels are replaced by their compressed difference values in order to decrease the bit rate. Experimental results demonstrate that the proposed scheme can enhance the compression performance of AMBTC effectively.

     

64-bit Block ciphers: hardware implementations and comparison analysis

A performance comparison for the 64-bit block cipher (Triple-DES, IDEA, CAST-128, MISTY1, and KHAZAD) FPGA hardware implementations is given in this paper. All these ciphers are under consideration from the ISO/IEC 18033-3 standard in order to provide an international encryption standard for the 64-bit block ciphers. Two basic architectures are implemented for each cipher. For the non-feedback cipher modes, the pipelined technique between the rounds is used, and the achieved throughput ranges from 3.0 Gbps for IDEA to 6.9 Gbps for Triple-DES. For feedback ciphers modes, the basic iterative architecture is considered and the achieved throughput ranges from 115 Mbps for Triple-DES to 462 Mbps for KHAZAD. The throughput, throughput per slice, latency, and area requirement results are provided for all the ciphers implementations. Our study is an effort to determine the most suitable algorithm for hardware implementation with FPGA devices.     

Lossless data hiding for color images based on block truncation coding

In this paper, we present a novel, reversible steganographic method, which can reconstruct an original image effectively after extracting the embedded secret data. The proposed reversible hiding method aims at BTC (block truncation coding)-compressed color images. Conventionally, each block of a color image compressed by BTC requires three bitmaps and three pairs of quantization levels for reconstruction. In order to improve the compression rate, a genetic algorithm (GA) is applied to find an approximate optimal common bitmap to replace the original three. The secret data then are embedded in the common bitmap and the quantization levels of each block use the properties of side matching and the order of these quantization levels to achieve reversibility. The experimental results demonstrate that the proposed method is practical for BTC-compressed color images and can embed more than three bits in each BTC-encoded block on average.     

Grayscale image formats for edge detection and for its FPGA implementation

The aim of this paper is analysis of image formats used for FPGA implementation of edge detection methods. All cameras used in FPGA applications give Raw RGB output video format, some cameras provide also YUV, YCbCr, RGB565/555 or compressed JPEG formats. If the FPGA circuit has limited number of configurable logic blocks (CLB) the JPEG format seems to be good solution how to increase the size of the processed image. On the other hand, using an image with lossy compression can more or less affect the overall result of image processing. The first goal of this paper is to show whether lossy image compression can affect the quality of edge detection. The results presented in this article show that lossy image compression can impair the efficiency of edge detection by up to six percent. Many researchers have proposed FPGA implementation of some edge detection methods. Usually their first step is RGB to grayscale conversion because they use edge detection methods for grayscale images. The second goal of this paper is to show that a performance of FPGA implementation can be improved if YUV, YCbCr or Raw RGB camera output formats are used instead of RGB format.     

Real time fractal image coder based on characteristic vector matching

Fractal coding algorithm has many applications including image compression. In this paper a classification scheme is presented which allows the hardware implementation of the fractal coder. High speed and low power consumption are the goal of the suggested design. The introduced method is based on binary classification of domain and range blocks. The proposed technique increases the processing speed and reduces the power consumption while the qualities of the reconstructed images are comparable with those of the available software techniques. In order to show the functionality of the proposed algorithm, the architecture was implemented on a FPGA chip. The application of the proposed hardware is shown in image compression. The resulted compression ratios, PSNR error, gate count, compression speed and power consumption are compared with the existing designs. Other applications of the proposed design are feasible in certain fields such as mass–volume database coding and also in video coder’s block matching schemes.     

An oblivious fragile watermarking scheme for images utilizing edge transitions in BTC bitmaps

As one of the famous block-based image coding schemes,block truncation coding(BTC) has been also applied in digital watermarking.Previous BTC-based watermarking or hiding schemes usually embed secret data by modifying the BTC encoding stage or BTC-compressed data,obtaining the watermarked image with poorer quality than the BTC-compressed version.This paper presents a new oblivious image watermarking scheme by exploiting BTC bitmaps.Unlike the traditional schemes,our approach does not really perform the BTC compression on images during the embedding process but utilizes the parity of the number of horizontal edge transitions in each BTC bitmap to guide the watermark embedding and extraction processes.The embedding process starts by partitioning the original cover image into non-overlapping 4×4 blocks and performing BTC on each block to obtain its BTC bitmap.One watermark bit is embedded in each block by modifying at most three pixel values in the block to make sure that the parity of the number of horizontal edge transitions in the bitmap of the modified block is equal to the embedded watermark bit.In the extraction stage,the suspicious image is first partitioned into non-overlapping 4×4 blocks and BTC is performed on each block to obtain its bitmap.Then,by checking the parity of the number of horizontal edge transitions in the bitmap,we can extract one watermark bit in each block.Experimental results demonstrate that the proposed watermarking scheme is fragile to various image processing operations while keeping the transparency very well.     

一种多运动目标检测方法在FPGA上的实现

运动目标的检测已在众多的领域得到了广泛的应用,但是由于嵌入式处理器自身的速度限制,该应用主要集中在PC机上。使用一种改进的基于纹理的算法用于背景提取。采用高速的FPGA实现,通过对基于局部二元模式直方图算法的改进,使该算法适合硬件实现,通过一个图像块硬件结构的实现,在FPGA上同时实现12个图像块并行处理,使系统处理速度有了很大的提高。     

方块截短编码中同步消除噪声干扰的新算法

方块截短编码是图像压缩的一种有效技术.当图像未受到噪声干扰时,已有的算法都有较好的还原质量,当图像受到噪声干扰时,已有的算法都存在还原质量不佳的缺陷.若在编码前用去噪方法滤除噪声,则会在实际系统中大大增加硬件复杂度.为改善该状况,提出一种在图像编码的同时利用统计特性消除噪声干扰的算法.实验结果表明,在图像没有受到噪声干扰时应用该算法后与已有算法相比具有相同的图像还原质量,当图像受到噪声干扰时,应用该算法后的图像还原质量有明显的提高,且不会增加硬件复杂度.     

High-speed JPEG coder implementation for a smart camera

The compression standard of the Joint Photographic Experts Group (JPEG) for still images is used in many imaging applications. Although machine vision algorithms are based on raw images, massive data reduction of images in many applications is required additionally, e.g. to archive images in the context of automated visual inspection or to store high-speed image sequences when memory space is limited. Especially in embedded systems the software implementation of compression algorithms is too slow to meet real-time requirements. In this paper we present a fast implementation of a JPEG coder in a field programmable gate array (FPGA). This JPEG coder uses the architecture-specific function blocks of a low-cost FPGA (dedicated multipliers, block RAM). Nevertheless, there is hardly any limitation to the generality of the approach, as these building blocks are manufacturer-independent elements of up-to-date FPGA architectures.     

An FPGA-based implementation of corner detection and matching with outlier rejection

ABSTRACT

To meet the high frame rate requirements of correct point correspondences with a sub-pixel precision, this paper first proposes a Field Programmable Gate Array (FPGA) architecture that consists of corner detection, corner matching, outlier rejection, and sub-pixel precision localisation. In the architecture, a combined Features from Accelerated Segment Test (FAST)+ Binary Robust Independent Elementary Features (BRIEF) algorithm is adopted for detection and matching with pixel precision, a combined algorithm of Slope-based Rejection (SR) and Correlation-Coefficient-based Rejection (CCR) is used to reject the outliers, and a gradient centroid-based algorithm is used for sub-pixel precision localisation. The whole FPGA architecture is implemented on a single FPGA platform (Xilinx XC72K325T). Five image datasets with different spatial resolutions, textures, lights, rotate angles, and viewpoints are used to evaluate the performance of the FPGA-based implementation. The experimental results show that (1) the SR and CCR algorithms are effective for outlier rejection; (2) a higher correct matching rate is achieved for the image pairs that cover artificial textures than for those that cover natural textures; (3) the proposed architecture is also suitable for image pairs with small change of lights, rotate angles, and viewpoints; (4) the speed of the FPGA-based implementation can reach 280 Frames Per Second (FPS), which is 35 times faster than the Personal Computer (PC)-based implementation; and (5) the usage of FPGA resources is acceptable for the selected FPGA platform. The speed and usage of the FPGA resources can be improved when the whole FPGA-based implementation is further optimised.     

A secret sharing scheme for EBTC using steganography

In this paper, a new method based on Block Truncation Coding (BTC) and the halftoning technique is proposed for secret sharing of lossy compressed images. BTC is a simple and efficient image compression technique. However, it yields images of undesirable quality, and significant blocking effects are seen as the block size that is used increases. A modified method known as Enhanced Block Truncation Coding (EBTC) is proposed to solve these problems. For secret sharing, we propose a (2, 2) secret sharing scheme which provides authentication using DE scheme. This scheme was developed for data hiding with grayscale images, but our proposed EBTC uses bitmap images for which the DE scheme is not appropriate. We show the solution for such a problem. Moreover, we reduce the computation complexity for secret sharing using the DE algorithm because past schemes which used polynomial or interpolation algorithms require too much time for secret sharing. In addition, we show how to authenticate a cover image. Experimental results show that our proposed scheme provides secret sharing with proper authentication and acceptable computational complexity.     

基于矢量量化的高效BTC图像编码算法

作为一种有损图像编码技术,块截短编码算法（BTC）的计算量较少,速度快,有较好的信道容错力,重建图像质量较高。然而,标准BTC算法的主要缺点是其压缩比特率比其他基于块图像编码的算法（如变换编码和矢量量化）高。为了降低比特率,提出了几种有效的BTC算法,还提出了一种简单的查表算法对每块的BTC量化数据编码,另外还引入了矢量量化技术以减少对位平面编码的比特数。为了减少由改进算法引入的额外失真,在每种提出的算法中,采用最优阈值而不用平均值作为量化阈值。     

FPGA implementation of image processing technique for blood samples characterization

This work presents a hardware implementation of an image processing algorithm for blood type determination. The image processing technique proposed in this paper uses the appearance of agglutination to determine blood type by detecting edges and contrast within the agglutinated sample. An FPGA implementation and parallel processing algorithms are used in conjugation with image processing techniques to make this system reliable for the characterization of large numbers of blood samples. The program was developed using Matlab software then transferred and implemented on a Vertex 6 FPGA from Xilinx employing ISE software. Hardware implementation of the proposed algorithm on FPGA demonstrates a power consumption of 770 mW from a 2.5 V power supply. Blood type characterization using our FPGA implementation requires only 6.6 s, while a desktop computer-based algorithm with Matlab implementation on a Pentium 4 processor with a 3 GHz clock takes 90 s. The presented device is faster, more portable, less expensive, and consumes less power than conventional instruments. The proposed hardware solution achieved accuracy of 99.5% when tested with over 500 different blood samples.     

Design optimization of the quantization and a pipelined 2D-DCT for real-time applications

The Discrete Cosine Transform (DCT) is one of the most widely used techniques for image compression. Several algorithms are proposed to implement the DCT-2D. The scaled SDCT algorithm is an optimization of the DCT-1D, which consists in gathering all the multiplications at the end. In this paper, in addition to the hardware implementation on an FPGA, an extended optimization has been performed by merging the multiplications in the quantization block without having an impact on the image quality. A simplified quantization has been performed also to keep higher the performances of the all chain. Tests using MATLAB environment have shown that our proposed approach produces images with nearly the same quality of the ones obtained using the JPEG standard. FPGA-based implementations of this proposed approach is presented and compared to other state of the art techniques. The target is an an Altera Cyclone II FPGA using the Quartus synthesis tool. Results show that our approach outperforms the other ones in terms of processing-speed, used resources and power consumption. A comparison has been done between this architecture and a distributed arithmetic based architecture.     

A fast, FPGA-based MPEG-2 video encoder with a novel automatic quality control scheme

A novel video encoder that controls image quality on the fly is presented along with its FPGA implementation. As a result of this new feature, which uses a concept called pruning, the processing speed increases by a factor of two when compared to the conventional method of processing without pruning. The FPGA implementation conforms to MPEG-2 standards and is capable of processing color pictures of sizes up to 1024×768 pixels at the real time rate of 25 frames/s.     

Adaptive gradient-based block compressive sensing with sparsity for noisy images

This paper develops a novel adaptive gradient-based block compressive sensing (AGbBCS_SP) methodology for noisy image compression and reconstruction. The AGbBCS_SP approach splits an image into blocks by maximizing their sparsity, and reconstructs images by solving a convex optimization problem. In block compressive sensing, the commonly used square block shapes cannot always produce the best results. The main contribution of our paper is to provide an adaptive method for block shape selection, improving noisy image reconstruction performance. The proposed algorithm can adaptively achieve better results by using the sparsity of pixels to adaptively select block shape. Experimental results with different image sets demonstrate that our AGbBCS_SP method is able to achieve better performance, in terms of peak signal to noise ratio (PSNR) and computational cost, than several classical algorithms.

     

A Reconfigurable Logic-Based Processor for the SCAN Image and Video Encryption Algorithm

This paper presents a detailed architecture and a reconfigurable logic based hardware design of the SCAN algorithm. This architecture can be used to encrypt high resolution images in real-time. Although the SCAN algorithm is a block cipher algorithm with arbitrarily large blocks, the present design is for 64×64 pixel blocks in order to provide real-time image encryption throughput. The architecture was initially targeted at the Xilinx XCV-1000 FPGA, for which design and performance results are presented in the paper.     

基于DSP的图像压缩系统设计与算法研究

提出一种基于DSP和FPGA协同设计实现视频图像压缩的控制逻辑方案。由FPGA模块来实现图像采集,DSP模块进行编码压缩,同时针对块匹配算法中搜索精度与计算复杂度相关性问题,介绍了一种基于块匹配的量子行为的微粒群优化算法（Block Match Quantum-behaved Particle Swarm Optimization,BMQPSO）。在图像的实时压缩算法处理中,先对原始图像序列每一帧的宏块用微粒子进行搜索,再根据收敛性要求对压缩编码进行优化。实验结果表明该算法压缩效果优于经典搜索算法。     

Improving super-resolution mapping through combining multiple super-resolution land-cover maps

Super-resolution mapping (SRM) is an ill-posed problem, and different SRM algorithms may generate non-identical fine-spatial resolution land-cover maps (sub-pixel maps) from the same input coarse-spatial resolution image. The output sub-pixels maps may each have differing strengths and weaknesses. A multiple SRM (M-SRM) method that combines the sub-pixel maps obtained from a set of SRM analyses, obtained from a single or multiple set of algorithms, is proposed in this study. Plurality voting, which selects the class with the most votes, is used to label each sub-pixel. In this study, three popular SRM algorithms, namely, the pixel-swapping algorithm (PSA), the Hopfield neural network (HNN) algorithm, and the Markov random field (MRF)-based algorithm, were used. The proposed M-SRM algorithm was validated using two data sets: a simulated multispectral image and an Airborne Visible/Infrared Imaging Spectrometer (AVIRIS) hyperspectral image. Results show that the highest overall accuracies were obtained by M-SRM in all experiments. For example, in the AVIRIS image experiment, the highest overall accuracies of PSA, HNN, and MRF were 88.89, 93.81, and 82.70%, respectively, and these increased to 95.06, 95.37, and 85.56%, respectively for M-SRM obtained from the multiple PSA, HNN, and MRF analyses.