Study of electrical and micro-structural properties of high-κ gate dielectric stacks deposited using pulse laser deposition for MOS capacitor applications

The electrical properties of hafnium oxide (HfO₂) gate dielectric as a metal–oxide–semiconductor (MOS) capacitor structure deposited using pulse laser deposition (PLD) technique at optimum substrate temperatures in an oxygen ambient gas are investigated. The film thickness and microstructure are examined using ellipsometer and atomic force microscope (AFM), respectively to see the effect of substrate temperatures on the device properties. The electrical J–V, C–V characteristics of the dielectric films are investigated employing Al–HfO₂–Si MOS capacitor structure. The important parameters like leakage current density, flat-band voltage (V_fb) and oxide-charge density (Q_ox) for MOS capacitors are extracted and investigated for optimum substrate temperature. Further, electrical studies of these MOS capacitors have been carried out by incorporating La₂O₃ into HfO₂ to fabricate HfO₂/La₂O₃ dielectric stacks at an optimized substrate temperature of 800 °C using a PLD deposition technique under oxygen ambient. These Al–HfO₂–La₂O₃–Si dielectric stacks MOS capacitor structure are found to possess better electrical properties than that of HfO₂ based MOS capacitors using the PLD deposition technique.     

Electrical properties of nickel electrodes for high-k MOS structures

Together with high-κ dielectric films, metal gate electrodes have to be employed in advanced CMOS technologies. The metal gate material should be carefully selected with respect to work function, stability of metal-dielectric stack and compatibility with the CMOS process. In our investigation Ni gate electrodes grown on thermal SiO₂, atomic-layer deposition HfO₂ and Al₂O₃ dielectric films have been analyzed by means of high-frequency capacitance-voltage measurement on MOS capacitors. Ni gate materials were prepared by RF diode sputter deposition. Work function of the investigated gate material and density of effective defect charge of the gate oxide film were extracted from the measurements. These properties are discussed with regard to application of Ni metal gates in CMOS technology.     

Dielectrics for Field Effect Technology

The availability of stable MOS gate systems and high density storage capacitors is an essential requirement for the development of the field effect storage technology. For standard MOSFET gates this role has been fulfilled by SiO₂ grown by thermal oxidation of the Si substrate. Improved insight into the properties of the Si/Si0₂ system and perfection of its growth technology will secure its role in Si MOSFET memories for the future. For charge storage application the stability requirements are less demanding. However, here SiO₂ is not able to provide sufficient capacity. In this case higher dielectric constant materials (Si₃N₄ or Ta₂O₅) have to take over. Particularly attractive appears the use of ferroelectrics. These dielectric materials not only offer a high dielectric constant, but also the perspective of providing non-volatile storage in capacitor structures.     

Study of temperature dependence of positive charge generation in thin dielectric film of MOS structure under high-fields

In this work, the temperature effect on positive charge generation under high-field electron injection in MOS structures is studied using a new multilevel current stress technique. In our experiments, we used commercially made test MOS capacitors based on thermal silicon dioxide film with thickness in the range from 7 to 100 nm. Using the proposed multilevel current stress technique one can investigate the positive charge generation in MOS structure gate dioxide under high electric fields. The technique is different from the standard constant current stress technique, as it includes two levels of current: the stress current level, which provides the generation of positive charge, and the additional measuring current level, which allows to monitor the change of dielectric charge. Due to the additional measuring current level, it is possible to decrease significantly the error of positive charge density measurement in the dielectric. The latter error is caused by the positive charge trapped in the initial stage of electron injection while the steady-state of the stress mode is being reached. It was found that the rise of sample temperature leads to a decrease of the density of the positive charge generated in SiO₂ film under high-field injection of electrons from the silicon substrate. A model of the positive charge generation in MOS structures under high-field electron injection has been proposed. The new model of the positive charge generation in MOS structures takes into account the temperature effect and the subsequent phenomena of dielectric charge state change: the band-to-band impact ionization in SiO₂ with the creation of electron-hole pairs and the subsequent trapping of holes in traps in the oxide; the trapping of injected electrons by trapped holes as well as the thermal release of trapped holes from the traps.     

Stability of pentacene organic field effect transistors with a low-k polymer/high-k oxide two-layer gate dielectric

This paper reports on the processing and the characterization of pentacene organic field effect transistors (OFETs) with a two-layer gate dielectric consisting of a polymer (PMMA) on a high-k oxide (Ta₂O₅). This dielectric stack has been designed in view to combine low voltage operating devices, by the use of a high-k oxide which increases the charge in the accumulation channel and the gate capacitance, and highly stable devices which generally could be achieved with polymer dielectrics but not necessarily with strongly polar high-k oxides. Bi-layer dielectric devices were compared to those with only Ta₂O₅ or PMMA gate insulators. Bias stress at room temperature was used to assess the electrical stability. A very low operating voltage was achieved with Ta₂O₅ but these devices exhibit hysteresis and degraded characteristics upon bias stress. OFETs with PMMA revealed very stable but operate at rather a high voltage due to the low dielectric constant of PMMA. Reasonably stable devices operating at about 10 V could have been obtained with PMMA/Ta₂O₅ two-layer dielectric. The origin of observed threshold voltage shift and mobility decrease upon bias stress are discussed.     

Study of reactive sputtering titanium oxide for metal-oxide-semiconductor capacitors

Metal oxide semiconductor (MOS) capacitors with titanium oxide (TiO_x) dielectric layer, deposited with different oxygen partial pressure (30, 35 and 40%) and annealed at 550, 750 and 1000 °C, were fabricated and characterized.Capacitance-voltage and current-voltage measurements were utilized to obtain, the effective dielectric constant, effective oxide thickness, leakage current density and interface quality. The obtained TiO_x films present a dielectric constant varying from 40 to 170 and a leakage current density, for a gate voltage of − 1 V, as low as 1 nA/cm² for some of the structures, acceptable for MOS fabrication, indicating that this material is a viable high dielectric constant substitute for current ultra thin dielectric layers.     

Structural, optical and electrical properties of high-k ZrO2 dielectrics on Si prepared by plasma assisted pulsed laser deposition

ZrO₂ films were grown on p-type Si(100) using plasma assisted pulsed laser deposition and the electrical characteristics of the ZrO₂ dielectrics incorporated in metal oxide silicon (MOS) capacitors were studied in combination with their structural and optical properties. The ZrO₂ dielectric layers are of polycrystalline structure with a monoclinic phase and show good interfacial properties without obvious SiO_x interface. The electrical performance of the capacitors exhibits typical MOS-type capacitance-voltage (C-V) and leakage current density-voltage (J-V) characteristics. Thermal annealing of the ZrO₂ dielectrics results in an improvement in C-V and J-V characteristics and a reduction in C-V hysteresis without obvious introduction of leakage paths for the fabricated MOS capacitors. The dielectric constant was calculated to be 15.4 and the leakage current density was measured to be 6.7 × 10^− 6 A/cm² at a gate voltage of + 1.0 V for 900 °C annealed ZrO₂ dielectric layers with an equivalent oxide thickness of 5.2 nm.     

Dielectric properties of Y2O3 donor-doped Ba0.8Sr0.2TiO3 ceramics

Ba_0.8Sr_0.2TiO₃ ceramics doped with Y₂O₃ from 0 to 0.10 mol% exhibit normal ferroelectric phase transition, while the ceramics doped with Y₂O₃ from 0.20 to 0.30 mol% show a giant dielectric constant behavior with loss less than 0.15 at 1 kHz from −40 °C to 140 °C, which is suggested due to semiconductive grain and the Maxwell–Wagner effect by structure disordering in grain boundary. The analyses of unipolar charge for the semiconductive grain indicate three kinds of dielectric processes: thermally stimulated process of unipolar hopping, dispersion process of dielectric constant with frequency, and phase transition process accompanied with disappearance of giant dielectric constant in cubic phase. The XPS results confirm that some of the barium ions are in low energy state to form e-Ba²⁺ and to provide hopping sites for electrons. The ceramics doped with Y₂O₃ from 0.50 to 0.75 mol% recover the normal ferroelectricity. The possible mechanics are relevant to binding effect of cation vacancies on electrons.     

Electrical properties of pulsed laser deposited Bi<Subscript>2</Subscript>Zn<Subscript>2/3</Subscript>Nb<Subscript>4/3</Subscript>O<Subscript>7</Subscript> thin films for high K gate dielectric application

Metal Insulator Semiconductor (MIS) capacitors with monoclinic bismuth zinc niobate pyrocholre having the composition Bi2Zn2_/3Nb_4/3O₇ (m-BZN) dielectric layer were fabricated and characterized. Capacitance voltage (C–V) and current voltage measurements were utilized to obtain the dielectric properties, leakage current density and interface quality. The results shows that the obtained m-BZN thin films presents a high dielectric constant in between 30 and 70, a good interface quality with silicon and a leakage current density of 10 μA/cm² for a field strength of 100 kV/cm which is acceptable for high performance logic circuits. The equilent oxide thickness for the films annealed at 200 °C was 10 nm. These results suggest that m-BZN thin films can be potentially integrated as gate dielectric materials in CMOS technology.     

Current conduction mechanisms in HfO2 and SrHfON thin films prepared by magnetron sputtering

Metal–oxide–semiconductor (MOS) capacitors incorporating HfO₂ and SrHfON gate dielectrics were fabricated by magnetron sputtering. The interface quality, thermal stability, and electrical properties of the MOS capacitors have been investigated. Compared to HfO₂ dielectric film, SrHfON dielectric film has thin interface layer with Si substrate, good thermal stability, and low leakage current densities. The dominant current conduction mechanisms (CCMs) of HfO₂ film are Schottky emission or Poole–Frenkel emission at low and high electric fields. The main CCMs of SrHfON film are Schottky emission or Poole–Frenkel emission at low electric field, whereas, the CCMs are replaced by space charge limited current at high electric field.     

Atomic-layer-deposited (ALD) Al_2O_3passivation dependent interface chemistry,band alignment and electrical properties of HfYO/Si gate stacks

In this work, the effects of atomic-layer-deposited(ALD) Al_2O_3 passivation layers with different thicknesses on the interface chemistry and electrical properties of sputtering-derived HfYO gate dielectrics on Si substrates have been investigated. The results of electrical measurements and X-ray photoelectron sepectroscopy(XPS) showed that 1-nm-thick Al_2O_3 passivation layer is optimized to obtain excellent electrical and interfacial properties for HfYO/Si gate stack. Then, the metal-oxide-semiconductor capacitors with HfYO/1-nm Al_2O_3/Si/Al gate stack were fabricated and annealed at different temperatures in forming gas(95% N_2+5% H_2). Capacitance-voltage(C-V) and current density-voltage(J-V) characteristics showed that the 250℃-annealed HYO high-k gate dielectric thin film demonstrated the lowest border trapped oxide charge density(-3.3 × 10~(10) cm~(-2)), smallest gate-leakage current(2.45 × 10~(-6) A/cm~2 at 2 V)compared with other samples. Moreover, the annealing temperature dependent leakage current conduction mechanism for Al/HfYO/Al_2O_3/Si/Al MOS capacitor has been investigated systematically. Detailed electrical measurements reveal that Poole-Frenkle emission is the main dominant emission in the region of low and medium electric fields while direct tunneling is dominant conduction mechanism at high electric fields.     

The influence of oxygen ambient annealing conditions on the quality of Al/SiO2/n-type 4H-SiC MOS structure

The effect of reoxidation process in O₂ on the electrical properties of metal-oxide-semiconductor (MOS) capacitors fabricated on n-type 4H-SiC (0 0 0 1) is investigated. All samples were oxidized in wet oxygen at temperature of 1175 °C. Reoxidation process was carried out on four of the five samples. Samples were annealed at temperature of 700 °C and 800 °C for different process times. The reoxidation process in oxygen improves the quality of the dielectric layer and the interface of Al/SiO₂/n-type 4H-SiC MOS structure. The best quality of the SiO₂/SiC interface can be achieved for the MOS structure annealed in O₂ at higher temperature (800 °C) for longer time. However, higher and more uniformly distributed values of breakdown voltage were obtained for MOS structures reoxidized at temperature of 700 °C.     

Structural and electrical properties of Ta<Subscript><Emphasis Type="Bold">2</Emphasis></Subscript>O<Subscript><Emphasis Type="Bold">5</Emphasis></Subscript> thin films prepared by photo-induced CVD

Tantalum oxide (Ta ₂ O ₅ ) films and Al/Ta ₂ O ₅ /Si MOS capacitors were prepared at various powers by ultraviolet photo-inducing hot filament chemical vapour deposition (HFCVD). Effects of ultraviolet light powers on the structure and electrical properties of Ta ₂ O ₅ thin films were studied using X-ray diffraction (XRD) and atomic force microscopy (AFM). The dielectric constant, leakage current density and breakdown electric field of the samples were studied by the capacitance–voltage (C–V) and current–voltage (I–V) measurements of the Al/Ta ₂ O ₅ /Si MOS capacitors. Results show that the Ta ₂ O ₅ thin films grown without inducement of UV light belong to amorphous phase, whereas the samples grown with inducement of UV-light belong to δ-Ta ₂ O ₅ phase. The dielectric constant and leakage current density of the Ta ₂ O ₅ thin films increase with increasing powers of the UV- lamps. Effects of UV- lamp powers on the structural and electrical properties were discussed.     

Structural and electronic properties of polyaniline/yittrium oxide composites

Composites of polyaniline with yttrium oxide (Y₂O₃) have been synthesized by chemical polymerization method. The structural properties of synthesized Polyaniline (PANI) and PANI/Y₂O₃ were studied by X-ray diffraction (XRD) analysis. XRD pattern indicate that PANI is intercalated into the layers of Y₂O₃ successfully and therefore the degree of crystallinity increases due to crystalline of Y₂O₃. Fourier transform infrared (FT-IR) indicated that there is a strong interaction between PANI and Y₂O₃. Electronic properties (Dielectric and Conductivity) of PANI and PANI/Y₂O₃ composite have been investigated between frequency ranges of 1 MHz and 3.0 GHz. Higher dielectric constants and dielectric losses of PANI/Y₂O₃ composites than those of Synthesis PANI were found. As the content of Y₂O₃ increased, the dielectric constant and loss also increased. The value of dielectric constant (ε/) for all PANI/Y₂O₃ composite is very high at low frequency but decreases with the increases of frequency. PANI/Y₂O₃ composite materials with high dielectric constants are highly desirable for use in charge-storage devices.     

Investigation of reliability measurements with ramped and constant voltage stress on mos gate oxides

MOS gate oxide capacitors over a wide range of oxide thicknesses (10·9–28nm) were stressed using constant voltage, ramped voltage stress and combined ramped/constant voltage stress measurements. The reliability measurements were performed with different bias conditions in order to assess the effect of the measurement conditions on the gate oxide lifetimes. A unipolar pulsed ramp was applied during the ramped voltage stress. It will be verified that this ramp yields identical breakdown distributions to the commonly used staircase ramp. Times to breakdown from ramped and constant voltage stress were directly compared. It was found that for thick oxides the times to breakdown of the ramped stress were greater than those of the constant stress. The measurement results of the combined ramped/constant voltage stress indicate that it is a valuable tool for monitoring extrinsic and intrinsic breakdown properties. The observations made in this work imply that the time to breakdown at a constant voltage is strongly dependent on the peak current injected into the oxide and, therefore, on a pre-stress before the constant stress voltage.     

Dielectric behavior and energy storage properties in BaO–SrO–Nb2O5–B2O3 system glass–ceramics with Gd2O3 addition

A series of strontium barium niobate-based borate system glass–ceramics with Gd₂O₃ addition have been prepared by controlled crystallization method. The effect of Gd₂O₃ addition on the microstructure, phase evolution and dielectric properties has been investigated. The results show that the addition of Gd₂O₃ to the glass–ceramics changes the dielectric property and energy-storage density. Typically, the glass–ceramics with 0.5 mol% Gd₂O₃ heat treated at 630 °C/2 h + 800 °C/3 h possesses a dielectric constant of 136, a breakdown strength of 1,075 kV/mm and energy-storage density of 6.94 J/cm³, which is suitable for the application in high energy-storage capacitors.     

Enhanced leakage current behavior of Sr2Ta2O7−x/SrTiO3 bilayer dielectrics for metal-insulator-metal capacitors

Metal-Insulator-Metal (MIM) capacitors are one of the most essential components of radio frequency devices and analog/mixed-signal integrated circuits. In order to obtain high capacitance densities in MIM devices, high-k materials have been considered to be promising candidates to replace the traditional insulators. The challenging point is that the dielectric material must demonstrate high capacitance density values with low leakage current densities.In this work, SrTiO₃ based MIM capacitors have been investigated and the electrical performance of the devices have been optimized by using bilayered systems of Sr₂Ta₂O_7−x/SrTiO₃ with different thicknesses of Sr₂Ta₂O_7−x. Sputtering X-Ray photoelectron spectroscopy (XPS) measurements have been applied to investigate the interfaces between the thin film constituents of the MIM stacks. The optimized bilayered system provides a leakage current density of 8∗10^− 8 A/cm² at 2 V (bottom electrode injection) and a high capacitance density of 13 fF/μm².     

Microstructure and electrical properties of Al2O3-ZrO2 composite films for gate dielectric applications

Al₂O₃-ZrO₂ composite films were fabricated on Si by ultrahigh vacuum electron-beam coevaporation. The crystallization temperature, surface morphology, structural characteristics and electrical properties of the annealed films are investigated. Our results indicate that the amorphous and mixed structure is maintained up to an annealing temperature of 900 °C, which is much higher than that of pure ZrO₂ film, and the interfacial oxide layer thickness does not increase after annealing at 900 °C. However, a portion of the Al₂O₃-ZrO₂ film becomes polycrystalline after 1000 °C annealing and interfacial broadening is observed. Possible explanations are given to explain our observations. A dielectric constant of 20.1 is calculated from the 900 °C-annealed ZrO₂-Al₂O₃ film based on high-frequency capacitance-voltage measurements. This dielectric characteristic shows an equivalent oxide thickness (EOT) as low as 1.94 nm. An extremely low leakage current density of ∼2×10⁻⁷ A/cm² at a gate voltage of 1 V and low interface state density are also observed in the dielectric film.     

Tunneling currents through ultra thin HfO2/Al2O3/HfO2 triple layer gate dielectrics for advanced MIS devices

The dramatic scaling down of silicon integrated circuits has led to an intensive study of high dielectric constant materials as an alternative to the conventional insulators currently employed in microelectronics, i.e., silicon dioxide, silicon nitride, or oxynitride, which seem to have reached their physical limit in terms of reduction of thickness due to large leakage gate current. Introducing a physically thicker high-K material can reduce the leakage current to the acceptable limit. There are many potential candidates for high-K gate dielectrics with the K-valves ranging from 9 to 80. These are Al₂O₃, Y₂O₃, La₂O₃, Ta₂O₅, TiO₂, ZrO₂ and HfO₂. It is important to study the various leakage mechanisms in these films with the aim of improving their leakage current characteristics for use in advanced microelectronics devices. A procedure for calculating the tunneling current for stacked dielectrics is developed and subsequently applied to ultra thin films with equivalent oxide thickness (EOT) of 3.0 nm. Tunneling currents have been calculated as a function of gate voltage for different structures. Direct and Fowler-Nordheim tunneling currents through triple layer dielectrics are investigated for substrate injection. Using exact tunneling transmission calculations, current density–gate voltage (J _g?V _g) characteristics for ultra thin single layer gate dielectrics with different thicknesses have been shown to agree well with recently reported experiments. Extensions of this approach demonstrate that tunneling currents in HfO₂/Al₂O₃/HfO₂ structure with equivalent oxide thickness of 3.0 nm can be significantly lower than that through single layer oxides of the same thickness.     

Hysteresis in metal insulator semiconductor structures with high temperature annealed ZrO2/SiOx layers

Hysteresis behaviour in sandwich structure — zirconium oxide/chemical silicon oxide, annealed at temperature of 850 °C in oxygen ambient, was studied. Formation of thin ZrSi_xO_y layer due to the high temperature annealing was found. Metal-insulator-semiconductor (MIS) capacitors using ZrO₂/ZrSi_xO_y/SiO_x insulator were studied. High-frequency capacitance-voltage (HF C-V), current-voltage (I-V) and current-time (I-t) measurements were carried out on the Al/ZrO₂/ZrSi_xO_y/SiO_x/Si capacitors.Two leakage current components were identified — tunneling current component at high electric fields and transient current component at low fields. The transient leakage currents are due to charge trapping phenomena. The measured I-t characteristics are related with charging/discharging and dielectric relaxation phenomena. A counter-clockwise HF C-V hysteresis, larger than 2 V at thickness of the stack structure of about 50 nm was observed.Metal-insulator-semiconductor field effect transistors (MISFETs) using ZrO₂/ZrSi_xO_y/SiO_x-gate insulator were studied. P-channel MISFETs with aluminum gate electrode were fabricated on standard n-type silicon substrates. Due to charging/discharging phenomena in the gate dielectric the transistors can be switched between On- and Off-state with the polarity of applied stress voltage.